/*
 ***********************************************************************************************************************
 *
 *  Copyright (c) 2014-2021 Advanced Micro Devices, Inc. All Rights Reserved.
 *
 *  Permission is hereby granted, free of charge, to any person obtaining a copy
 *  of this software and associated documentation files (the "Software"), to deal
 *  in the Software without restriction, including without limitation the rights
 *  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 *  copies of the Software, and to permit persons to whom the Software is
 *  furnished to do so, subject to the following conditions:
 *
 *  The above copyright notice and this permission notice shall be included in all
 *  copies or substantial portions of the Software.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 *  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 *  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 *  SOFTWARE.
 *
 **********************************************************************************************************************/

#if !defined (SI_CI_VI_PI_MERGED_TYPEDEF_HEADER)
#define SI_CI_VI_PI_MERGED_TYPEDEF_HEADER

#include "si_ci_vi_merged_registers.h"

namespace Pal
{
namespace Gfx6
{
inline namespace Chip
{
typedef union ABM_TEST_DEBUG_DATA__SI__VI      regABM_TEST_DEBUG_DATA__SI__VI;
typedef union ABM_TEST_DEBUG_INDEX__SI__VI     regABM_TEST_DEBUG_INDEX__SI__VI;
typedef union ACP_CONFIG__CI                   regACP_CONFIG__CI;
typedef union ADAPTER_ID                       regADAPTER_ID;
typedef union ADAPTER_ID_W                     regADAPTER_ID_W;
typedef union AFMT_60958_0__SI__VI             regAFMT_60958_0__SI__VI;
typedef union AFMT_60958_1__SI__VI             regAFMT_60958_1__SI__VI;
typedef union AFMT_60958_2__SI__VI             regAFMT_60958_2__SI__VI;
typedef union AFMT_AUDIO_CRC_CONTROL__SI__VI   regAFMT_AUDIO_CRC_CONTROL__SI__VI;
typedef union AFMT_AUDIO_CRC_RESULT__SI__VI    regAFMT_AUDIO_CRC_RESULT__SI__VI;
typedef union AFMT_AUDIO_INFO0__SI__VI         regAFMT_AUDIO_INFO0__SI__VI;
typedef union AFMT_AUDIO_INFO1__SI__VI         regAFMT_AUDIO_INFO1__SI__VI;
typedef union AFMT_AUDIO_PACKET_CONTROL2__SI   regAFMT_AUDIO_PACKET_CONTROL2__SI;
typedef union AFMT_AUDIO_PACKET_CONTROL2__VI   regAFMT_AUDIO_PACKET_CONTROL2__VI;
typedef union AFMT_AUDIO_PACKET_CONTROL__SI    regAFMT_AUDIO_PACKET_CONTROL__SI;
typedef union AFMT_AUDIO_PACKET_CONTROL__VI    regAFMT_AUDIO_PACKET_CONTROL__VI;
typedef union AFMT_AVI_INFO0__SI__VI           regAFMT_AVI_INFO0__SI__VI;
typedef union AFMT_AVI_INFO1__SI__VI           regAFMT_AVI_INFO1__SI__VI;
typedef union AFMT_AVI_INFO2__SI__VI           regAFMT_AVI_INFO2__SI__VI;
typedef union AFMT_AVI_INFO3__SI__VI           regAFMT_AVI_INFO3__SI__VI;
typedef union AFMT_INFOFRAME_CONTROL0__SI__VI  regAFMT_INFOFRAME_CONTROL0__SI__VI;
typedef union AFMT_ISRC1_0__SI__VI             regAFMT_ISRC1_0__SI__VI;
typedef union AFMT_ISRC1_1__SI__VI             regAFMT_ISRC1_1__SI__VI;
typedef union AFMT_ISRC1_2__SI__VI             regAFMT_ISRC1_2__SI__VI;
typedef union AFMT_ISRC1_3__SI__VI             regAFMT_ISRC1_3__SI__VI;
typedef union AFMT_ISRC1_4__SI__VI             regAFMT_ISRC1_4__SI__VI;
typedef union AFMT_ISRC2_0__SI__VI             regAFMT_ISRC2_0__SI__VI;
typedef union AFMT_ISRC2_1__SI__VI             regAFMT_ISRC2_1__SI__VI;
typedef union AFMT_ISRC2_2__SI__VI             regAFMT_ISRC2_2__SI__VI;
typedef union AFMT_ISRC2_3__SI__VI             regAFMT_ISRC2_3__SI__VI;
typedef union AFMT_MPEG_INFO0__SI__VI          regAFMT_MPEG_INFO0__SI__VI;
typedef union AFMT_MPEG_INFO1__SI__VI          regAFMT_MPEG_INFO1__SI__VI;
typedef union AFMT_RAMP_CONTROL0__SI__VI       regAFMT_RAMP_CONTROL0__SI__VI;
typedef union AFMT_RAMP_CONTROL1__SI__VI       regAFMT_RAMP_CONTROL1__SI__VI;
typedef union AFMT_RAMP_CONTROL2__SI__VI       regAFMT_RAMP_CONTROL2__SI__VI;
typedef union AFMT_RAMP_CONTROL3__SI__VI       regAFMT_RAMP_CONTROL3__SI__VI;
typedef union AFMT_STATUS__SI                  regAFMT_STATUS__SI;
typedef union AFMT_STATUS__VI                  regAFMT_STATUS__VI;
typedef union AFMT_VBI_PACKET_CONTROL__SI__VI  regAFMT_VBI_PACKET_CONTROL__SI__VI;
typedef union ATC_ATS_CNTL__CI__VI             regATC_ATS_CNTL__CI__VI;
typedef union ATC_ATS_DEBUG__CI__VI            regATC_ATS_DEBUG__CI__VI;
typedef union ATC_ATS_DEFAULT_PAGE_CNTL__CI__VI regATC_ATS_DEFAULT_PAGE_CNTL__CI__VI;
typedef union ATC_ATS_DEFAULT_PAGE_LOW__CI     regATC_ATS_DEFAULT_PAGE_LOW__CI;
typedef union ATC_ATS_DEFAULT_PAGE_LOW__VI     regATC_ATS_DEFAULT_PAGE_LOW__VI;
typedef union ATC_ATS_FAULT_CNTL__CI__VI       regATC_ATS_FAULT_CNTL__CI__VI;
typedef union ATC_ATS_FAULT_DEBUG__CI__VI      regATC_ATS_FAULT_DEBUG__CI__VI;
typedef union ATC_ATS_FAULT_STATUS_ADDR__CI__VI regATC_ATS_FAULT_STATUS_ADDR__CI__VI;
typedef union ATC_ATS_FAULT_STATUS_INFO__CI__VI regATC_ATS_FAULT_STATUS_INFO__CI__VI;
typedef union ATC_ATS_STATUS__CI__VI           regATC_ATS_STATUS__CI__VI;
typedef union ATC_L1RD_DEBUG_TLB__CI__VI       regATC_L1RD_DEBUG_TLB__CI__VI;
typedef union ATC_L1RD_STATUS__CI__VI          regATC_L1RD_STATUS__CI__VI;
typedef union ATC_L1WR_DEBUG_TLB__CI__VI       regATC_L1WR_DEBUG_TLB__CI__VI;
typedef union ATC_L1WR_STATUS__CI__VI          regATC_L1WR_STATUS__CI__VI;
typedef union ATC_L1_ADDRESS_OFFSET__CI__VI    regATC_L1_ADDRESS_OFFSET__CI__VI;
typedef union ATC_L1_CNTL__CI__VI              regATC_L1_CNTL__CI__VI;
typedef union ATC_L2_CNTL2__CI__VI             regATC_L2_CNTL2__CI__VI;
typedef union ATC_L2_CNTL__CI__VI              regATC_L2_CNTL__CI__VI;
typedef union ATC_L2_DEBUG2__CI                regATC_L2_DEBUG2__CI;
typedef union ATC_L2_DEBUG2__VI                regATC_L2_DEBUG2__VI;
typedef union ATC_L2_DEBUG__CI__VI             regATC_L2_DEBUG__CI__VI;
typedef union ATC_MISC_CG__CI__VI              regATC_MISC_CG__CI__VI;
typedef union ATC_PERFCOUNTER0_CFG__CI__VI     regATC_PERFCOUNTER0_CFG__CI__VI;
typedef union ATC_PERFCOUNTER1_CFG__CI__VI     regATC_PERFCOUNTER1_CFG__CI__VI;
typedef union ATC_PERFCOUNTER2_CFG__CI__VI     regATC_PERFCOUNTER2_CFG__CI__VI;
typedef union ATC_PERFCOUNTER3_CFG__CI__VI     regATC_PERFCOUNTER3_CFG__CI__VI;
typedef union ATC_PERFCOUNTER_HI__CI__VI       regATC_PERFCOUNTER_HI__CI__VI;
typedef union ATC_PERFCOUNTER_LO__CI__VI       regATC_PERFCOUNTER_LO__CI__VI;
typedef union ATC_PERFCOUNTER_RSLT_CNTL__CI__VI regATC_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union ATC_VMID0_PASID_MAPPING__CI__VI  regATC_VMID0_PASID_MAPPING__CI__VI;
typedef union ATC_VMID10_PASID_MAPPING__CI__VI regATC_VMID10_PASID_MAPPING__CI__VI;
typedef union ATC_VMID11_PASID_MAPPING__CI__VI regATC_VMID11_PASID_MAPPING__CI__VI;
typedef union ATC_VMID12_PASID_MAPPING__CI__VI regATC_VMID12_PASID_MAPPING__CI__VI;
typedef union ATC_VMID13_PASID_MAPPING__CI__VI regATC_VMID13_PASID_MAPPING__CI__VI;
typedef union ATC_VMID14_PASID_MAPPING__CI__VI regATC_VMID14_PASID_MAPPING__CI__VI;
typedef union ATC_VMID15_PASID_MAPPING__CI__VI regATC_VMID15_PASID_MAPPING__CI__VI;
typedef union ATC_VMID1_PASID_MAPPING__CI__VI  regATC_VMID1_PASID_MAPPING__CI__VI;
typedef union ATC_VMID2_PASID_MAPPING__CI__VI  regATC_VMID2_PASID_MAPPING__CI__VI;
typedef union ATC_VMID3_PASID_MAPPING__CI__VI  regATC_VMID3_PASID_MAPPING__CI__VI;
typedef union ATC_VMID4_PASID_MAPPING__CI__VI  regATC_VMID4_PASID_MAPPING__CI__VI;
typedef union ATC_VMID5_PASID_MAPPING__CI__VI  regATC_VMID5_PASID_MAPPING__CI__VI;
typedef union ATC_VMID6_PASID_MAPPING__CI__VI  regATC_VMID6_PASID_MAPPING__CI__VI;
typedef union ATC_VMID7_PASID_MAPPING__CI__VI  regATC_VMID7_PASID_MAPPING__CI__VI;
typedef union ATC_VMID8_PASID_MAPPING__CI__VI  regATC_VMID8_PASID_MAPPING__CI__VI;
typedef union ATC_VMID9_PASID_MAPPING__CI__VI  regATC_VMID9_PASID_MAPPING__CI__VI;
typedef union ATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI regATC_VMID_PASID_MAPPING_UPDATE_STATUS__CI__VI;
typedef union ATC_VM_APERTURE0_CNTL2__CI__VI   regATC_VM_APERTURE0_CNTL2__CI__VI;
typedef union ATC_VM_APERTURE0_CNTL__CI__VI    regATC_VM_APERTURE0_CNTL__CI__VI;
typedef union ATC_VM_APERTURE0_HIGH_ADDR__CI__VI regATC_VM_APERTURE0_HIGH_ADDR__CI__VI;
typedef union ATC_VM_APERTURE0_LOW_ADDR__CI__VI regATC_VM_APERTURE0_LOW_ADDR__CI__VI;
typedef union ATC_VM_APERTURE1_CNTL2__CI__VI   regATC_VM_APERTURE1_CNTL2__CI__VI;
typedef union ATC_VM_APERTURE1_CNTL__CI__VI    regATC_VM_APERTURE1_CNTL__CI__VI;
typedef union ATC_VM_APERTURE1_HIGH_ADDR__CI__VI regATC_VM_APERTURE1_HIGH_ADDR__CI__VI;
typedef union ATC_VM_APERTURE1_LOW_ADDR__CI__VI regATC_VM_APERTURE1_LOW_ADDR__CI__VI;
typedef union ATTR00__SI__VI                   regATTR00__SI__VI;
typedef union ATTR01__SI__VI                   regATTR01__SI__VI;
typedef union ATTR02__SI__VI                   regATTR02__SI__VI;
typedef union ATTR03__SI__VI                   regATTR03__SI__VI;
typedef union ATTR04__SI__VI                   regATTR04__SI__VI;
typedef union ATTR05__SI__VI                   regATTR05__SI__VI;
typedef union ATTR06__SI__VI                   regATTR06__SI__VI;
typedef union ATTR07__SI__VI                   regATTR07__SI__VI;
typedef union ATTR08__SI__VI                   regATTR08__SI__VI;
typedef union ATTR09__SI__VI                   regATTR09__SI__VI;
typedef union ATTR0A__SI__VI                   regATTR0A__SI__VI;
typedef union ATTR0B__SI__VI                   regATTR0B__SI__VI;
typedef union ATTR0C__SI__VI                   regATTR0C__SI__VI;
typedef union ATTR0D__SI__VI                   regATTR0D__SI__VI;
typedef union ATTR0E__SI__VI                   regATTR0E__SI__VI;
typedef union ATTR0F__SI__VI                   regATTR0F__SI__VI;
typedef union ATTR10__SI__VI                   regATTR10__SI__VI;
typedef union ATTR11__SI__VI                   regATTR11__SI__VI;
typedef union ATTR12__SI__VI                   regATTR12__SI__VI;
typedef union ATTR13__SI__VI                   regATTR13__SI__VI;
typedef union ATTR14__SI__VI                   regATTR14__SI__VI;
typedef union ATTRDR__SI__VI                   regATTRDR__SI__VI;
typedef union ATTRDW__SI__VI                   regATTRDW__SI__VI;
typedef union ATTRX__SI__VI                    regATTRX__SI__VI;
typedef union AUDIO_DESCRIPTOR0__SI__VI        regAUDIO_DESCRIPTOR0__SI__VI;
typedef union AUDIO_DESCRIPTOR10__SI__VI       regAUDIO_DESCRIPTOR10__SI__VI;
typedef union AUDIO_DESCRIPTOR11__SI__VI       regAUDIO_DESCRIPTOR11__SI__VI;
typedef union AUDIO_DESCRIPTOR12__SI__VI       regAUDIO_DESCRIPTOR12__SI__VI;
typedef union AUDIO_DESCRIPTOR13__SI__VI       regAUDIO_DESCRIPTOR13__SI__VI;
typedef union AUDIO_DESCRIPTOR1__SI__VI        regAUDIO_DESCRIPTOR1__SI__VI;
typedef union AUDIO_DESCRIPTOR2__SI__VI        regAUDIO_DESCRIPTOR2__SI__VI;
typedef union AUDIO_DESCRIPTOR3__SI__VI        regAUDIO_DESCRIPTOR3__SI__VI;
typedef union AUDIO_DESCRIPTOR4__SI__VI        regAUDIO_DESCRIPTOR4__SI__VI;
typedef union AUDIO_DESCRIPTOR5__SI__VI        regAUDIO_DESCRIPTOR5__SI__VI;
typedef union AUDIO_DESCRIPTOR6__SI__VI        regAUDIO_DESCRIPTOR6__SI__VI;
typedef union AUDIO_DESCRIPTOR7__SI__VI        regAUDIO_DESCRIPTOR7__SI__VI;
typedef union AUDIO_DESCRIPTOR8__SI__VI        regAUDIO_DESCRIPTOR8__SI__VI;
typedef union AUDIO_DESCRIPTOR9__SI__VI        regAUDIO_DESCRIPTOR9__SI__VI;
typedef union AUXN_IMPCAL__SI                  regAUXN_IMPCAL__SI;
typedef union AUXN_IMPCAL__VI                  regAUXN_IMPCAL__VI;
typedef union AUXP_IMPCAL__SI                  regAUXP_IMPCAL__SI;
typedef union AUXP_IMPCAL__VI                  regAUXP_IMPCAL__VI;
typedef union AUX_ARB_CONTROL__SI__VI          regAUX_ARB_CONTROL__SI__VI;
typedef union AUX_CONTROL__SI__VI              regAUX_CONTROL__SI__VI;
typedef union AUX_DPHY_RX_CONTROL0__SI__VI     regAUX_DPHY_RX_CONTROL0__SI__VI;
typedef union AUX_DPHY_RX_CONTROL1__SI__VI     regAUX_DPHY_RX_CONTROL1__SI__VI;
typedef union AUX_DPHY_RX_STATUS__SI__VI       regAUX_DPHY_RX_STATUS__SI__VI;
typedef union AUX_DPHY_TX_CONTROL__SI__VI      regAUX_DPHY_TX_CONTROL__SI__VI;
typedef union AUX_DPHY_TX_REF_CONTROL__SI__VI  regAUX_DPHY_TX_REF_CONTROL__SI__VI;
typedef union AUX_DPHY_TX_STATUS__SI__VI       regAUX_DPHY_TX_STATUS__SI__VI;
typedef union AUX_INTERRUPT_CONTROL__SI__VI    regAUX_INTERRUPT_CONTROL__SI__VI;
typedef union AUX_LS_DATA__SI__VI              regAUX_LS_DATA__SI__VI;
typedef union AUX_LS_STATUS__SI__VI            regAUX_LS_STATUS__SI__VI;
typedef union AUX_SW_CONTROL__SI__VI           regAUX_SW_CONTROL__SI__VI;
typedef union AUX_SW_DATA__SI__VI              regAUX_SW_DATA__SI__VI;
typedef union AUX_SW_STATUS__SI__VI            regAUX_SW_STATUS__SI__VI;
typedef union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI__VI regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__SI__VI;
typedef union AZALIA_AUDIO_DTO_CONTROL__SI     regAZALIA_AUDIO_DTO_CONTROL__SI;
typedef union AZALIA_AUDIO_DTO_CONTROL__VI     regAZALIA_AUDIO_DTO_CONTROL__VI;
typedef union AZALIA_AUDIO_DTO__SI__VI         regAZALIA_AUDIO_DTO__SI__VI;
typedef union AZALIA_BDL_DMA_CONTROL__SI       regAZALIA_BDL_DMA_CONTROL__SI;
typedef union AZALIA_BDL_DMA_CONTROL__VI       regAZALIA_BDL_DMA_CONTROL__VI;
typedef union AZALIA_CORB_DMA_CONTROL__SI__VI  regAZALIA_CORB_DMA_CONTROL__SI__VI;
typedef union AZALIA_CUMULATIVE_LATENCY_COUNT__SI__VI regAZALIA_CUMULATIVE_LATENCY_COUNT__SI__VI;
typedef union AZALIA_CUMULATIVE_REQUEST_COUNT__SI__VI regAZALIA_CUMULATIVE_REQUEST_COUNT__SI__VI;
typedef union AZALIA_CYCLIC_BUFFER_SYNC__SI__VI regAZALIA_CYCLIC_BUFFER_SYNC__SI__VI;
typedef union AZALIA_DATA_DMA_CONTROL__SI__VI  regAZALIA_DATA_DMA_CONTROL__SI__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI regAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__SI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI regAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI__VI regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__SI__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI;
typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI regAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__SI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI regAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI regAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__SI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI regAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI;
typedef union AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI;
typedef union AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__SI__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SI__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SI__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SI__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI regAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI regAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__SI;
typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI regAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI regAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI regAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI regAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__SI__VI;
typedef union AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI regAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__SI__VI;
typedef union AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI regAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SI__VI;
typedef union AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI regAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SI__VI;
typedef union AZALIA_LATENCY_COUNTER_CONTROL__SI__VI regAZALIA_LATENCY_COUNTER_CONTROL__SI__VI;
typedef union AZALIA_RIRB_AND_DP_CONTROL__SI__VI regAZALIA_RIRB_AND_DP_CONTROL__SI__VI;
typedef union AZALIA_UNDERFLOW_FILLER_SAMPLE__SI__VI regAZALIA_UNDERFLOW_FILLER_SAMPLE__SI__VI;
typedef union AZALIA_WORSTCASE_LATENCY_COUNT__SI__VI regAZALIA_WORSTCASE_LATENCY_COUNT__SI__VI;
typedef union AZ_TEST_DEBUG_DATA__SI__VI       regAZ_TEST_DEBUG_DATA__SI__VI;
typedef union AZ_TEST_DEBUG_INDEX__SI__VI      regAZ_TEST_DEBUG_INDEX__SI__VI;
typedef union BACO_CNTL_MISC__CI__VI           regBACO_CNTL_MISC__CI__VI;
typedef union BACO_CNTL__CI__VI                regBACO_CNTL__CI__VI;
typedef union BASE_ADDR_1                      regBASE_ADDR_1;
typedef union BASE_ADDR_2                      regBASE_ADDR_2;
typedef union BASE_ADDR_3                      regBASE_ADDR_3;
typedef union BASE_ADDR_4                      regBASE_ADDR_4;
typedef union BASE_ADDR_5                      regBASE_ADDR_5;
typedef union BASE_ADDR_6                      regBASE_ADDR_6;
typedef union BASE_CLASS                       regBASE_CLASS;
typedef union BCI_DEBUG_READ                   regBCI_DEBUG_READ;
typedef union BIF_BACO_DEBUG_LATCH__CI__VI     regBIF_BACO_DEBUG_LATCH__CI__VI;
typedef union BIF_BACO_DEBUG__CI__VI           regBIF_BACO_DEBUG__CI__VI;
typedef union BIF_BACO_MSIC__CI                regBIF_BACO_MSIC__CI;
typedef union BIF_BUSNUM_CNTL1                 regBIF_BUSNUM_CNTL1;
typedef union BIF_BUSNUM_CNTL2                 regBIF_BUSNUM_CNTL2;
typedef union BIF_BUSNUM_LIST0                 regBIF_BUSNUM_LIST0;
typedef union BIF_BUSNUM_LIST1                 regBIF_BUSNUM_LIST1;
typedef union BIF_BUSY_DELAY_CNTR              regBIF_BUSY_DELAY_CNTR;
typedef union BIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI regBIF_CC_RFE_IMP_OVERRIDECNTL__CI__VI;
typedef union BIF_CLK_PDWN_DELAY_TIMER__SI__CI regBIF_CLK_PDWN_DELAY_TIMER__SI__CI;
typedef union BIF_DEBUG_CNTL                   regBIF_DEBUG_CNTL;
typedef union BIF_DEBUG_MUX                    regBIF_DEBUG_MUX;
typedef union BIF_DEBUG_OUT                    regBIF_DEBUG_OUT;
typedef union BIF_DEVFUNCNUM_LIST0__CI__VI     regBIF_DEVFUNCNUM_LIST0__CI__VI;
typedef union BIF_DEVFUNCNUM_LIST1__CI__VI     regBIF_DEVFUNCNUM_LIST1__CI__VI;
typedef union BIF_DOORBELL_CNTL__CI__VI        regBIF_DOORBELL_CNTL__CI__VI;
typedef union BIF_FB_EN                        regBIF_FB_EN;
typedef union BIF_FEATURES_CONTROL_MISC__CI__VI regBIF_FEATURES_CONTROL_MISC__CI__VI;
typedef union BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI regBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__CI__VI;
typedef union BIF_IMPCTL_RXCNTL__CI__VI        regBIF_IMPCTL_RXCNTL__CI__VI;
typedef union BIF_IMPCTL_SMPLCNTL__CI__VI      regBIF_IMPCTL_SMPLCNTL__CI__VI;
typedef union BIF_IMPCTL_TXCNTL_pd__CI__VI     regBIF_IMPCTL_TXCNTL_pd__CI__VI;
typedef union BIF_IMPCTL_TXCNTL_pu__CI__VI     regBIF_IMPCTL_TXCNTL_pu__CI__VI;
typedef union BIF_LNCNT_RESET__CI              regBIF_LNCNT_RESET__CI;
typedef union BIF_PERFCOUNTER0_RESULT__CI__VI  regBIF_PERFCOUNTER0_RESULT__CI__VI;
typedef union BIF_PERFCOUNTER1_RESULT__CI__VI  regBIF_PERFCOUNTER1_RESULT__CI__VI;
typedef union BIF_PERFMON_CNTL__CI__VI         regBIF_PERFMON_CNTL__CI__VI;
typedef union BIF_PIF_TXCLK_SWITCH_TIMER__CI   regBIF_PIF_TXCLK_SWITCH_TIMER__CI;
typedef union BIF_PWDN_COMMAND__CI             regBIF_PWDN_COMMAND__CI;
typedef union BIF_PWDN_COMMAND__VI             regBIF_PWDN_COMMAND__VI;
typedef union BIF_PWDN_STATUS__CI              regBIF_PWDN_STATUS__CI;
typedef union BIF_PWDN_STATUS__VI              regBIF_PWDN_STATUS__VI;
typedef union BIF_RESET_CNTL__CI               regBIF_RESET_CNTL__CI;
typedef union BIF_RESET_EN__SI__CI             regBIF_RESET_EN__SI__CI;
typedef union BIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI regBIF_RFE_CLIENT_SOFTRST_TRIGGER__CI__VI;
typedef union BIF_RFE_IMPRST_CNTL__CI__VI      regBIF_RFE_IMPRST_CNTL__CI__VI;
typedef union BIF_RFE_MASTER_SOFTRST_TRIGGER__CI regBIF_RFE_MASTER_SOFTRST_TRIGGER__CI;
typedef union BIF_RFE_MASTER_SOFTRST_TRIGGER__VI regBIF_RFE_MASTER_SOFTRST_TRIGGER__VI;
typedef union BIF_RFE_MMCFG_CNTL__CI__VI       regBIF_RFE_MMCFG_CNTL__CI__VI;
typedef union BIF_RFE_MST_BU_CMDSTATUS__CI__VI regBIF_RFE_MST_BU_CMDSTATUS__CI__VI;
typedef union BIF_RFE_MST_BX_CMDSTATUS__CI__VI regBIF_RFE_MST_BX_CMDSTATUS__CI__VI;
typedef union BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI regBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__CI__VI;
typedef union BIF_RFE_MST_TMOUT_STATUS__CI__VI regBIF_RFE_MST_TMOUT_STATUS__CI__VI;
typedef union BIF_RFE_SNOOP_REG__CI__VI        regBIF_RFE_SNOOP_REG__CI__VI;
typedef union BIF_RFE_SOFTRST_CNTL__CI         regBIF_RFE_SOFTRST_CNTL__CI;
typedef union BIF_RFE_SOFTRST_CNTL__VI         regBIF_RFE_SOFTRST_CNTL__VI;
typedef union BIF_SCRATCH0                     regBIF_SCRATCH0;
typedef union BIF_SCRATCH1                     regBIF_SCRATCH1;
typedef union BIF_SLVARB_MODE__CI__VI          regBIF_SLVARB_MODE__CI__VI;
typedef union BIF_SSA_DISP_LOWER__CI           regBIF_SSA_DISP_LOWER__CI;
typedef union BIF_SSA_DISP_UPPER__CI           regBIF_SSA_DISP_UPPER__CI;
typedef union BIF_SSA_GFX0_LOWER__CI           regBIF_SSA_GFX0_LOWER__CI;
typedef union BIF_SSA_GFX0_UPPER__CI           regBIF_SSA_GFX0_UPPER__CI;
typedef union BIF_SSA_GFX1_LOWER__CI           regBIF_SSA_GFX1_LOWER__CI;
typedef union BIF_SSA_GFX1_UPPER__CI           regBIF_SSA_GFX1_UPPER__CI;
typedef union BIF_SSA_GFX2_LOWER__CI           regBIF_SSA_GFX2_LOWER__CI;
typedef union BIF_SSA_GFX2_UPPER__CI           regBIF_SSA_GFX2_UPPER__CI;
typedef union BIF_SSA_GFX3_LOWER__CI           regBIF_SSA_GFX3_LOWER__CI;
typedef union BIF_SSA_GFX3_UPPER__CI           regBIF_SSA_GFX3_UPPER__CI;
typedef union BIF_SSA_MC_LOWER__CI             regBIF_SSA_MC_LOWER__CI;
typedef union BIF_SSA_MC_UPPER__CI             regBIF_SSA_MC_UPPER__CI;
typedef union BIF_SSA_PWR_STATUS__CI           regBIF_SSA_PWR_STATUS__CI;
typedef union BIF_XDMA_HI__CI__VI              regBIF_XDMA_HI__CI__VI;
typedef union BIF_XDMA_LO__CI__VI              regBIF_XDMA_LO__CI__VI;
typedef union BIOS_SCRATCH_0                   regBIOS_SCRATCH_0;
typedef union BIOS_SCRATCH_1                   regBIOS_SCRATCH_1;
typedef union BIOS_SCRATCH_10                  regBIOS_SCRATCH_10;
typedef union BIOS_SCRATCH_11                  regBIOS_SCRATCH_11;
typedef union BIOS_SCRATCH_12                  regBIOS_SCRATCH_12;
typedef union BIOS_SCRATCH_13                  regBIOS_SCRATCH_13;
typedef union BIOS_SCRATCH_14                  regBIOS_SCRATCH_14;
typedef union BIOS_SCRATCH_15                  regBIOS_SCRATCH_15;
typedef union BIOS_SCRATCH_2                   regBIOS_SCRATCH_2;
typedef union BIOS_SCRATCH_3                   regBIOS_SCRATCH_3;
typedef union BIOS_SCRATCH_4                   regBIOS_SCRATCH_4;
typedef union BIOS_SCRATCH_5                   regBIOS_SCRATCH_5;
typedef union BIOS_SCRATCH_6                   regBIOS_SCRATCH_6;
typedef union BIOS_SCRATCH_7                   regBIOS_SCRATCH_7;
typedef union BIOS_SCRATCH_8                   regBIOS_SCRATCH_8;
typedef union BIOS_SCRATCH_9                   regBIOS_SCRATCH_9;
typedef union BIST                             regBIST;
typedef union BL1_PWM_ABM_CNTL__SI__VI         regBL1_PWM_ABM_CNTL__SI__VI;
typedef union BL1_PWM_AMBIENT_LIGHT_LEVEL__SI__VI regBL1_PWM_AMBIENT_LIGHT_LEVEL__SI__VI;
typedef union BL1_PWM_BL_UPDATE_SAMPLE_RATE__SI__VI regBL1_PWM_BL_UPDATE_SAMPLE_RATE__SI__VI;
typedef union BL1_PWM_CURRENT_ABM_LEVEL__SI__VI regBL1_PWM_CURRENT_ABM_LEVEL__SI__VI;
typedef union BL1_PWM_FINAL_DUTY_CYCLE__SI__VI regBL1_PWM_FINAL_DUTY_CYCLE__SI__VI;
typedef union BL1_PWM_GRP2_REG_LOCK__SI__VI    regBL1_PWM_GRP2_REG_LOCK__SI__VI;
typedef union BL1_PWM_MINIMUM_DUTY_CYCLE__SI__VI regBL1_PWM_MINIMUM_DUTY_CYCLE__SI__VI;
typedef union BL1_PWM_TARGET_ABM_LEVEL__SI__VI regBL1_PWM_TARGET_ABM_LEVEL__SI__VI;
typedef union BL1_PWM_USER_LEVEL__SI__VI       regBL1_PWM_USER_LEVEL__SI__VI;
typedef union BL_PWM_CNTL2__SI__VI             regBL_PWM_CNTL2__SI__VI;
typedef union BL_PWM_CNTL__SI__VI              regBL_PWM_CNTL__SI__VI;
typedef union BL_PWM_GRP1_REG_LOCK__SI__VI     regBL_PWM_GRP1_REG_LOCK__SI__VI;
typedef union BL_PWM_PERIOD_CNTL__SI__VI       regBL_PWM_PERIOD_CNTL__SI__VI;
typedef union BUS_CNTL                         regBUS_CNTL;
typedef union BX_RESET_EN__CI__VI              regBX_RESET_EN__CI__VI;
typedef union CACHE_LINE                       regCACHE_LINE;
typedef union CAPTURE_HOST_BUSNUM              regCAPTURE_HOST_BUSNUM;
typedef union CAP_PTR                          regCAP_PTR;
typedef union CB_BLEND0_CONTROL                regCB_BLEND0_CONTROL;
typedef union CB_BLEND1_CONTROL                regCB_BLEND1_CONTROL;
typedef union CB_BLEND2_CONTROL                regCB_BLEND2_CONTROL;
typedef union CB_BLEND3_CONTROL                regCB_BLEND3_CONTROL;
typedef union CB_BLEND4_CONTROL                regCB_BLEND4_CONTROL;
typedef union CB_BLEND5_CONTROL                regCB_BLEND5_CONTROL;
typedef union CB_BLEND6_CONTROL                regCB_BLEND6_CONTROL;
typedef union CB_BLEND7_CONTROL                regCB_BLEND7_CONTROL;
typedef union CB_BLEND_ALPHA                   regCB_BLEND_ALPHA;
typedef union CB_BLEND_BLUE                    regCB_BLEND_BLUE;
typedef union CB_BLEND_GREEN                   regCB_BLEND_GREEN;
typedef union CB_BLEND_RED                     regCB_BLEND_RED;
typedef union CB_CGTT_SCLK_CTRL                regCB_CGTT_SCLK_CTRL;
typedef union CB_COLOR0_ATTRIB                 regCB_COLOR0_ATTRIB;
typedef union CB_COLOR0_BASE                   regCB_COLOR0_BASE;
typedef union CB_COLOR0_CLEAR_WORD0            regCB_COLOR0_CLEAR_WORD0;
typedef union CB_COLOR0_CLEAR_WORD1            regCB_COLOR0_CLEAR_WORD1;
typedef union CB_COLOR0_CMASK                  regCB_COLOR0_CMASK;
typedef union CB_COLOR0_CMASK_SLICE            regCB_COLOR0_CMASK_SLICE;
typedef union CB_COLOR0_FMASK                  regCB_COLOR0_FMASK;
typedef union CB_COLOR0_FMASK_SLICE            regCB_COLOR0_FMASK_SLICE;
typedef union CB_COLOR0_INFO                   regCB_COLOR0_INFO;
typedef union CB_COLOR0_PITCH                  regCB_COLOR0_PITCH;
typedef union CB_COLOR0_SLICE                  regCB_COLOR0_SLICE;
typedef union CB_COLOR0_VIEW                   regCB_COLOR0_VIEW;
typedef union CB_COLOR1_ATTRIB                 regCB_COLOR1_ATTRIB;
typedef union CB_COLOR1_BASE                   regCB_COLOR1_BASE;
typedef union CB_COLOR1_CLEAR_WORD0            regCB_COLOR1_CLEAR_WORD0;
typedef union CB_COLOR1_CLEAR_WORD1            regCB_COLOR1_CLEAR_WORD1;
typedef union CB_COLOR1_CMASK                  regCB_COLOR1_CMASK;
typedef union CB_COLOR1_CMASK_SLICE            regCB_COLOR1_CMASK_SLICE;
typedef union CB_COLOR1_FMASK                  regCB_COLOR1_FMASK;
typedef union CB_COLOR1_FMASK_SLICE            regCB_COLOR1_FMASK_SLICE;
typedef union CB_COLOR1_INFO                   regCB_COLOR1_INFO;
typedef union CB_COLOR1_PITCH                  regCB_COLOR1_PITCH;
typedef union CB_COLOR1_SLICE                  regCB_COLOR1_SLICE;
typedef union CB_COLOR1_VIEW                   regCB_COLOR1_VIEW;
typedef union CB_COLOR2_ATTRIB                 regCB_COLOR2_ATTRIB;
typedef union CB_COLOR2_BASE                   regCB_COLOR2_BASE;
typedef union CB_COLOR2_CLEAR_WORD0            regCB_COLOR2_CLEAR_WORD0;
typedef union CB_COLOR2_CLEAR_WORD1            regCB_COLOR2_CLEAR_WORD1;
typedef union CB_COLOR2_CMASK                  regCB_COLOR2_CMASK;
typedef union CB_COLOR2_CMASK_SLICE            regCB_COLOR2_CMASK_SLICE;
typedef union CB_COLOR2_FMASK                  regCB_COLOR2_FMASK;
typedef union CB_COLOR2_FMASK_SLICE            regCB_COLOR2_FMASK_SLICE;
typedef union CB_COLOR2_INFO                   regCB_COLOR2_INFO;
typedef union CB_COLOR2_PITCH                  regCB_COLOR2_PITCH;
typedef union CB_COLOR2_SLICE                  regCB_COLOR2_SLICE;
typedef union CB_COLOR2_VIEW                   regCB_COLOR2_VIEW;
typedef union CB_COLOR3_ATTRIB                 regCB_COLOR3_ATTRIB;
typedef union CB_COLOR3_BASE                   regCB_COLOR3_BASE;
typedef union CB_COLOR3_CLEAR_WORD0            regCB_COLOR3_CLEAR_WORD0;
typedef union CB_COLOR3_CLEAR_WORD1            regCB_COLOR3_CLEAR_WORD1;
typedef union CB_COLOR3_CMASK                  regCB_COLOR3_CMASK;
typedef union CB_COLOR3_CMASK_SLICE            regCB_COLOR3_CMASK_SLICE;
typedef union CB_COLOR3_FMASK                  regCB_COLOR3_FMASK;
typedef union CB_COLOR3_FMASK_SLICE            regCB_COLOR3_FMASK_SLICE;
typedef union CB_COLOR3_INFO                   regCB_COLOR3_INFO;
typedef union CB_COLOR3_PITCH                  regCB_COLOR3_PITCH;
typedef union CB_COLOR3_SLICE                  regCB_COLOR3_SLICE;
typedef union CB_COLOR3_VIEW                   regCB_COLOR3_VIEW;
typedef union CB_COLOR4_ATTRIB                 regCB_COLOR4_ATTRIB;
typedef union CB_COLOR4_BASE                   regCB_COLOR4_BASE;
typedef union CB_COLOR4_CLEAR_WORD0            regCB_COLOR4_CLEAR_WORD0;
typedef union CB_COLOR4_CLEAR_WORD1            regCB_COLOR4_CLEAR_WORD1;
typedef union CB_COLOR4_CMASK                  regCB_COLOR4_CMASK;
typedef union CB_COLOR4_CMASK_SLICE            regCB_COLOR4_CMASK_SLICE;
typedef union CB_COLOR4_FMASK                  regCB_COLOR4_FMASK;
typedef union CB_COLOR4_FMASK_SLICE            regCB_COLOR4_FMASK_SLICE;
typedef union CB_COLOR4_INFO                   regCB_COLOR4_INFO;
typedef union CB_COLOR4_PITCH                  regCB_COLOR4_PITCH;
typedef union CB_COLOR4_SLICE                  regCB_COLOR4_SLICE;
typedef union CB_COLOR4_VIEW                   regCB_COLOR4_VIEW;
typedef union CB_COLOR5_ATTRIB                 regCB_COLOR5_ATTRIB;
typedef union CB_COLOR5_BASE                   regCB_COLOR5_BASE;
typedef union CB_COLOR5_CLEAR_WORD0            regCB_COLOR5_CLEAR_WORD0;
typedef union CB_COLOR5_CLEAR_WORD1            regCB_COLOR5_CLEAR_WORD1;
typedef union CB_COLOR5_CMASK                  regCB_COLOR5_CMASK;
typedef union CB_COLOR5_CMASK_SLICE            regCB_COLOR5_CMASK_SLICE;
typedef union CB_COLOR5_FMASK                  regCB_COLOR5_FMASK;
typedef union CB_COLOR5_FMASK_SLICE            regCB_COLOR5_FMASK_SLICE;
typedef union CB_COLOR5_INFO                   regCB_COLOR5_INFO;
typedef union CB_COLOR5_PITCH                  regCB_COLOR5_PITCH;
typedef union CB_COLOR5_SLICE                  regCB_COLOR5_SLICE;
typedef union CB_COLOR5_VIEW                   regCB_COLOR5_VIEW;
typedef union CB_COLOR6_ATTRIB                 regCB_COLOR6_ATTRIB;
typedef union CB_COLOR6_BASE                   regCB_COLOR6_BASE;
typedef union CB_COLOR6_CLEAR_WORD0            regCB_COLOR6_CLEAR_WORD0;
typedef union CB_COLOR6_CLEAR_WORD1            regCB_COLOR6_CLEAR_WORD1;
typedef union CB_COLOR6_CMASK                  regCB_COLOR6_CMASK;
typedef union CB_COLOR6_CMASK_SLICE            regCB_COLOR6_CMASK_SLICE;
typedef union CB_COLOR6_FMASK                  regCB_COLOR6_FMASK;
typedef union CB_COLOR6_FMASK_SLICE            regCB_COLOR6_FMASK_SLICE;
typedef union CB_COLOR6_INFO                   regCB_COLOR6_INFO;
typedef union CB_COLOR6_PITCH                  regCB_COLOR6_PITCH;
typedef union CB_COLOR6_SLICE                  regCB_COLOR6_SLICE;
typedef union CB_COLOR6_VIEW                   regCB_COLOR6_VIEW;
typedef union CB_COLOR7_ATTRIB                 regCB_COLOR7_ATTRIB;
typedef union CB_COLOR7_BASE                   regCB_COLOR7_BASE;
typedef union CB_COLOR7_CLEAR_WORD0            regCB_COLOR7_CLEAR_WORD0;
typedef union CB_COLOR7_CLEAR_WORD1            regCB_COLOR7_CLEAR_WORD1;
typedef union CB_COLOR7_CMASK                  regCB_COLOR7_CMASK;
typedef union CB_COLOR7_CMASK_SLICE            regCB_COLOR7_CMASK_SLICE;
typedef union CB_COLOR7_FMASK                  regCB_COLOR7_FMASK;
typedef union CB_COLOR7_FMASK_SLICE            regCB_COLOR7_FMASK_SLICE;
typedef union CB_COLOR7_INFO                   regCB_COLOR7_INFO;
typedef union CB_COLOR7_PITCH                  regCB_COLOR7_PITCH;
typedef union CB_COLOR7_SLICE                  regCB_COLOR7_SLICE;
typedef union CB_COLOR7_VIEW                   regCB_COLOR7_VIEW;
typedef union CB_COLOR_CONTROL                 regCB_COLOR_CONTROL;
typedef union CB_DEBUG_BUS_1                   regCB_DEBUG_BUS_1;
typedef union CB_DEBUG_BUS_13__SI__CI          regCB_DEBUG_BUS_13__SI__CI;
typedef union CB_DEBUG_BUS_13__VI              regCB_DEBUG_BUS_13__VI;
typedef union CB_DEBUG_BUS_14__SI__CI          regCB_DEBUG_BUS_14__SI__CI;
typedef union CB_DEBUG_BUS_14__VI              regCB_DEBUG_BUS_14__VI;
typedef union CB_DEBUG_BUS_15__SI__CI          regCB_DEBUG_BUS_15__SI__CI;
typedef union CB_DEBUG_BUS_15__VI              regCB_DEBUG_BUS_15__VI;
typedef union CB_DEBUG_BUS_16__SI__CI          regCB_DEBUG_BUS_16__SI__CI;
typedef union CB_DEBUG_BUS_16__VI              regCB_DEBUG_BUS_16__VI;
typedef union CB_DEBUG_BUS_17__SI__CI          regCB_DEBUG_BUS_17__SI__CI;
typedef union CB_DEBUG_BUS_17__VI              regCB_DEBUG_BUS_17__VI;
typedef union CB_DEBUG_BUS_18__SI__CI          regCB_DEBUG_BUS_18__SI__CI;
typedef union CB_DEBUG_BUS_18__VI              regCB_DEBUG_BUS_18__VI;
typedef union CB_DEBUG_BUS_2                   regCB_DEBUG_BUS_2;
typedef union CB_HW_CONTROL                    regCB_HW_CONTROL;
typedef union CB_HW_CONTROL_1                  regCB_HW_CONTROL_1;
typedef union CB_HW_CONTROL_2__CI              regCB_HW_CONTROL_2__CI;
typedef union CB_HW_CONTROL_2__VI              regCB_HW_CONTROL_2__VI;
typedef union CB_HW_CONTROL_2__SI              regCB_HW_CONTROL_2__SI;
typedef union CB_HW_CONTROL_3__CI__VI          regCB_HW_CONTROL_3__CI__VI;
typedef union CB_PERFCOUNTER0_HI               regCB_PERFCOUNTER0_HI;
typedef union CB_PERFCOUNTER0_LO               regCB_PERFCOUNTER0_LO;
typedef union CB_PERFCOUNTER0_SELECT1__CI__VI  regCB_PERFCOUNTER0_SELECT1__CI__VI;
typedef union CB_PERFCOUNTER0_SELECT1__SI      regCB_PERFCOUNTER0_SELECT1__SI;
typedef union CB_PERFCOUNTER0_SELECT__CI__VI   regCB_PERFCOUNTER0_SELECT__CI__VI;
typedef union CB_PERFCOUNTER1_HI               regCB_PERFCOUNTER1_HI;
typedef union CB_PERFCOUNTER1_LO               regCB_PERFCOUNTER1_LO;
typedef union CB_PERFCOUNTER1_SELECT__CI__VI   regCB_PERFCOUNTER1_SELECT__CI__VI;
typedef union CB_PERFCOUNTER2_HI               regCB_PERFCOUNTER2_HI;
typedef union CB_PERFCOUNTER2_LO               regCB_PERFCOUNTER2_LO;
typedef union CB_PERFCOUNTER2_SELECT__CI__VI   regCB_PERFCOUNTER2_SELECT__CI__VI;
typedef union CB_PERFCOUNTER3_HI               regCB_PERFCOUNTER3_HI;
typedef union CB_PERFCOUNTER3_LO               regCB_PERFCOUNTER3_LO;
typedef union CB_PERFCOUNTER3_SELECT__CI__VI   regCB_PERFCOUNTER3_SELECT__CI__VI;
typedef union CB_PERFCOUNTER_FILTER__CI__VI    regCB_PERFCOUNTER_FILTER__CI__VI;
typedef union CB_SHADER_MASK                   regCB_SHADER_MASK;
typedef union CB_TARGET_MASK                   regCB_TARGET_MASK;
typedef union CC_DRM_ID_STRAPS                 regCC_DRM_ID_STRAPS;
typedef union CC_GC_EDC_CONFIG__CI__VI         regCC_GC_EDC_CONFIG__CI__VI;
typedef union CC_GC_PRIM_CONFIG__CI__VI        regCC_GC_PRIM_CONFIG__CI__VI;
typedef union CC_GC_SHADER_ARRAY_CONFIG__CI__VI regCC_GC_SHADER_ARRAY_CONFIG__CI__VI;
typedef union CC_GC_SHADER_ARRAY_CONFIG__SI    regCC_GC_SHADER_ARRAY_CONFIG__SI;
typedef union CC_GIO_IOCCFG_FUSES__CI__VI      regCC_GIO_IOCCFG_FUSES__CI__VI;
typedef union CC_GIO_IOC_FUSES__CI__VI         regCC_GIO_IOC_FUSES__CI__VI;
typedef union CC_MC_MAX_CHANNEL                regCC_MC_MAX_CHANNEL;
typedef union CC_RB_BACKEND_DISABLE            regCC_RB_BACKEND_DISABLE;
typedef union CC_RB_DAISY_CHAIN                regCC_RB_DAISY_CHAIN;
typedef union CC_RB_REDUNDANCY__CI__VI         regCC_RB_REDUNDANCY__CI__VI;
typedef union CC_RB_REDUNDANCY__SI             regCC_RB_REDUNDANCY__SI;
typedef union CC_RCU_FUSES__CI                 regCC_RCU_FUSES__CI;
typedef union CC_RCU_FUSES__VI                 regCC_RCU_FUSES__VI;
typedef union CC_SCLK_VID_FUSES__CI__VI        regCC_SCLK_VID_FUSES__CI__VI;
typedef union CC_SMU_MISC_FUSES__CI__VI        regCC_SMU_MISC_FUSES__CI__VI;
typedef union CC_SMU_TST_EFUSE1_MISC__CI__VI   regCC_SMU_TST_EFUSE1_MISC__CI__VI;
typedef union CC_SQC_BANK_DISABLE              regCC_SQC_BANK_DISABLE;
typedef union CC_SYS_RB_BACKEND_DISABLE        regCC_SYS_RB_BACKEND_DISABLE;
typedef union CC_SYS_RB_REDUNDANCY__SI__CI     regCC_SYS_RB_REDUNDANCY__SI__CI;
typedef union CC_SYS_RB_REDUNDANCY__VI         regCC_SYS_RB_REDUNDANCY__VI;
typedef union CC_THM_STRAPS0__CI__VI           regCC_THM_STRAPS0__CI__VI;
typedef union CC_TST_ID_STRAPS__CI__VI         regCC_TST_ID_STRAPS__CI__VI;
typedef union CGTS_CU0_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU0_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU0_SP0_CTRL_REG__CI__VI    regCGTS_CU0_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU0_SP1_CTRL_REG__CI__VI    regCGTS_CU0_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU0_TA_SQC_CTRL_REG__CI__VI regCGTS_CU0_TA_SQC_CTRL_REG__CI__VI;
typedef union CGTS_CU0_TD_TCP_CTRL_REG__CI__VI regCGTS_CU0_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU10_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU10_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU10_SP0_CTRL_REG__CI__VI   regCGTS_CU10_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU10_SP1_CTRL_REG__CI__VI   regCGTS_CU10_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU10_TA_CTRL_REG__CI__VI    regCGTS_CU10_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU10_TD_TCP_CTRL_REG__CI__VI regCGTS_CU10_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU11_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU11_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU11_SP0_CTRL_REG__CI__VI   regCGTS_CU11_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU11_SP1_CTRL_REG__CI__VI   regCGTS_CU11_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU11_TA_CTRL_REG__CI__VI    regCGTS_CU11_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU11_TD_TCP_CTRL_REG__CI__VI regCGTS_CU11_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU12_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU12_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU12_SP0_CTRL_REG__CI__VI   regCGTS_CU12_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU12_SP1_CTRL_REG__CI__VI   regCGTS_CU12_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU12_TA_SQC_CTRL_REG__CI__VI regCGTS_CU12_TA_SQC_CTRL_REG__CI__VI;
typedef union CGTS_CU12_TD_TCP_CTRL_REG__CI__VI regCGTS_CU12_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU13_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU13_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU13_SP0_CTRL_REG__CI__VI   regCGTS_CU13_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU13_SP1_CTRL_REG__CI__VI   regCGTS_CU13_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU13_TA_CTRL_REG__CI__VI    regCGTS_CU13_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU13_TD_TCP_CTRL_REG__CI__VI regCGTS_CU13_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU14_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU14_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU14_SP0_CTRL_REG__CI__VI   regCGTS_CU14_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU14_SP1_CTRL_REG__CI__VI   regCGTS_CU14_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU14_TA_CTRL_REG__CI__VI    regCGTS_CU14_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU14_TD_TCP_CTRL_REG__CI__VI regCGTS_CU14_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU15_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU15_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU15_SP0_CTRL_REG__CI__VI   regCGTS_CU15_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU15_SP1_CTRL_REG__CI__VI   regCGTS_CU15_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU15_TA_CTRL_REG__CI__VI    regCGTS_CU15_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU15_TD_TCP_CTRL_REG__CI__VI regCGTS_CU15_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU1_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU1_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU1_SP0_CTRL_REG__CI__VI    regCGTS_CU1_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU1_SP1_CTRL_REG__CI__VI    regCGTS_CU1_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU1_TA_CTRL_REG__CI__VI     regCGTS_CU1_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU1_TD_TCP_CTRL_REG__CI__VI regCGTS_CU1_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU2_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU2_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU2_SP0_CTRL_REG__CI__VI    regCGTS_CU2_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU2_SP1_CTRL_REG__CI__VI    regCGTS_CU2_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU2_TA_CTRL_REG__CI__VI     regCGTS_CU2_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU2_TD_TCP_CTRL_REG__CI__VI regCGTS_CU2_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU3_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU3_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU3_SP0_CTRL_REG__CI__VI    regCGTS_CU3_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU3_SP1_CTRL_REG__CI__VI    regCGTS_CU3_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU3_TA_CTRL_REG__CI__VI     regCGTS_CU3_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU3_TD_TCP_CTRL_REG__CI__VI regCGTS_CU3_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU4_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU4_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU4_SP0_CTRL_REG__CI__VI    regCGTS_CU4_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU4_SP1_CTRL_REG__CI__VI    regCGTS_CU4_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU4_TA_SQC_CTRL_REG__CI__VI regCGTS_CU4_TA_SQC_CTRL_REG__CI__VI;
typedef union CGTS_CU4_TD_TCP_CTRL_REG__CI__VI regCGTS_CU4_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU5_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU5_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU5_SP0_CTRL_REG__CI__VI    regCGTS_CU5_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU5_SP1_CTRL_REG__CI__VI    regCGTS_CU5_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU5_TA_CTRL_REG__CI__VI     regCGTS_CU5_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU5_TD_TCP_CTRL_REG__CI__VI regCGTS_CU5_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU6_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU6_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU6_SP0_CTRL_REG__CI__VI    regCGTS_CU6_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU6_SP1_CTRL_REG__CI__VI    regCGTS_CU6_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU6_TA_CTRL_REG__CI__VI     regCGTS_CU6_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU6_TD_TCP_CTRL_REG__CI__VI regCGTS_CU6_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU7_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU7_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU7_SP0_CTRL_REG__CI__VI    regCGTS_CU7_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU7_SP1_CTRL_REG__CI__VI    regCGTS_CU7_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU7_TA_CTRL_REG__CI__VI     regCGTS_CU7_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU7_TD_TCP_CTRL_REG__CI__VI regCGTS_CU7_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU8_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU8_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU8_SP0_CTRL_REG__CI__VI    regCGTS_CU8_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU8_SP1_CTRL_REG__CI__VI    regCGTS_CU8_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU8_TA_SQC_CTRL_REG__CI__VI regCGTS_CU8_TA_SQC_CTRL_REG__CI__VI;
typedef union CGTS_CU8_TD_TCP_CTRL_REG__CI__VI regCGTS_CU8_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_CU9_LDS_SQ_CTRL_REG__CI__VI regCGTS_CU9_LDS_SQ_CTRL_REG__CI__VI;
typedef union CGTS_CU9_SP0_CTRL_REG__CI__VI    regCGTS_CU9_SP0_CTRL_REG__CI__VI;
typedef union CGTS_CU9_SP1_CTRL_REG__CI__VI    regCGTS_CU9_SP1_CTRL_REG__CI__VI;
typedef union CGTS_CU9_TA_CTRL_REG__CI__VI     regCGTS_CU9_TA_CTRL_REG__CI__VI;
typedef union CGTS_CU9_TD_TCP_CTRL_REG__CI__VI regCGTS_CU9_TD_TCP_CTRL_REG__CI__VI;
typedef union CGTS_RD_CTRL_REG                 regCGTS_RD_CTRL_REG;
typedef union CGTS_RD_REG                      regCGTS_RD_REG;
typedef union CGTS_SM_CTRL_REG                 regCGTS_SM_CTRL_REG;
typedef union CGTS_TCC_DISABLE                 regCGTS_TCC_DISABLE;
typedef union CGTS_USER_TCC_DISABLE            regCGTS_USER_TCC_DISABLE;
typedef union CGTT_BCI_CLK_CTRL                regCGTT_BCI_CLK_CTRL;
typedef union CGTT_CPC_CLK_CTRL__CI__VI        regCGTT_CPC_CLK_CTRL__CI__VI;
typedef union CGTT_CPF_CLK_CTRL__CI__VI        regCGTT_CPF_CLK_CTRL__CI__VI;
typedef union CGTT_CP_CLK_CTRL                 regCGTT_CP_CLK_CTRL;
typedef union CGTT_GDS_CLK_CTRL                regCGTT_GDS_CLK_CTRL;
typedef union CGTT_IA_CLK_CTRL__CI__VI         regCGTT_IA_CLK_CTRL__CI__VI;
typedef union CGTT_IA_CLK_CTRL__SI             regCGTT_IA_CLK_CTRL__SI;
typedef union CGTT_PA_CLK_CTRL                 regCGTT_PA_CLK_CTRL;
typedef union CGTT_PC_CLK_CTRL                 regCGTT_PC_CLK_CTRL;
typedef union CGTT_RLC_CLK_CTRL                regCGTT_RLC_CLK_CTRL;
typedef union CGTT_ROM_CLK_CTRL0               regCGTT_ROM_CLK_CTRL0;
typedef union CGTT_SC_CLK_CTRL                 regCGTT_SC_CLK_CTRL;
typedef union CGTT_SPI_CLK_CTRL                regCGTT_SPI_CLK_CTRL;
typedef union CGTT_SQG_CLK_CTRL                regCGTT_SQG_CLK_CTRL;
typedef union CGTT_SQ_CLK_CTRL                 regCGTT_SQ_CLK_CTRL;
typedef union CGTT_SX_CLK_CTRL0                regCGTT_SX_CLK_CTRL0;
typedef union CGTT_SX_CLK_CTRL1__SI__CI        regCGTT_SX_CLK_CTRL1__SI__CI;
typedef union CGTT_SX_CLK_CTRL1__VI            regCGTT_SX_CLK_CTRL1__VI;
typedef union CGTT_SX_CLK_CTRL2__SI__CI        regCGTT_SX_CLK_CTRL2__SI__CI;
typedef union CGTT_SX_CLK_CTRL2__VI            regCGTT_SX_CLK_CTRL2__VI;
typedef union CGTT_SX_CLK_CTRL3__SI__CI        regCGTT_SX_CLK_CTRL3__SI__CI;
typedef union CGTT_SX_CLK_CTRL3__VI            regCGTT_SX_CLK_CTRL3__VI;
typedef union CGTT_SX_CLK_CTRL4__SI__CI        regCGTT_SX_CLK_CTRL4__SI__CI;
typedef union CGTT_SX_CLK_CTRL4__VI            regCGTT_SX_CLK_CTRL4__VI;
typedef union CGTT_TCI_CLK_CTRL                regCGTT_TCI_CLK_CTRL;
typedef union CGTT_TCP_CLK_CTRL                regCGTT_TCP_CLK_CTRL;
typedef union CGTT_VGT_CLK_CTRL__SI__CI        regCGTT_VGT_CLK_CTRL__SI__CI;
typedef union CGTT_VGT_CLK_CTRL__VI            regCGTT_VGT_CLK_CTRL__VI;
typedef union CGTT_WD_CLK_CTRL__CI             regCGTT_WD_CLK_CTRL__CI;
typedef union CGTT_WD_CLK_CTRL__VI             regCGTT_WD_CLK_CTRL__VI;
typedef union CG_ACLK_CNTL__CI__VI             regCG_ACLK_CNTL__CI__VI;
typedef union CG_ACPI_CNTL__CI__VI             regCG_ACPI_CNTL__CI__VI;
typedef union CG_CLKPIN_CNTL_2__CI__VI         regCG_CLKPIN_CNTL_2__CI__VI;
typedef union CG_CLKPIN_CNTL__CI__VI           regCG_CLKPIN_CNTL__CI__VI;
typedef union CG_CLKPIN_CNTL__SI               regCG_CLKPIN_CNTL__SI;
typedef union CG_DCLK_CNTL__CI__VI             regCG_DCLK_CNTL__CI__VI;
typedef union CG_DCLK_STATUS__CI__VI           regCG_DCLK_STATUS__CI__VI;
typedef union CG_DISPLAY_GAP_CNTL2__CI__VI     regCG_DISPLAY_GAP_CNTL2__CI__VI;
typedef union CG_DISPLAY_GAP_CNTL__CI__VI      regCG_DISPLAY_GAP_CNTL__CI__VI;
typedef union CG_DISPLAY_GAP_CNTL__SI          regCG_DISPLAY_GAP_CNTL__SI;
typedef union CG_ECLK_CNTL__CI__VI             regCG_ECLK_CNTL__CI__VI;
typedef union CG_ECLK_STATUS__CI__VI           regCG_ECLK_STATUS__CI__VI;
typedef union CG_FDO_CTRL0                     regCG_FDO_CTRL0;
typedef union CG_FDO_CTRL1                     regCG_FDO_CTRL1;
typedef union CG_FDO_CTRL2                     regCG_FDO_CTRL2;
typedef union CG_FPS_CNT__CI                   regCG_FPS_CNT__CI;
typedef union CG_FPS_CNT__VI                   regCG_FPS_CNT__VI;
typedef union CG_FREQ_TRAN_VOTING_0__CI__VI    regCG_FREQ_TRAN_VOTING_0__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_1__CI__VI    regCG_FREQ_TRAN_VOTING_1__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_2__CI__VI    regCG_FREQ_TRAN_VOTING_2__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_3__CI__VI    regCG_FREQ_TRAN_VOTING_3__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_4__CI__VI    regCG_FREQ_TRAN_VOTING_4__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_5__CI__VI    regCG_FREQ_TRAN_VOTING_5__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_6__CI__VI    regCG_FREQ_TRAN_VOTING_6__CI__VI;
typedef union CG_FREQ_TRAN_VOTING_7__CI__VI    regCG_FREQ_TRAN_VOTING_7__CI__VI;
typedef union CG_FREQ_TRAN_VOTING__SI          regCG_FREQ_TRAN_VOTING__SI;
typedef union CG_MULT_THERMAL_CTRL__SI__CI     regCG_MULT_THERMAL_CTRL__SI__CI;
typedef union CG_MULT_THERMAL_CTRL__VI         regCG_MULT_THERMAL_CTRL__VI;
typedef union CG_MULT_THERMAL_STATUS           regCG_MULT_THERMAL_STATUS;
typedef union CG_SPLL_FUNC_CNTL__SI__CI        regCG_SPLL_FUNC_CNTL__SI__CI;
typedef union CG_SPLL_FUNC_CNTL__VI            regCG_SPLL_FUNC_CNTL__VI;
typedef union CG_SPLL_FUNC_CNTL_2              regCG_SPLL_FUNC_CNTL_2;
typedef union CG_SPLL_FUNC_CNTL_3              regCG_SPLL_FUNC_CNTL_3;
typedef union CG_SPLL_FUNC_CNTL_4__SI__CI      regCG_SPLL_FUNC_CNTL_4__SI__CI;
typedef union CG_SPLL_FUNC_CNTL_4__VI          regCG_SPLL_FUNC_CNTL_4__VI;
typedef union CG_SPLL_FUNC_CNTL_5__SI__CI      regCG_SPLL_FUNC_CNTL_5__SI__CI;
typedef union CG_SPLL_FUNC_CNTL_5__VI          regCG_SPLL_FUNC_CNTL_5__VI;
typedef union CG_SPLL_FUNC_CNTL_6__CI__VI      regCG_SPLL_FUNC_CNTL_6__CI__VI;
typedef union CG_SPLL_SPREAD_SPECTRUM          regCG_SPLL_SPREAD_SPECTRUM;
typedef union CG_SPLL_SPREAD_SPECTRUM_2        regCG_SPLL_SPREAD_SPECTRUM_2;
typedef union CG_STATIC_SCREEN_PARAMETER       regCG_STATIC_SCREEN_PARAMETER;
typedef union CG_TACH_CTRL                     regCG_TACH_CTRL;
typedef union CG_TACH_STATUS                   regCG_TACH_STATUS;
typedef union CG_THERMAL_CTRL                  regCG_THERMAL_CTRL;
typedef union CG_THERMAL_INT                   regCG_THERMAL_INT;
typedef union CG_THERMAL_INT_CTRL__CI__VI      regCG_THERMAL_INT_CTRL__CI__VI;
typedef union CG_THERMAL_INT_ENA__CI__VI       regCG_THERMAL_INT_ENA__CI__VI;
typedef union CG_THERMAL_INT_STATUS__CI__VI    regCG_THERMAL_INT_STATUS__CI__VI;
typedef union CG_THERMAL_STATUS                regCG_THERMAL_STATUS;
typedef union CG_ULV_PARAMETER                 regCG_ULV_PARAMETER;
typedef union CG_VCLK_CNTL__CI__VI             regCG_VCLK_CNTL__CI__VI;
typedef union CG_VCLK_STATUS__CI__VI           regCG_VCLK_STATUS__CI__VI;
typedef union CHUB_ATC_PERFCOUNTER0_CFG__CI__VI regCHUB_ATC_PERFCOUNTER0_CFG__CI__VI;
typedef union CHUB_ATC_PERFCOUNTER1_CFG__CI__VI regCHUB_ATC_PERFCOUNTER1_CFG__CI__VI;
typedef union CHUB_ATC_PERFCOUNTER_HI__CI__VI  regCHUB_ATC_PERFCOUNTER_HI__CI__VI;
typedef union CHUB_ATC_PERFCOUNTER_LO__CI__VI  regCHUB_ATC_PERFCOUNTER_LO__CI__VI;
typedef union CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI regCHUB_ATC_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union CLIENT0_BM                       regCLIENT0_BM;
typedef union CLIENT0_CD0                      regCLIENT0_CD0;
typedef union CLIENT0_CD1                      regCLIENT0_CD1;
typedef union CLIENT0_CD2                      regCLIENT0_CD2;
typedef union CLIENT0_CD3                      regCLIENT0_CD3;
typedef union CLIENT0_CK0                      regCLIENT0_CK0;
typedef union CLIENT0_CK1                      regCLIENT0_CK1;
typedef union CLIENT0_CK2                      regCLIENT0_CK2;
typedef union CLIENT0_CK3                      regCLIENT0_CK3;
typedef union CLIENT0_K0                       regCLIENT0_K0;
typedef union CLIENT0_K1                       regCLIENT0_K1;
typedef union CLIENT0_K2                       regCLIENT0_K2;
typedef union CLIENT0_K3                       regCLIENT0_K3;
typedef union CLIENT0_OFFSET                   regCLIENT0_OFFSET;
typedef union CLIENT0_STATUS                   regCLIENT0_STATUS;
typedef union CLIENT1_BM                       regCLIENT1_BM;
typedef union CLIENT1_CD0                      regCLIENT1_CD0;
typedef union CLIENT1_CD1                      regCLIENT1_CD1;
typedef union CLIENT1_CD2                      regCLIENT1_CD2;
typedef union CLIENT1_CD3                      regCLIENT1_CD3;
typedef union CLIENT1_CK0                      regCLIENT1_CK0;
typedef union CLIENT1_CK1                      regCLIENT1_CK1;
typedef union CLIENT1_CK2                      regCLIENT1_CK2;
typedef union CLIENT1_CK3                      regCLIENT1_CK3;
typedef union CLIENT1_K0                       regCLIENT1_K0;
typedef union CLIENT1_K1                       regCLIENT1_K1;
typedef union CLIENT1_K2                       regCLIENT1_K2;
typedef union CLIENT1_K3                       regCLIENT1_K3;
typedef union CLIENT1_OFFSET                   regCLIENT1_OFFSET;
typedef union CLIENT1_PORT_STATUS              regCLIENT1_PORT_STATUS;
typedef union CLIENT2_BM                       regCLIENT2_BM;
typedef union CLIENT2_CD0                      regCLIENT2_CD0;
typedef union CLIENT2_CD1                      regCLIENT2_CD1;
typedef union CLIENT2_CD2                      regCLIENT2_CD2;
typedef union CLIENT2_CD3                      regCLIENT2_CD3;
typedef union CLIENT2_CK0                      regCLIENT2_CK0;
typedef union CLIENT2_CK1                      regCLIENT2_CK1;
typedef union CLIENT2_CK2                      regCLIENT2_CK2;
typedef union CLIENT2_CK3                      regCLIENT2_CK3;
typedef union CLIENT2_K0                       regCLIENT2_K0;
typedef union CLIENT2_K1                       regCLIENT2_K1;
typedef union CLIENT2_K2                       regCLIENT2_K2;
typedef union CLIENT2_K3                       regCLIENT2_K3;
typedef union CLIENT2_OFFSET                   regCLIENT2_OFFSET;
typedef union CLIENT2_STATUS                   regCLIENT2_STATUS;
typedef union CLIPPER_DEBUG_REG00              regCLIPPER_DEBUG_REG00;
typedef union CLIPPER_DEBUG_REG01              regCLIPPER_DEBUG_REG01;
typedef union CLIPPER_DEBUG_REG02              regCLIPPER_DEBUG_REG02;
typedef union CLIPPER_DEBUG_REG03              regCLIPPER_DEBUG_REG03;
typedef union CLIPPER_DEBUG_REG04              regCLIPPER_DEBUG_REG04;
typedef union CLIPPER_DEBUG_REG05              regCLIPPER_DEBUG_REG05;
typedef union CLIPPER_DEBUG_REG06              regCLIPPER_DEBUG_REG06;
typedef union CLIPPER_DEBUG_REG07              regCLIPPER_DEBUG_REG07;
typedef union CLIPPER_DEBUG_REG08              regCLIPPER_DEBUG_REG08;
typedef union CLIPPER_DEBUG_REG09              regCLIPPER_DEBUG_REG09;
typedef union CLIPPER_DEBUG_REG10              regCLIPPER_DEBUG_REG10;
typedef union CLIPPER_DEBUG_REG11              regCLIPPER_DEBUG_REG11;
typedef union CLIPPER_DEBUG_REG12              regCLIPPER_DEBUG_REG12;
typedef union CLIPPER_DEBUG_REG13              regCLIPPER_DEBUG_REG13;
typedef union CLIPPER_DEBUG_REG14              regCLIPPER_DEBUG_REG14;
typedef union CLIPPER_DEBUG_REG15              regCLIPPER_DEBUG_REG15;
typedef union CLIPPER_DEBUG_REG16              regCLIPPER_DEBUG_REG16;
typedef union CLIPPER_DEBUG_REG17              regCLIPPER_DEBUG_REG17;
typedef union CLIPPER_DEBUG_REG18              regCLIPPER_DEBUG_REG18;
typedef union CLIPPER_DEBUG_REG19              regCLIPPER_DEBUG_REG19;
typedef union CLKREQB_PAD_CNTL__CI__VI         regCLKREQB_PAD_CNTL__CI__VI;
typedef union CNB_PWRMGT_CNTL__CI__VI          regCNB_PWRMGT_CNTL__CI__VI;
typedef union COHER_DEST_BASE_0                regCOHER_DEST_BASE_0;
typedef union COHER_DEST_BASE_1                regCOHER_DEST_BASE_1;
typedef union COHER_DEST_BASE_2                regCOHER_DEST_BASE_2;
typedef union COHER_DEST_BASE_3                regCOHER_DEST_BASE_3;
typedef union COHER_DEST_BASE_HI_0__CI__VI     regCOHER_DEST_BASE_HI_0__CI__VI;
typedef union COHER_DEST_BASE_HI_1__CI__VI     regCOHER_DEST_BASE_HI_1__CI__VI;
typedef union COHER_DEST_BASE_HI_2__CI__VI     regCOHER_DEST_BASE_HI_2__CI__VI;
typedef union COHER_DEST_BASE_HI_3__CI__VI     regCOHER_DEST_BASE_HI_3__CI__VI;
typedef union COMMAND                          regCOMMAND;
typedef union COMPUTE_DIM_X                    regCOMPUTE_DIM_X;
typedef union COMPUTE_DIM_Y                    regCOMPUTE_DIM_Y;
typedef union COMPUTE_DIM_Z                    regCOMPUTE_DIM_Z;
typedef union COMPUTE_DISPATCH_INITIATOR       regCOMPUTE_DISPATCH_INITIATOR;
typedef union COMPUTE_MISC_RESERVED__CI__VI    regCOMPUTE_MISC_RESERVED__CI__VI;
typedef union COMPUTE_NUM_THREAD_X             regCOMPUTE_NUM_THREAD_X;
typedef union COMPUTE_NUM_THREAD_Y             regCOMPUTE_NUM_THREAD_Y;
typedef union COMPUTE_NUM_THREAD_Z             regCOMPUTE_NUM_THREAD_Z;
typedef union COMPUTE_PERFCOUNT_ENABLE__CI__VI regCOMPUTE_PERFCOUNT_ENABLE__CI__VI;
typedef union COMPUTE_PGM_HI                   regCOMPUTE_PGM_HI;
typedef union COMPUTE_PGM_LO                   regCOMPUTE_PGM_LO;
typedef union COMPUTE_PGM_RSRC1                regCOMPUTE_PGM_RSRC1;
typedef union COMPUTE_PGM_RSRC2                regCOMPUTE_PGM_RSRC2;
typedef union COMPUTE_PIPELINESTAT_ENABLE__CI__VI regCOMPUTE_PIPELINESTAT_ENABLE__CI__VI;
typedef union COMPUTE_RESOURCE_LIMITS          regCOMPUTE_RESOURCE_LIMITS;
typedef union COMPUTE_RESTART_X__CI__VI        regCOMPUTE_RESTART_X__CI__VI;
typedef union COMPUTE_RESTART_Y__CI__VI        regCOMPUTE_RESTART_Y__CI__VI;
typedef union COMPUTE_RESTART_Z__CI__VI        regCOMPUTE_RESTART_Z__CI__VI;
typedef union COMPUTE_START_X                  regCOMPUTE_START_X;
typedef union COMPUTE_START_Y                  regCOMPUTE_START_Y;
typedef union COMPUTE_START_Z                  regCOMPUTE_START_Z;
typedef union COMPUTE_STATIC_THREAD_MGMT_SE0   regCOMPUTE_STATIC_THREAD_MGMT_SE0;
typedef union COMPUTE_STATIC_THREAD_MGMT_SE1   regCOMPUTE_STATIC_THREAD_MGMT_SE1;
typedef union COMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI regCOMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI;
typedef union COMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI regCOMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI;
typedef union COMPUTE_TBA_HI                   regCOMPUTE_TBA_HI;
typedef union COMPUTE_TBA_LO                   regCOMPUTE_TBA_LO;
typedef union COMPUTE_THREAD_TRACE_ENABLE__CI__VI regCOMPUTE_THREAD_TRACE_ENABLE__CI__VI;
typedef union COMPUTE_TMA_HI                   regCOMPUTE_TMA_HI;
typedef union COMPUTE_TMA_LO                   regCOMPUTE_TMA_LO;
typedef union COMPUTE_TMPRING_SIZE             regCOMPUTE_TMPRING_SIZE;
typedef union COMPUTE_USER_DATA_0              regCOMPUTE_USER_DATA_0;
typedef union COMPUTE_USER_DATA_1              regCOMPUTE_USER_DATA_1;
typedef union COMPUTE_USER_DATA_10             regCOMPUTE_USER_DATA_10;
typedef union COMPUTE_USER_DATA_11             regCOMPUTE_USER_DATA_11;
typedef union COMPUTE_USER_DATA_12             regCOMPUTE_USER_DATA_12;
typedef union COMPUTE_USER_DATA_13             regCOMPUTE_USER_DATA_13;
typedef union COMPUTE_USER_DATA_14             regCOMPUTE_USER_DATA_14;
typedef union COMPUTE_USER_DATA_15             regCOMPUTE_USER_DATA_15;
typedef union COMPUTE_USER_DATA_2              regCOMPUTE_USER_DATA_2;
typedef union COMPUTE_USER_DATA_3              regCOMPUTE_USER_DATA_3;
typedef union COMPUTE_USER_DATA_4              regCOMPUTE_USER_DATA_4;
typedef union COMPUTE_USER_DATA_5              regCOMPUTE_USER_DATA_5;
typedef union COMPUTE_USER_DATA_6              regCOMPUTE_USER_DATA_6;
typedef union COMPUTE_USER_DATA_7              regCOMPUTE_USER_DATA_7;
typedef union COMPUTE_USER_DATA_8              regCOMPUTE_USER_DATA_8;
typedef union COMPUTE_USER_DATA_9              regCOMPUTE_USER_DATA_9;
typedef union COMPUTE_VMID                     regCOMPUTE_VMID;
typedef union CONFIG_APER_SIZE                 regCONFIG_APER_SIZE;
typedef union CONFIG_CNTL                      regCONFIG_CNTL;
typedef union CONFIG_F0_BASE                   regCONFIG_F0_BASE;
typedef union CONFIG_MEMSIZE                   regCONFIG_MEMSIZE;
typedef union CONFIG_REG_APER_SIZE             regCONFIG_REG_APER_SIZE;
typedef union CORB_CONTROL__SI__VI             regCORB_CONTROL__SI__VI;
typedef union CORB_LOWER_BASE_ADDRESS__SI__VI  regCORB_LOWER_BASE_ADDRESS__SI__VI;
typedef union CORB_READ_POINTER__SI__VI        regCORB_READ_POINTER__SI__VI;
typedef union CORB_SIZE__SI__VI                regCORB_SIZE__SI__VI;
typedef union CORB_STATUS__SI__VI              regCORB_STATUS__SI__VI;
typedef union CORB_UPPER_BASE_ADDRESS__SI__VI  regCORB_UPPER_BASE_ADDRESS__SI__VI;
typedef union CORB_WRITE_POINTER__SI__VI       regCORB_WRITE_POINTER__SI__VI;
typedef union CPC1_CONFIG__CI                  regCPC1_CONFIG__CI;
typedef union CPC2_CONFIG__CI                  regCPC2_CONFIG__CI;
typedef union CPC_INT_CNTL__CI__VI             regCPC_INT_CNTL__CI__VI;
typedef union CPC_INT_CNTX_ID__CI__VI          regCPC_INT_CNTX_ID__CI__VI;
typedef union CPC_INT_STATUS__CI__VI           regCPC_INT_STATUS__CI__VI;
typedef union CPC_PERFCOUNTER0_HI__CI__VI      regCPC_PERFCOUNTER0_HI__CI__VI;
typedef union CPC_PERFCOUNTER0_LO__CI__VI      regCPC_PERFCOUNTER0_LO__CI__VI;
typedef union CPC_PERFCOUNTER0_SELECT1__CI__VI regCPC_PERFCOUNTER0_SELECT1__CI__VI;
typedef union CPC_PERFCOUNTER0_SELECT__CI__VI  regCPC_PERFCOUNTER0_SELECT__CI__VI;
typedef union CPC_PERFCOUNTER1_HI__CI__VI      regCPC_PERFCOUNTER1_HI__CI__VI;
typedef union CPC_PERFCOUNTER1_LO__CI__VI      regCPC_PERFCOUNTER1_LO__CI__VI;
typedef union CPC_PERFCOUNTER1_SELECT__CI__VI  regCPC_PERFCOUNTER1_SELECT__CI__VI;
typedef union CPF_PERFCOUNTER0_HI__CI__VI      regCPF_PERFCOUNTER0_HI__CI__VI;
typedef union CPF_PERFCOUNTER0_LO__CI__VI      regCPF_PERFCOUNTER0_LO__CI__VI;
typedef union CPF_PERFCOUNTER0_SELECT1__CI__VI regCPF_PERFCOUNTER0_SELECT1__CI__VI;
typedef union CPF_PERFCOUNTER0_SELECT__CI__VI  regCPF_PERFCOUNTER0_SELECT__CI__VI;
typedef union CPF_PERFCOUNTER1_HI__CI__VI      regCPF_PERFCOUNTER1_HI__CI__VI;
typedef union CPF_PERFCOUNTER1_LO__CI__VI      regCPF_PERFCOUNTER1_LO__CI__VI;
typedef union CPF_PERFCOUNTER1_SELECT__CI__VI  regCPF_PERFCOUNTER1_SELECT__CI__VI;
typedef union CPG_CONFIG__CI                   regCPG_CONFIG__CI;
typedef union CPG_PERFCOUNTER0_HI__CI__VI      regCPG_PERFCOUNTER0_HI__CI__VI;
typedef union CPG_PERFCOUNTER0_LO__CI__VI      regCPG_PERFCOUNTER0_LO__CI__VI;
typedef union CPG_PERFCOUNTER0_SELECT1__CI__VI regCPG_PERFCOUNTER0_SELECT1__CI__VI;
typedef union CPG_PERFCOUNTER0_SELECT__CI__VI  regCPG_PERFCOUNTER0_SELECT__CI__VI;
typedef union CPG_PERFCOUNTER1_HI__CI__VI      regCPG_PERFCOUNTER1_HI__CI__VI;
typedef union CPG_PERFCOUNTER1_LO__CI__VI      regCPG_PERFCOUNTER1_LO__CI__VI;
typedef union CPG_PERFCOUNTER1_SELECT__CI__VI  regCPG_PERFCOUNTER1_SELECT__CI__VI;
typedef union CP_APPEND_ADDR_HI__SI__CI        regCP_APPEND_ADDR_HI__SI__CI;
typedef union CP_APPEND_ADDR_HI__VI            regCP_APPEND_ADDR_HI__VI;
typedef union CP_APPEND_ADDR_LO                regCP_APPEND_ADDR_LO;
typedef union CP_APPEND_DATA                   regCP_APPEND_DATA;
typedef union CP_APPEND_LAST_CS_FENCE          regCP_APPEND_LAST_CS_FENCE;
typedef union CP_APPEND_LAST_PS_FENCE          regCP_APPEND_LAST_PS_FENCE;
typedef union CP_ATOMIC_PREOP_HI               regCP_ATOMIC_PREOP_HI;
typedef union CP_ATOMIC_PREOP_LO               regCP_ATOMIC_PREOP_LO;
typedef union CP_BUSY_STAT                     regCP_BUSY_STAT;
typedef union CP_CEQ1_AVAIL                    regCP_CEQ1_AVAIL;
typedef union CP_CEQ2_AVAIL                    regCP_CEQ2_AVAIL;
typedef union CP_CE_COMPARE_COUNT__CI__VI      regCP_CE_COMPARE_COUNT__CI__VI;
typedef union CP_CE_COUNTER__CI__VI            regCP_CE_COUNTER__CI__VI;
typedef union CP_CE_DE_COUNT__CI__VI           regCP_CE_DE_COUNT__CI__VI;
typedef union CP_CE_HEADER_DUMP                regCP_CE_HEADER_DUMP;
typedef union CP_CE_IB1_BASE_HI                regCP_CE_IB1_BASE_HI;
typedef union CP_CE_IB1_BASE_LO                regCP_CE_IB1_BASE_LO;
typedef union CP_CE_IB1_BUFSZ                  regCP_CE_IB1_BUFSZ;
typedef union CP_CE_IB1_OFFSET__CI__VI         regCP_CE_IB1_OFFSET__CI__VI;
typedef union CP_CE_IB2_BASE_HI                regCP_CE_IB2_BASE_HI;
typedef union CP_CE_IB2_BASE_LO                regCP_CE_IB2_BASE_LO;
typedef union CP_CE_IB2_BUFSZ                  regCP_CE_IB2_BUFSZ;
typedef union CP_CE_IB2_OFFSET__CI__VI         regCP_CE_IB2_OFFSET__CI__VI;
typedef union CP_CE_INIT_BASE_HI               regCP_CE_INIT_BASE_HI;
typedef union CP_CE_INIT_BASE_LO               regCP_CE_INIT_BASE_LO;
typedef union CP_CE_INIT_BUFSZ                 regCP_CE_INIT_BUFSZ;
typedef union CP_CE_INTR_ROUTINE_START__CI__VI regCP_CE_INTR_ROUTINE_START__CI__VI;
typedef union CP_CE_PRGRM_CNTR_START__CI__VI   regCP_CE_PRGRM_CNTR_START__CI__VI;
typedef union CP_CE_ROQ_IB1_STAT               regCP_CE_ROQ_IB1_STAT;
typedef union CP_CE_ROQ_IB2_STAT               regCP_CE_ROQ_IB2_STAT;
typedef union CP_CE_ROQ_RB_STAT                regCP_CE_ROQ_RB_STAT;
typedef union CP_CE_UCODE_ADDR                 regCP_CE_UCODE_ADDR;
typedef union CP_CE_UCODE_DATA                 regCP_CE_UCODE_DATA;
typedef union CP_CMD_DATA                      regCP_CMD_DATA;
typedef union CP_CMD_INDEX                     regCP_CMD_INDEX;
typedef union CP_CNTX_STAT__CI__VI             regCP_CNTX_STAT__CI__VI;
typedef union CP_CNTX_STAT__SI                 regCP_CNTX_STAT__SI;
typedef union CP_COHER_BASE                    regCP_COHER_BASE;
typedef union CP_COHER_BASE_HI__CI__VI         regCP_COHER_BASE_HI__CI__VI;
typedef union CP_COHER_CNTL                    regCP_COHER_CNTL;
typedef union CP_COHER_SIZE                    regCP_COHER_SIZE;
typedef union CP_COHER_SIZE_HI__CI__VI         regCP_COHER_SIZE_HI__CI__VI;
typedef union CP_COHER_START_DELAY             regCP_COHER_START_DELAY;
typedef union CP_COHER_STATUS                  regCP_COHER_STATUS;
typedef union CP_CONFIG__SI__VI                regCP_CONFIG__SI__VI;
typedef union CP_CONTEXT_CNTL__CI__VI          regCP_CONTEXT_CNTL__CI__VI;
typedef union CP_CPC_BUSY_STAT__CI__VI         regCP_CPC_BUSY_STAT__CI__VI;
typedef union CP_CPC_GRBM_FREE_COUNT__CI__VI   regCP_CPC_GRBM_FREE_COUNT__CI__VI;
typedef union CP_CPC_HALT_HYST_COUNT__CI__VI   regCP_CPC_HALT_HYST_COUNT__CI__VI;
typedef union CP_CPC_MC_CNTL__CI               regCP_CPC_MC_CNTL__CI;
typedef union CP_CPC_SCRATCH_DATA__CI__VI      regCP_CPC_SCRATCH_DATA__CI__VI;
typedef union CP_CPC_SCRATCH_INDEX__CI__VI     regCP_CPC_SCRATCH_INDEX__CI__VI;
typedef union CP_CPC_STALLED_STAT1__CI__VI     regCP_CPC_STALLED_STAT1__CI__VI;
typedef union CP_CPC_STATUS__CI__VI            regCP_CPC_STATUS__CI__VI;
typedef union CP_CPF_BUSY_STAT__CI__VI         regCP_CPF_BUSY_STAT__CI__VI;
typedef union CP_CPF_STALLED_STAT1__CI__VI     regCP_CPF_STALLED_STAT1__CI__VI;
typedef union CP_CPF_STATUS__CI__VI            regCP_CPF_STATUS__CI__VI;
typedef union CP_CSF_CNTL                      regCP_CSF_CNTL;
typedef union CP_CSF_STAT                      regCP_CSF_STAT;
typedef union CP_DEVICE_ID__CI__VI             regCP_DEVICE_ID__CI__VI;
typedef union CP_DE_CE_COUNT__CI__VI           regCP_DE_CE_COUNT__CI__VI;
typedef union CP_DE_DE_COUNT__CI__VI           regCP_DE_DE_COUNT__CI__VI;
typedef union CP_DE_LAST_INVAL_COUNT__CI__VI   regCP_DE_LAST_INVAL_COUNT__CI__VI;
typedef union CP_DFY_ADDR_HI__CI__VI           regCP_DFY_ADDR_HI__CI__VI;
typedef union CP_DFY_ADDR_LO__CI__VI           regCP_DFY_ADDR_LO__CI__VI;
typedef union CP_DFY_CNTL__CI                  regCP_DFY_CNTL__CI;
typedef union CP_DFY_CNTL__VI                  regCP_DFY_CNTL__VI;
typedef union CP_DFY_DATA_0__CI__VI            regCP_DFY_DATA_0__CI__VI;
typedef union CP_DFY_DATA_10__CI__VI           regCP_DFY_DATA_10__CI__VI;
typedef union CP_DFY_DATA_11__CI__VI           regCP_DFY_DATA_11__CI__VI;
typedef union CP_DFY_DATA_12__CI__VI           regCP_DFY_DATA_12__CI__VI;
typedef union CP_DFY_DATA_13__CI__VI           regCP_DFY_DATA_13__CI__VI;
typedef union CP_DFY_DATA_14__CI__VI           regCP_DFY_DATA_14__CI__VI;
typedef union CP_DFY_DATA_15__CI__VI           regCP_DFY_DATA_15__CI__VI;
typedef union CP_DFY_DATA_1__CI__VI            regCP_DFY_DATA_1__CI__VI;
typedef union CP_DFY_DATA_2__CI__VI            regCP_DFY_DATA_2__CI__VI;
typedef union CP_DFY_DATA_3__CI__VI            regCP_DFY_DATA_3__CI__VI;
typedef union CP_DFY_DATA_4__CI__VI            regCP_DFY_DATA_4__CI__VI;
typedef union CP_DFY_DATA_5__CI__VI            regCP_DFY_DATA_5__CI__VI;
typedef union CP_DFY_DATA_6__CI__VI            regCP_DFY_DATA_6__CI__VI;
typedef union CP_DFY_DATA_7__CI__VI            regCP_DFY_DATA_7__CI__VI;
typedef union CP_DFY_DATA_8__CI__VI            regCP_DFY_DATA_8__CI__VI;
typedef union CP_DFY_DATA_9__CI__VI            regCP_DFY_DATA_9__CI__VI;
typedef union CP_DFY_STAT__CI__VI              regCP_DFY_STAT__CI__VI;
typedef union CP_DMA_CNTL                      regCP_DMA_CNTL;
typedef union CP_DMA_ME_COMMAND                regCP_DMA_ME_COMMAND;
typedef union CP_DMA_ME_CONTROL__CI            regCP_DMA_ME_CONTROL__CI;
typedef union CP_DMA_ME_CONTROL__VI            regCP_DMA_ME_CONTROL__VI;
typedef union CP_DMA_ME_DST_ADDR               regCP_DMA_ME_DST_ADDR;
typedef union CP_DMA_ME_DST_ADDR_HI            regCP_DMA_ME_DST_ADDR_HI;
typedef union CP_DMA_ME_SRC_ADDR               regCP_DMA_ME_SRC_ADDR;
typedef union CP_DMA_ME_SRC_ADDR_HI            regCP_DMA_ME_SRC_ADDR_HI;
typedef union CP_DMA_PFP_COMMAND               regCP_DMA_PFP_COMMAND;
typedef union CP_DMA_PFP_CONTROL__CI           regCP_DMA_PFP_CONTROL__CI;
typedef union CP_DMA_PFP_CONTROL__VI           regCP_DMA_PFP_CONTROL__VI;
typedef union CP_DMA_PFP_DST_ADDR              regCP_DMA_PFP_DST_ADDR;
typedef union CP_DMA_PFP_DST_ADDR_HI           regCP_DMA_PFP_DST_ADDR_HI;
typedef union CP_DMA_PFP_SRC_ADDR              regCP_DMA_PFP_SRC_ADDR;
typedef union CP_DMA_PFP_SRC_ADDR_HI           regCP_DMA_PFP_SRC_ADDR_HI;
typedef union CP_DMA_READ_TAGS                 regCP_DMA_READ_TAGS;
typedef union CP_ECC_FIRSTOCCURRENCE__SI__CI   regCP_ECC_FIRSTOCCURRENCE__SI__CI;
typedef union CP_ECC_FIRSTOCCURRENCE__VI       regCP_ECC_FIRSTOCCURRENCE__VI;
typedef union CP_ECC_FIRSTOCCURRENCE_RING0__SI__CI regCP_ECC_FIRSTOCCURRENCE_RING0__SI__CI;
typedef union CP_ECC_FIRSTOCCURRENCE_RING0__VI regCP_ECC_FIRSTOCCURRENCE_RING0__VI;
typedef union CP_ECC_FIRSTOCCURRENCE_RING1__SI__CI regCP_ECC_FIRSTOCCURRENCE_RING1__SI__CI;
typedef union CP_ECC_FIRSTOCCURRENCE_RING1__VI regCP_ECC_FIRSTOCCURRENCE_RING1__VI;
typedef union CP_ECC_FIRSTOCCURRENCE_RING2__SI__CI regCP_ECC_FIRSTOCCURRENCE_RING2__SI__CI;
typedef union CP_ECC_FIRSTOCCURRENCE_RING2__VI regCP_ECC_FIRSTOCCURRENCE_RING2__VI;
typedef union CP_ENDIAN_SWAP__CI__VI           regCP_ENDIAN_SWAP__CI__VI;
typedef union CP_EOP_DONE_ADDR_HI__CI__VI      regCP_EOP_DONE_ADDR_HI__CI__VI;
typedef union CP_EOP_DONE_ADDR_HI__SI          regCP_EOP_DONE_ADDR_HI__SI;
typedef union CP_EOP_DONE_ADDR_LO__CI__VI      regCP_EOP_DONE_ADDR_LO__CI__VI;
typedef union CP_EOP_DONE_ADDR_LO__SI          regCP_EOP_DONE_ADDR_LO__SI;
typedef union CP_EOP_DONE_DATA_CNTL__CI__VI    regCP_EOP_DONE_DATA_CNTL__CI__VI;
typedef union CP_EOP_DONE_DATA_HI__CI__VI      regCP_EOP_DONE_DATA_HI__CI__VI;
typedef union CP_EOP_DONE_DATA_HI__SI          regCP_EOP_DONE_DATA_HI__SI;
typedef union CP_EOP_DONE_DATA_LO__CI__VI      regCP_EOP_DONE_DATA_LO__CI__VI;
typedef union CP_EOP_DONE_DATA_LO__SI          regCP_EOP_DONE_DATA_LO__SI;
typedef union CP_EOP_DONE_EVENT_CNTL__CI       regCP_EOP_DONE_EVENT_CNTL__CI;
typedef union CP_EOP_DONE_EVENT_CNTL__VI       regCP_EOP_DONE_EVENT_CNTL__VI;
typedef union CP_EOP_LAST_FENCE_HI             regCP_EOP_LAST_FENCE_HI;
typedef union CP_EOP_LAST_FENCE_LO             regCP_EOP_LAST_FENCE_LO;
typedef union CP_FETCHER_SOURCE__CI            regCP_FETCHER_SOURCE__CI;
typedef union CP_GDS_ATOMIC0_PREOP_HI          regCP_GDS_ATOMIC0_PREOP_HI;
typedef union CP_GDS_ATOMIC0_PREOP_LO          regCP_GDS_ATOMIC0_PREOP_LO;
typedef union CP_GDS_ATOMIC1_PREOP_HI          regCP_GDS_ATOMIC1_PREOP_HI;
typedef union CP_GDS_ATOMIC1_PREOP_LO          regCP_GDS_ATOMIC1_PREOP_LO;
typedef union CP_GRBM_FREE_COUNT               regCP_GRBM_FREE_COUNT;
typedef union CP_HPD_EOP_BASE_ADDR_HI__CI      regCP_HPD_EOP_BASE_ADDR_HI__CI;
typedef union CP_HPD_EOP_BASE_ADDR__CI         regCP_HPD_EOP_BASE_ADDR__CI;
typedef union CP_HPD_EOP_CONTROL__CI           regCP_HPD_EOP_CONTROL__CI;
typedef union CP_HPD_EOP_VMID__CI              regCP_HPD_EOP_VMID__CI;
typedef union CP_HPD_ROQ_OFFSETS__CI__VI       regCP_HPD_ROQ_OFFSETS__CI__VI;
typedef union CP_HQD_ACTIVE__CI__VI            regCP_HQD_ACTIVE__CI__VI;
typedef union CP_HQD_ATOMIC0_PREOP_HI__CI__VI  regCP_HQD_ATOMIC0_PREOP_HI__CI__VI;
typedef union CP_HQD_ATOMIC0_PREOP_LO__CI__VI  regCP_HQD_ATOMIC0_PREOP_LO__CI__VI;
typedef union CP_HQD_ATOMIC1_PREOP_HI__CI__VI  regCP_HQD_ATOMIC1_PREOP_HI__CI__VI;
typedef union CP_HQD_ATOMIC1_PREOP_LO__CI__VI  regCP_HQD_ATOMIC1_PREOP_LO__CI__VI;
typedef union CP_HQD_DEQUEUE_REQUEST__CI__VI   regCP_HQD_DEQUEUE_REQUEST__CI__VI;
typedef union CP_HQD_DMA_OFFLOAD__CI__VI       regCP_HQD_DMA_OFFLOAD__CI__VI;
typedef union CP_HQD_HQ_SCHEDULER0__CI         regCP_HQD_HQ_SCHEDULER0__CI;
typedef union CP_HQD_HQ_SCHEDULER0__VI         regCP_HQD_HQ_SCHEDULER0__VI;
typedef union CP_HQD_HQ_SCHEDULER1__CI__VI     regCP_HQD_HQ_SCHEDULER1__CI__VI;
typedef union CP_HQD_IB_BASE_ADDR_HI__CI__VI   regCP_HQD_IB_BASE_ADDR_HI__CI__VI;
typedef union CP_HQD_IB_BASE_ADDR__CI__VI      regCP_HQD_IB_BASE_ADDR__CI__VI;
typedef union CP_HQD_IB_CONTROL__CI            regCP_HQD_IB_CONTROL__CI;
typedef union CP_HQD_IB_CONTROL__VI            regCP_HQD_IB_CONTROL__VI;
typedef union CP_HQD_IB_RPTR__CI__VI           regCP_HQD_IB_RPTR__CI__VI;
typedef union CP_HQD_IQ_RPTR__CI__VI           regCP_HQD_IQ_RPTR__CI__VI;
typedef union CP_HQD_IQ_TIMER__CI              regCP_HQD_IQ_TIMER__CI;
typedef union CP_HQD_IQ_TIMER__VI              regCP_HQD_IQ_TIMER__VI;
typedef union CP_HQD_MSG_TYPE__CI__VI          regCP_HQD_MSG_TYPE__CI__VI;
typedef union CP_HQD_PERSISTENT_STATE__CI__VI  regCP_HQD_PERSISTENT_STATE__CI__VI;
typedef union CP_HQD_PIPE_PRIORITY__CI__VI     regCP_HQD_PIPE_PRIORITY__CI__VI;
typedef union CP_HQD_PQ_BASE_HI__CI__VI        regCP_HQD_PQ_BASE_HI__CI__VI;
typedef union CP_HQD_PQ_BASE__CI__VI           regCP_HQD_PQ_BASE__CI__VI;
typedef union CP_HQD_PQ_CONTROL__CI            regCP_HQD_PQ_CONTROL__CI;
typedef union CP_HQD_PQ_CONTROL__VI            regCP_HQD_PQ_CONTROL__VI;
typedef union CP_HQD_PQ_DOORBELL_CONTROL__CI__VI regCP_HQD_PQ_DOORBELL_CONTROL__CI__VI;
typedef union CP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI regCP_HQD_PQ_RPTR_REPORT_ADDR_HI__CI__VI;
typedef union CP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI regCP_HQD_PQ_RPTR_REPORT_ADDR__CI__VI;
typedef union CP_HQD_PQ_RPTR__CI__VI           regCP_HQD_PQ_RPTR__CI__VI;
typedef union CP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI regCP_HQD_PQ_WPTR_POLL_ADDR_HI__CI__VI;
typedef union CP_HQD_PQ_WPTR_POLL_ADDR__CI__VI regCP_HQD_PQ_WPTR_POLL_ADDR__CI__VI;
typedef union CP_HQD_PQ_WPTR__CI__VI           regCP_HQD_PQ_WPTR__CI__VI;
typedef union CP_HQD_QUANTUM__CI__VI           regCP_HQD_QUANTUM__CI__VI;
typedef union CP_HQD_QUEUE_PRIORITY__CI__VI    regCP_HQD_QUEUE_PRIORITY__CI__VI;
typedef union CP_HQD_SEMA_CMD__CI__VI          regCP_HQD_SEMA_CMD__CI__VI;
typedef union CP_HQD_VMID__CI__VI              regCP_HQD_VMID__CI__VI;
typedef union CP_IB1_BASE_HI                   regCP_IB1_BASE_HI;
typedef union CP_IB1_BASE_LO                   regCP_IB1_BASE_LO;
typedef union CP_IB1_BUFSZ                     regCP_IB1_BUFSZ;
typedef union CP_IB1_OFFSET                    regCP_IB1_OFFSET;
typedef union CP_IB1_PREAMBLE_BEGIN            regCP_IB1_PREAMBLE_BEGIN;
typedef union CP_IB1_PREAMBLE_END              regCP_IB1_PREAMBLE_END;
typedef union CP_IB2_BASE_HI                   regCP_IB2_BASE_HI;
typedef union CP_IB2_BASE_LO                   regCP_IB2_BASE_LO;
typedef union CP_IB2_BUFSZ                     regCP_IB2_BUFSZ;
typedef union CP_IB2_OFFSET                    regCP_IB2_OFFSET;
typedef union CP_IB2_PREAMBLE_BEGIN            regCP_IB2_PREAMBLE_BEGIN;
typedef union CP_IB2_PREAMBLE_END              regCP_IB2_PREAMBLE_END;
typedef union CP_INT_CNTL_RING0__CI__VI        regCP_INT_CNTL_RING0__CI__VI;
typedef union CP_INT_CNTL_RING0__SI            regCP_INT_CNTL_RING0__SI;
typedef union CP_INT_CNTL_RING1__CI__VI        regCP_INT_CNTL_RING1__CI__VI;
typedef union CP_INT_CNTL_RING1__SI            regCP_INT_CNTL_RING1__SI;
typedef union CP_INT_CNTL_RING2__CI__VI        regCP_INT_CNTL_RING2__CI__VI;
typedef union CP_INT_CNTL_RING2__SI            regCP_INT_CNTL_RING2__SI;
typedef union CP_INT_CNTL__CI__VI              regCP_INT_CNTL__CI__VI;
typedef union CP_INT_CNTL__SI                  regCP_INT_CNTL__SI;
typedef union CP_INT_STATUS_RING0__CI          regCP_INT_STATUS_RING0__CI;
typedef union CP_INT_STATUS_RING0__VI          regCP_INT_STATUS_RING0__VI;
typedef union CP_INT_STATUS_RING0__SI          regCP_INT_STATUS_RING0__SI;
typedef union CP_INT_STATUS_RING1__CI__VI      regCP_INT_STATUS_RING1__CI__VI;
typedef union CP_INT_STATUS_RING1__SI          regCP_INT_STATUS_RING1__SI;
typedef union CP_INT_STATUS_RING2__CI__VI      regCP_INT_STATUS_RING2__CI__VI;
typedef union CP_INT_STATUS_RING2__SI          regCP_INT_STATUS_RING2__SI;
typedef union CP_INT_STATUS__CI__VI            regCP_INT_STATUS__CI__VI;
typedef union CP_INT_STATUS__SI                regCP_INT_STATUS__SI;
typedef union CP_INT_STAT_DEBUG__CI__VI        regCP_INT_STAT_DEBUG__CI__VI;
typedef union CP_INT_STAT_DEBUG__SI            regCP_INT_STAT_DEBUG__SI;
typedef union CP_IQ_WAIT_TIME1__CI__VI         regCP_IQ_WAIT_TIME1__CI__VI;
typedef union CP_IQ_WAIT_TIME2__CI__VI         regCP_IQ_WAIT_TIME2__CI__VI;
typedef union CP_MAX_CONTEXT__CI__VI           regCP_MAX_CONTEXT__CI__VI;
typedef union CP_MC_PACK_DELAY_CNT__SI__CI     regCP_MC_PACK_DELAY_CNT__SI__CI;
typedef union CP_MC_TAG_CNTL__CI               regCP_MC_TAG_CNTL__CI;
typedef union CP_MC_TAG_DATA__CI               regCP_MC_TAG_DATA__CI;
typedef union CP_ME0_PIPE0_PRIORITY__CI__VI    regCP_ME0_PIPE0_PRIORITY__CI__VI;
typedef union CP_ME0_PIPE0_VMID__CI__VI        regCP_ME0_PIPE0_VMID__CI__VI;
typedef union CP_ME0_PIPE1_PRIORITY__CI__VI    regCP_ME0_PIPE1_PRIORITY__CI__VI;
typedef union CP_ME0_PIPE1_VMID__CI__VI        regCP_ME0_PIPE1_VMID__CI__VI;
typedef union CP_ME0_PIPE2_PRIORITY__CI__VI    regCP_ME0_PIPE2_PRIORITY__CI__VI;
typedef union CP_ME0_PIPE_PRIORITY_CNTS__CI__VI regCP_ME0_PIPE_PRIORITY_CNTS__CI__VI;
typedef union CP_ME1_INT_STAT_DEBUG__CI__VI    regCP_ME1_INT_STAT_DEBUG__CI__VI;
typedef union CP_ME1_PIPE0_INT_CNTL__CI__VI    regCP_ME1_PIPE0_INT_CNTL__CI__VI;
typedef union CP_ME1_PIPE0_INT_STATUS__CI__VI  regCP_ME1_PIPE0_INT_STATUS__CI__VI;
typedef union CP_ME1_PIPE0_PRIORITY__CI__VI    regCP_ME1_PIPE0_PRIORITY__CI__VI;
typedef union CP_ME1_PIPE1_INT_CNTL__CI__VI    regCP_ME1_PIPE1_INT_CNTL__CI__VI;
typedef union CP_ME1_PIPE1_INT_STATUS__CI__VI  regCP_ME1_PIPE1_INT_STATUS__CI__VI;
typedef union CP_ME1_PIPE1_PRIORITY__CI__VI    regCP_ME1_PIPE1_PRIORITY__CI__VI;
typedef union CP_ME1_PIPE2_INT_CNTL__CI__VI    regCP_ME1_PIPE2_INT_CNTL__CI__VI;
typedef union CP_ME1_PIPE2_INT_STATUS__CI__VI  regCP_ME1_PIPE2_INT_STATUS__CI__VI;
typedef union CP_ME1_PIPE2_PRIORITY__CI__VI    regCP_ME1_PIPE2_PRIORITY__CI__VI;
typedef union CP_ME1_PIPE3_INT_CNTL__CI__VI    regCP_ME1_PIPE3_INT_CNTL__CI__VI;
typedef union CP_ME1_PIPE3_INT_STATUS__CI__VI  regCP_ME1_PIPE3_INT_STATUS__CI__VI;
typedef union CP_ME1_PIPE3_PRIORITY__CI__VI    regCP_ME1_PIPE3_PRIORITY__CI__VI;
typedef union CP_ME1_PIPE_PRIORITY_CNTS__CI__VI regCP_ME1_PIPE_PRIORITY_CNTS__CI__VI;
typedef union CP_ME2_INT_STAT_DEBUG__CI__VI    regCP_ME2_INT_STAT_DEBUG__CI__VI;
typedef union CP_ME2_PIPE0_INT_CNTL__CI__VI    regCP_ME2_PIPE0_INT_CNTL__CI__VI;
typedef union CP_ME2_PIPE0_INT_STATUS__CI__VI  regCP_ME2_PIPE0_INT_STATUS__CI__VI;
typedef union CP_ME2_PIPE0_PRIORITY__CI__VI    regCP_ME2_PIPE0_PRIORITY__CI__VI;
typedef union CP_ME2_PIPE1_INT_CNTL__CI__VI    regCP_ME2_PIPE1_INT_CNTL__CI__VI;
typedef union CP_ME2_PIPE1_INT_STATUS__CI__VI  regCP_ME2_PIPE1_INT_STATUS__CI__VI;
typedef union CP_ME2_PIPE1_PRIORITY__CI__VI    regCP_ME2_PIPE1_PRIORITY__CI__VI;
typedef union CP_ME2_PIPE2_INT_CNTL__CI__VI    regCP_ME2_PIPE2_INT_CNTL__CI__VI;
typedef union CP_ME2_PIPE2_INT_STATUS__CI__VI  regCP_ME2_PIPE2_INT_STATUS__CI__VI;
typedef union CP_ME2_PIPE2_PRIORITY__CI__VI    regCP_ME2_PIPE2_PRIORITY__CI__VI;
typedef union CP_ME2_PIPE3_INT_CNTL__CI__VI    regCP_ME2_PIPE3_INT_CNTL__CI__VI;
typedef union CP_ME2_PIPE3_INT_STATUS__CI__VI  regCP_ME2_PIPE3_INT_STATUS__CI__VI;
typedef union CP_ME2_PIPE3_PRIORITY__CI__VI    regCP_ME2_PIPE3_PRIORITY__CI__VI;
typedef union CP_ME2_PIPE_PRIORITY_CNTS__CI__VI regCP_ME2_PIPE_PRIORITY_CNTS__CI__VI;
typedef union CP_MEC1_F32_INTERRUPT__CI        regCP_MEC1_F32_INTERRUPT__CI;
typedef union CP_MEC1_F32_INTERRUPT__VI        regCP_MEC1_F32_INTERRUPT__VI;
typedef union CP_MEC1_INTR_ROUTINE_START__CI__VI regCP_MEC1_INTR_ROUTINE_START__CI__VI;
typedef union CP_MEC1_PRGRM_CNTR_START__CI__VI regCP_MEC1_PRGRM_CNTR_START__CI__VI;
typedef union CP_MEC2_F32_INTERRUPT__CI        regCP_MEC2_F32_INTERRUPT__CI;
typedef union CP_MEC2_F32_INTERRUPT__VI        regCP_MEC2_F32_INTERRUPT__VI;
typedef union CP_MEC2_INTR_ROUTINE_START__CI__VI regCP_MEC2_INTR_ROUTINE_START__CI__VI;
typedef union CP_MEC2_PRGRM_CNTR_START__CI__VI regCP_MEC2_PRGRM_CNTR_START__CI__VI;
typedef union CP_MEC_CNTL__CI__VI              regCP_MEC_CNTL__CI__VI;
typedef union CP_MEC_ME1_HEADER_DUMP__CI__VI   regCP_MEC_ME1_HEADER_DUMP__CI__VI;
typedef union CP_MEC_ME1_UCODE_ADDR__CI__VI    regCP_MEC_ME1_UCODE_ADDR__CI__VI;
typedef union CP_MEC_ME1_UCODE_DATA__CI__VI    regCP_MEC_ME1_UCODE_DATA__CI__VI;
typedef union CP_MEC_ME2_HEADER_DUMP__CI__VI   regCP_MEC_ME2_HEADER_DUMP__CI__VI;
typedef union CP_MEC_ME2_UCODE_ADDR__CI__VI    regCP_MEC_ME2_UCODE_ADDR__CI__VI;
typedef union CP_MEC_ME2_UCODE_DATA__CI__VI    regCP_MEC_ME2_UCODE_DATA__CI__VI;
typedef union CP_MEM_SLP_CNTL                  regCP_MEM_SLP_CNTL;
typedef union CP_MEQ_AVAIL                     regCP_MEQ_AVAIL;
typedef union CP_MEQ_STAT                      regCP_MEQ_STAT;
typedef union CP_MEQ_STQ_THRESHOLD__CI__VI     regCP_MEQ_STQ_THRESHOLD__CI__VI;
typedef union CP_MEQ_THRESHOLDS                regCP_MEQ_THRESHOLDS;
typedef union CP_ME_ATOMIC_PREOP_HI__CI__VI    regCP_ME_ATOMIC_PREOP_HI__CI__VI;
typedef union CP_ME_ATOMIC_PREOP_LO__CI__VI    regCP_ME_ATOMIC_PREOP_LO__CI__VI;
typedef union CP_ME_CNTL                       regCP_ME_CNTL;
typedef union CP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI regCP_ME_GDS_ATOMIC0_PREOP_HI__CI__VI;
typedef union CP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI regCP_ME_GDS_ATOMIC0_PREOP_LO__CI__VI;
typedef union CP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI regCP_ME_GDS_ATOMIC1_PREOP_HI__CI__VI;
typedef union CP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI regCP_ME_GDS_ATOMIC1_PREOP_LO__CI__VI;
typedef union CP_ME_HEADER_DUMP                regCP_ME_HEADER_DUMP;
typedef union CP_ME_INTR_ROUTINE_START__CI__VI regCP_ME_INTR_ROUTINE_START__CI__VI;
typedef union CP_ME_MC_RADDR_HI                regCP_ME_MC_RADDR_HI;
typedef union CP_ME_MC_RADDR_LO                regCP_ME_MC_RADDR_LO;
typedef union CP_ME_MC_WADDR_HI                regCP_ME_MC_WADDR_HI;
typedef union CP_ME_MC_WADDR_LO                regCP_ME_MC_WADDR_LO;
typedef union CP_ME_MC_WDATA_HI                regCP_ME_MC_WDATA_HI;
typedef union CP_ME_MC_WDATA_LO                regCP_ME_MC_WDATA_LO;
typedef union CP_ME_PREEMPTION__SI__CI         regCP_ME_PREEMPTION__SI__CI;
typedef union CP_ME_PREEMPTION__VI             regCP_ME_PREEMPTION__VI;
typedef union CP_ME_PRGRM_CNTR_START__CI__VI   regCP_ME_PRGRM_CNTR_START__CI__VI;
typedef union CP_ME_RAM_DATA                   regCP_ME_RAM_DATA;
typedef union CP_ME_RAM_RADDR                  regCP_ME_RAM_RADDR;
typedef union CP_ME_RAM_WADDR                  regCP_ME_RAM_WADDR;
typedef union CP_MQD_BASE_ADDR_HI__CI__VI      regCP_MQD_BASE_ADDR_HI__CI__VI;
typedef union CP_MQD_BASE_ADDR__CI__VI         regCP_MQD_BASE_ADDR__CI__VI;
typedef union CP_MQD_CONTROL__CI               regCP_MQD_CONTROL__CI;
typedef union CP_MQD_CONTROL__VI               regCP_MQD_CONTROL__VI;
typedef union CP_NUM_PRIM_NEEDED_COUNT0_HI     regCP_NUM_PRIM_NEEDED_COUNT0_HI;
typedef union CP_NUM_PRIM_NEEDED_COUNT0_LO     regCP_NUM_PRIM_NEEDED_COUNT0_LO;
typedef union CP_NUM_PRIM_NEEDED_COUNT1_HI     regCP_NUM_PRIM_NEEDED_COUNT1_HI;
typedef union CP_NUM_PRIM_NEEDED_COUNT1_LO     regCP_NUM_PRIM_NEEDED_COUNT1_LO;
typedef union CP_NUM_PRIM_NEEDED_COUNT2_HI     regCP_NUM_PRIM_NEEDED_COUNT2_HI;
typedef union CP_NUM_PRIM_NEEDED_COUNT2_LO     regCP_NUM_PRIM_NEEDED_COUNT2_LO;
typedef union CP_NUM_PRIM_NEEDED_COUNT3_HI     regCP_NUM_PRIM_NEEDED_COUNT3_HI;
typedef union CP_NUM_PRIM_NEEDED_COUNT3_LO     regCP_NUM_PRIM_NEEDED_COUNT3_LO;
typedef union CP_NUM_PRIM_WRITTEN_COUNT0_HI    regCP_NUM_PRIM_WRITTEN_COUNT0_HI;
typedef union CP_NUM_PRIM_WRITTEN_COUNT0_LO    regCP_NUM_PRIM_WRITTEN_COUNT0_LO;
typedef union CP_NUM_PRIM_WRITTEN_COUNT1_HI    regCP_NUM_PRIM_WRITTEN_COUNT1_HI;
typedef union CP_NUM_PRIM_WRITTEN_COUNT1_LO    regCP_NUM_PRIM_WRITTEN_COUNT1_LO;
typedef union CP_NUM_PRIM_WRITTEN_COUNT2_HI    regCP_NUM_PRIM_WRITTEN_COUNT2_HI;
typedef union CP_NUM_PRIM_WRITTEN_COUNT2_LO    regCP_NUM_PRIM_WRITTEN_COUNT2_LO;
typedef union CP_NUM_PRIM_WRITTEN_COUNT3_HI    regCP_NUM_PRIM_WRITTEN_COUNT3_HI;
typedef union CP_NUM_PRIM_WRITTEN_COUNT3_LO    regCP_NUM_PRIM_WRITTEN_COUNT3_LO;
typedef union CP_PA_CINVOC_COUNT_HI            regCP_PA_CINVOC_COUNT_HI;
typedef union CP_PA_CINVOC_COUNT_LO            regCP_PA_CINVOC_COUNT_LO;
typedef union CP_PA_CPRIM_COUNT_HI             regCP_PA_CPRIM_COUNT_HI;
typedef union CP_PA_CPRIM_COUNT_LO             regCP_PA_CPRIM_COUNT_LO;
typedef union CP_PERFMON_CNTL                  regCP_PERFMON_CNTL;
typedef union CP_PERFMON_CNTX_CNTL             regCP_PERFMON_CNTX_CNTL;
typedef union CP_PFP_ATOMIC_PREOP_HI__CI__VI   regCP_PFP_ATOMIC_PREOP_HI__CI__VI;
typedef union CP_PFP_ATOMIC_PREOP_LO__CI__VI   regCP_PFP_ATOMIC_PREOP_LO__CI__VI;
typedef union CP_PFP_F32_INTERRUPT__CI__VI     regCP_PFP_F32_INTERRUPT__CI__VI;
typedef union CP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI regCP_PFP_GDS_ATOMIC0_PREOP_HI__CI__VI;
typedef union CP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI regCP_PFP_GDS_ATOMIC0_PREOP_LO__CI__VI;
typedef union CP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI regCP_PFP_GDS_ATOMIC1_PREOP_HI__CI__VI;
typedef union CP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI regCP_PFP_GDS_ATOMIC1_PREOP_LO__CI__VI;
typedef union CP_PFP_HEADER_DUMP               regCP_PFP_HEADER_DUMP;
typedef union CP_PFP_IB_CONTROL                regCP_PFP_IB_CONTROL;
typedef union CP_PFP_INTR_ROUTINE_START__CI__VI regCP_PFP_INTR_ROUTINE_START__CI__VI;
typedef union CP_PFP_LOAD_CONTROL__SI__CI      regCP_PFP_LOAD_CONTROL__SI__CI;
typedef union CP_PFP_LOAD_CONTROL__VI          regCP_PFP_LOAD_CONTROL__VI;
typedef union CP_PFP_PRGRM_CNTR_START__CI__VI  regCP_PFP_PRGRM_CNTR_START__CI__VI;
typedef union CP_PFP_UCODE_ADDR                regCP_PFP_UCODE_ADDR;
typedef union CP_PFP_UCODE_DATA                regCP_PFP_UCODE_DATA;
typedef union CP_PIPEID__CI__VI                regCP_PIPEID__CI__VI;
typedef union CP_PIPE_STATS_ADDR_HI__CI__VI    regCP_PIPE_STATS_ADDR_HI__CI__VI;
typedef union CP_PIPE_STATS_ADDR_HI__SI        regCP_PIPE_STATS_ADDR_HI__SI;
typedef union CP_PIPE_STATS_ADDR_LO            regCP_PIPE_STATS_ADDR_LO;
typedef union CP_PQ_WPTR_POLL_CNTL1__CI__VI    regCP_PQ_WPTR_POLL_CNTL1__CI__VI;
typedef union CP_PQ_WPTR_POLL_CNTL__CI__VI     regCP_PQ_WPTR_POLL_CNTL__CI__VI;
typedef union CP_PRT_LOD_STATS_CNTL0__CI__VI   regCP_PRT_LOD_STATS_CNTL0__CI__VI;
typedef union CP_PRT_LOD_STATS_CNTL1__CI__VI   regCP_PRT_LOD_STATS_CNTL1__CI__VI;
typedef union CP_PRT_LOD_STATS_CNTL2__CI__VI   regCP_PRT_LOD_STATS_CNTL2__CI__VI;
typedef union CP_PWR_CNTL__CI                  regCP_PWR_CNTL__CI;
typedef union CP_PWR_CNTL__VI                  regCP_PWR_CNTL__VI;
typedef union CP_PWR_CNTL__SI                  regCP_PWR_CNTL__SI;
typedef union CP_QUEUE_THRESHOLDS              regCP_QUEUE_THRESHOLDS;
typedef union CP_RB0_BASE                      regCP_RB0_BASE;
typedef union CP_RB0_BASE_HI__CI__VI           regCP_RB0_BASE_HI__CI__VI;
typedef union CP_RB0_CNTL__CI                  regCP_RB0_CNTL__CI;
typedef union CP_RB0_CNTL__VI                  regCP_RB0_CNTL__VI;
typedef union CP_RB0_CNTL__SI                  regCP_RB0_CNTL__SI;
typedef union CP_RB0_RPTR                      regCP_RB0_RPTR;
typedef union CP_RB0_RPTR_ADDR                 regCP_RB0_RPTR_ADDR;
typedef union CP_RB0_RPTR_ADDR_HI              regCP_RB0_RPTR_ADDR_HI;
typedef union CP_RB0_WPTR                      regCP_RB0_WPTR;
typedef union CP_RB1_BASE                      regCP_RB1_BASE;
typedef union CP_RB1_BASE_HI__CI__VI           regCP_RB1_BASE_HI__CI__VI;
typedef union CP_RB1_CNTL__SI__CI              regCP_RB1_CNTL__SI__CI;
typedef union CP_RB1_CNTL__VI                  regCP_RB1_CNTL__VI;
typedef union CP_RB1_RPTR                      regCP_RB1_RPTR;
typedef union CP_RB1_RPTR_ADDR                 regCP_RB1_RPTR_ADDR;
typedef union CP_RB1_RPTR_ADDR_HI              regCP_RB1_RPTR_ADDR_HI;
typedef union CP_RB1_WPTR                      regCP_RB1_WPTR;
typedef union CP_RB2_BASE                      regCP_RB2_BASE;
typedef union CP_RB2_CNTL__SI__CI              regCP_RB2_CNTL__SI__CI;
typedef union CP_RB2_CNTL__VI                  regCP_RB2_CNTL__VI;
typedef union CP_RB2_RPTR                      regCP_RB2_RPTR;
typedef union CP_RB2_RPTR_ADDR                 regCP_RB2_RPTR_ADDR;
typedef union CP_RB2_RPTR_ADDR_HI              regCP_RB2_RPTR_ADDR_HI;
typedef union CP_RB2_WPTR                      regCP_RB2_WPTR;
typedef union CP_RB_BASE                       regCP_RB_BASE;
typedef union CP_RB_CNTL__CI                   regCP_RB_CNTL__CI;
typedef union CP_RB_CNTL__VI                   regCP_RB_CNTL__VI;
typedef union CP_RB_CNTL__SI                   regCP_RB_CNTL__SI;
typedef union CP_RB_OFFSET                     regCP_RB_OFFSET;
typedef union CP_RB_RPTR                       regCP_RB_RPTR;
typedef union CP_RB_RPTR_ADDR                  regCP_RB_RPTR_ADDR;
typedef union CP_RB_RPTR_ADDR_HI               regCP_RB_RPTR_ADDR_HI;
typedef union CP_RB_RPTR_WR                    regCP_RB_RPTR_WR;
typedef union CP_RB_VMID                       regCP_RB_VMID;
typedef union CP_RB_WPTR                       regCP_RB_WPTR;
typedef union CP_RB_WPTR_DELAY                 regCP_RB_WPTR_DELAY;
typedef union CP_RB_WPTR_POLL_ADDR_HI__CI      regCP_RB_WPTR_POLL_ADDR_HI__CI;
typedef union CP_RB_WPTR_POLL_ADDR_HI__VI      regCP_RB_WPTR_POLL_ADDR_HI__VI;
typedef union CP_RB_WPTR_POLL_ADDR_HI__SI      regCP_RB_WPTR_POLL_ADDR_HI__SI;
typedef union CP_RB_WPTR_POLL_ADDR_LO__CI      regCP_RB_WPTR_POLL_ADDR_LO__CI;
typedef union CP_RB_WPTR_POLL_ADDR_LO__VI      regCP_RB_WPTR_POLL_ADDR_LO__VI;
typedef union CP_RB_WPTR_POLL_ADDR_LO__SI      regCP_RB_WPTR_POLL_ADDR_LO__SI;
typedef union CP_RB_WPTR_POLL_CNTL             regCP_RB_WPTR_POLL_CNTL;
typedef union CP_RING0_PRIORITY                regCP_RING0_PRIORITY;
typedef union CP_RING1_PRIORITY                regCP_RING1_PRIORITY;
typedef union CP_RING2_PRIORITY                regCP_RING2_PRIORITY;
typedef union CP_RINGID                        regCP_RINGID;
typedef union CP_RING_PRIORITY_CNTS            regCP_RING_PRIORITY_CNTS;
typedef union CP_ROQ1_THRESHOLDS               regCP_ROQ1_THRESHOLDS;
typedef union CP_ROQ2_AVAIL                    regCP_ROQ2_AVAIL;
typedef union CP_ROQ2_THRESHOLDS               regCP_ROQ2_THRESHOLDS;
typedef union CP_ROQ_AVAIL                     regCP_ROQ_AVAIL;
typedef union CP_ROQ_IB1_STAT                  regCP_ROQ_IB1_STAT;
typedef union CP_ROQ_IB2_STAT                  regCP_ROQ_IB2_STAT;
typedef union CP_ROQ_RB_STAT                   regCP_ROQ_RB_STAT;
typedef union CP_ROQ_THRESHOLDS__CI__VI        regCP_ROQ_THRESHOLDS__CI__VI;
typedef union CP_SCRATCH_DATA                  regCP_SCRATCH_DATA;
typedef union CP_SCRATCH_INDEX                 regCP_SCRATCH_INDEX;
typedef union CP_SC_PSINVOC_COUNT0_HI          regCP_SC_PSINVOC_COUNT0_HI;
typedef union CP_SC_PSINVOC_COUNT0_LO          regCP_SC_PSINVOC_COUNT0_LO;
typedef union CP_SC_PSINVOC_COUNT1_HI__CI__VI  regCP_SC_PSINVOC_COUNT1_HI__CI__VI;
typedef union CP_SC_PSINVOC_COUNT1_HI__SI      regCP_SC_PSINVOC_COUNT1_HI__SI;
typedef union CP_SC_PSINVOC_COUNT1_LO__CI__VI  regCP_SC_PSINVOC_COUNT1_LO__CI__VI;
typedef union CP_SC_PSINVOC_COUNT1_LO__SI      regCP_SC_PSINVOC_COUNT1_LO__SI;
typedef union CP_SEM_WAIT_TIMER                regCP_SEM_WAIT_TIMER;
typedef union CP_SIG_SEM_ADDR_HI               regCP_SIG_SEM_ADDR_HI;
typedef union CP_SIG_SEM_ADDR_LO               regCP_SIG_SEM_ADDR_LO;
typedef union CP_STALLED_STAT1__CI             regCP_STALLED_STAT1__CI;
typedef union CP_STALLED_STAT1__VI             regCP_STALLED_STAT1__VI;
typedef union CP_STALLED_STAT1__SI             regCP_STALLED_STAT1__SI;
typedef union CP_STALLED_STAT2                 regCP_STALLED_STAT2;
typedef union CP_STALLED_STAT3                 regCP_STALLED_STAT3;
typedef union CP_STAT__CI                      regCP_STAT__CI;
typedef union CP_STAT__VI                      regCP_STAT__VI;
typedef union CP_STAT__SI                      regCP_STAT__SI;
typedef union CP_STQ_AVAIL                     regCP_STQ_AVAIL;
typedef union CP_STQ_STAT                      regCP_STQ_STAT;
typedef union CP_STQ_THRESHOLDS                regCP_STQ_THRESHOLDS;
typedef union CP_STQ_WR_STAT__CI__VI           regCP_STQ_WR_STAT__CI__VI;
typedef union CP_STREAM_OUT_ADDR_HI__CI__VI    regCP_STREAM_OUT_ADDR_HI__CI__VI;
typedef union CP_STREAM_OUT_ADDR_HI__SI        regCP_STREAM_OUT_ADDR_HI__SI;
typedef union CP_STREAM_OUT_ADDR_LO            regCP_STREAM_OUT_ADDR_LO;
typedef union CP_STRMOUT_CNTL                  regCP_STRMOUT_CNTL;
typedef union CP_ST_BASE_HI                    regCP_ST_BASE_HI;
typedef union CP_ST_BASE_LO                    regCP_ST_BASE_LO;
typedef union CP_ST_BUFSZ                      regCP_ST_BUFSZ;
typedef union CP_VGT_CSINVOC_COUNT_HI          regCP_VGT_CSINVOC_COUNT_HI;
typedef union CP_VGT_CSINVOC_COUNT_LO          regCP_VGT_CSINVOC_COUNT_LO;
typedef union CP_VGT_DSINVOC_COUNT_HI          regCP_VGT_DSINVOC_COUNT_HI;
typedef union CP_VGT_DSINVOC_COUNT_LO          regCP_VGT_DSINVOC_COUNT_LO;
typedef union CP_VGT_GSINVOC_COUNT_HI          regCP_VGT_GSINVOC_COUNT_HI;
typedef union CP_VGT_GSINVOC_COUNT_LO          regCP_VGT_GSINVOC_COUNT_LO;
typedef union CP_VGT_GSPRIM_COUNT_HI           regCP_VGT_GSPRIM_COUNT_HI;
typedef union CP_VGT_GSPRIM_COUNT_LO           regCP_VGT_GSPRIM_COUNT_LO;
typedef union CP_VGT_HSINVOC_COUNT_HI          regCP_VGT_HSINVOC_COUNT_HI;
typedef union CP_VGT_HSINVOC_COUNT_LO          regCP_VGT_HSINVOC_COUNT_LO;
typedef union CP_VGT_IAPRIM_COUNT_HI           regCP_VGT_IAPRIM_COUNT_HI;
typedef union CP_VGT_IAPRIM_COUNT_LO           regCP_VGT_IAPRIM_COUNT_LO;
typedef union CP_VGT_IAVERT_COUNT_HI           regCP_VGT_IAVERT_COUNT_HI;
typedef union CP_VGT_IAVERT_COUNT_LO           regCP_VGT_IAVERT_COUNT_LO;
typedef union CP_VGT_VSINVOC_COUNT_HI          regCP_VGT_VSINVOC_COUNT_HI;
typedef union CP_VGT_VSINVOC_COUNT_LO          regCP_VGT_VSINVOC_COUNT_LO;
typedef union CP_VMID                          regCP_VMID;
typedef union CP_VMID_PREEMPT__CI              regCP_VMID_PREEMPT__CI;
typedef union CP_VMID_PREEMPT__VI              regCP_VMID_PREEMPT__VI;
typedef union CP_VMID_RESET__CI__VI            regCP_VMID_RESET__CI__VI;
typedef union CP_WAIT_REG_MEM_TIMEOUT          regCP_WAIT_REG_MEM_TIMEOUT;
typedef union CP_WAIT_SEM_ADDR_HI              regCP_WAIT_SEM_ADDR_HI;
typedef union CP_WAIT_SEM_ADDR_LO              regCP_WAIT_SEM_ADDR_LO;
typedef union CRT00__SI__VI                    regCRT00__SI__VI;
typedef union CRT01__SI__VI                    regCRT01__SI__VI;
typedef union CRT02__SI__VI                    regCRT02__SI__VI;
typedef union CRT03__SI__VI                    regCRT03__SI__VI;
typedef union CRT04__SI__VI                    regCRT04__SI__VI;
typedef union CRT05__SI__VI                    regCRT05__SI__VI;
typedef union CRT06__SI__VI                    regCRT06__SI__VI;
typedef union CRT07__SI__VI                    regCRT07__SI__VI;
typedef union CRT08__SI__VI                    regCRT08__SI__VI;
typedef union CRT09__SI__VI                    regCRT09__SI__VI;
typedef union CRT0A__SI__VI                    regCRT0A__SI__VI;
typedef union CRT0B__SI__VI                    regCRT0B__SI__VI;
typedef union CRT0C__SI__VI                    regCRT0C__SI__VI;
typedef union CRT0D__SI__VI                    regCRT0D__SI__VI;
typedef union CRT0E__SI__VI                    regCRT0E__SI__VI;
typedef union CRT0F__SI__VI                    regCRT0F__SI__VI;
typedef union CRT10__SI__VI                    regCRT10__SI__VI;
typedef union CRT11__SI__VI                    regCRT11__SI__VI;
typedef union CRT12__SI__VI                    regCRT12__SI__VI;
typedef union CRT13__SI__VI                    regCRT13__SI__VI;
typedef union CRT14__SI__VI                    regCRT14__SI__VI;
typedef union CRT15__SI__VI                    regCRT15__SI__VI;
typedef union CRT16__SI__VI                    regCRT16__SI__VI;
typedef union CRT17__SI__VI                    regCRT17__SI__VI;
typedef union CRT18__SI__VI                    regCRT18__SI__VI;
typedef union CRT1E__SI__VI                    regCRT1E__SI__VI;
typedef union CRT1F__SI__VI                    regCRT1F__SI__VI;
typedef union CRT22__SI__VI                    regCRT22__SI__VI;
typedef union CRTC0_PIXEL_RATE_CNTL__SI        regCRTC0_PIXEL_RATE_CNTL__SI;
typedef union CRTC0_PIXEL_RATE_CNTL__VI        regCRTC0_PIXEL_RATE_CNTL__VI;
typedef union CRTC1_PIXEL_RATE_CNTL__SI        regCRTC1_PIXEL_RATE_CNTL__SI;
typedef union CRTC1_PIXEL_RATE_CNTL__VI        regCRTC1_PIXEL_RATE_CNTL__VI;
typedef union CRTC2_PIXEL_RATE_CNTL__SI        regCRTC2_PIXEL_RATE_CNTL__SI;
typedef union CRTC2_PIXEL_RATE_CNTL__VI        regCRTC2_PIXEL_RATE_CNTL__VI;
typedef union CRTC3_PIXEL_RATE_CNTL__SI        regCRTC3_PIXEL_RATE_CNTL__SI;
typedef union CRTC3_PIXEL_RATE_CNTL__VI        regCRTC3_PIXEL_RATE_CNTL__VI;
typedef union CRTC4_PIXEL_RATE_CNTL__SI        regCRTC4_PIXEL_RATE_CNTL__SI;
typedef union CRTC4_PIXEL_RATE_CNTL__VI        regCRTC4_PIXEL_RATE_CNTL__VI;
typedef union CRTC5_PIXEL_RATE_CNTL__SI        regCRTC5_PIXEL_RATE_CNTL__SI;
typedef union CRTC5_PIXEL_RATE_CNTL__VI        regCRTC5_PIXEL_RATE_CNTL__VI;
typedef union CRTC8_DATA__SI__VI               regCRTC8_DATA__SI__VI;
typedef union CRTC8_IDX__SI__VI                regCRTC8_IDX__SI__VI;
typedef union CRTC_ALLOW_STOP_OFF_V_CNT__SI__VI regCRTC_ALLOW_STOP_OFF_V_CNT__SI__VI;
typedef union CRTC_BLACK_COLOR__SI__VI         regCRTC_BLACK_COLOR__SI__VI;
typedef union CRTC_BLANK_CONTROL               regCRTC_BLANK_CONTROL;
typedef union CRTC_BLANK_DATA_COLOR__SI__VI    regCRTC_BLANK_DATA_COLOR__SI__VI;
typedef union CRTC_CONTROL__SI                 regCRTC_CONTROL__SI;
typedef union CRTC_CONTROL__VI                 regCRTC_CONTROL__VI;
typedef union CRTC_COUNT_CONTROL__SI__VI       regCRTC_COUNT_CONTROL__SI__VI;
typedef union CRTC_COUNT_RESET__SI__VI         regCRTC_COUNT_RESET__SI__VI;
typedef union CRTC_DOUBLE_BUFFER_CONTROL__SI__VI regCRTC_DOUBLE_BUFFER_CONTROL__SI__VI;
typedef union CRTC_DTMTEST_CNTL__SI__VI        regCRTC_DTMTEST_CNTL__SI__VI;
typedef union CRTC_DTMTEST_STATUS_POSITION__SI__VI regCRTC_DTMTEST_STATUS_POSITION__SI__VI;
typedef union CRTC_FLOW_CONTROL__SI__VI        regCRTC_FLOW_CONTROL__SI__VI;
typedef union CRTC_FORCE_COUNT_NOW_CNTL__SI__VI regCRTC_FORCE_COUNT_NOW_CNTL__SI__VI;
typedef union CRTC_H_BLANK_START_END__SI__VI   regCRTC_H_BLANK_START_END__SI__VI;
typedef union CRTC_H_SYNC_A_CNTL__SI__VI       regCRTC_H_SYNC_A_CNTL__SI__VI;
typedef union CRTC_H_SYNC_A__SI__VI            regCRTC_H_SYNC_A__SI__VI;
typedef union CRTC_H_SYNC_B_CNTL__SI__VI       regCRTC_H_SYNC_B_CNTL__SI__VI;
typedef union CRTC_H_SYNC_B__SI__VI            regCRTC_H_SYNC_B__SI__VI;
typedef union CRTC_H_TOTAL__SI__VI             regCRTC_H_TOTAL__SI__VI;
typedef union CRTC_INTERLACE_CONTROL__SI__VI   regCRTC_INTERLACE_CONTROL__SI__VI;
typedef union CRTC_INTERLACE_STATUS__SI__VI    regCRTC_INTERLACE_STATUS__SI__VI;
typedef union CRTC_INTERRUPT_CONTROL__SI__VI   regCRTC_INTERRUPT_CONTROL__SI__VI;
typedef union CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI regCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SI__VI;
typedef union CRTC_MASTER_EN__SI__VI           regCRTC_MASTER_EN__SI__VI;
typedef union CRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI regCRTC_MVP_INBAND_CNTL_INSERT_TIMER__SI__VI;
typedef union CRTC_MVP_INBAND_CNTL_INSERT__SI__VI regCRTC_MVP_INBAND_CNTL_INSERT__SI__VI;
typedef union CRTC_MVP_STATUS__SI__VI          regCRTC_MVP_STATUS__SI__VI;
typedef union CRTC_NOM_VERT_POSITION__SI__VI   regCRTC_NOM_VERT_POSITION__SI__VI;
typedef union CRTC_OVERSCAN_COLOR__SI__VI      regCRTC_OVERSCAN_COLOR__SI__VI;
typedef union CRTC_PIXEL_DATA_READBACK__SI     regCRTC_PIXEL_DATA_READBACK__SI;
typedef union CRTC_SNAPSHOT_CONTROL__SI__VI    regCRTC_SNAPSHOT_CONTROL__SI__VI;
typedef union CRTC_SNAPSHOT_FRAME__SI__VI      regCRTC_SNAPSHOT_FRAME__SI__VI;
typedef union CRTC_SNAPSHOT_POSITION__SI__VI   regCRTC_SNAPSHOT_POSITION__SI__VI;
typedef union CRTC_SNAPSHOT_STATUS__SI__VI     regCRTC_SNAPSHOT_STATUS__SI__VI;
typedef union CRTC_START_LINE_CONTROL__SI__VI  regCRTC_START_LINE_CONTROL__SI__VI;
typedef union CRTC_STATUS                      regCRTC_STATUS;
typedef union CRTC_STATUS_FRAME_COUNT__SI__VI  regCRTC_STATUS_FRAME_COUNT__SI__VI;
typedef union CRTC_STATUS_HV_COUNT__SI__VI     regCRTC_STATUS_HV_COUNT__SI__VI;
typedef union CRTC_STATUS_POSITION             regCRTC_STATUS_POSITION;
typedef union CRTC_STATUS_VF_COUNT__SI__VI     regCRTC_STATUS_VF_COUNT__SI__VI;
typedef union CRTC_STEREO_CONTROL__SI          regCRTC_STEREO_CONTROL__SI;
typedef union CRTC_STEREO_CONTROL__VI          regCRTC_STEREO_CONTROL__VI;
typedef union CRTC_STEREO_FORCE_NEXT_EYE__SI__VI regCRTC_STEREO_FORCE_NEXT_EYE__SI__VI;
typedef union CRTC_STEREO_STATUS__SI__VI       regCRTC_STEREO_STATUS__SI__VI;
typedef union CRTC_TEST_DEBUG_DATA__SI__VI     regCRTC_TEST_DEBUG_DATA__SI__VI;
typedef union CRTC_TEST_DEBUG_INDEX__SI__VI    regCRTC_TEST_DEBUG_INDEX__SI__VI;
typedef union CRTC_TEST_PATTERN_COLOR__SI__VI  regCRTC_TEST_PATTERN_COLOR__SI__VI;
typedef union CRTC_TEST_PATTERN_CONTROL__SI__VI regCRTC_TEST_PATTERN_CONTROL__SI__VI;
typedef union CRTC_TEST_PATTERN_PARAMETERS__SI__VI regCRTC_TEST_PATTERN_PARAMETERS__SI__VI;
typedef union CRTC_TRIGA_CNTL__SI              regCRTC_TRIGA_CNTL__SI;
typedef union CRTC_TRIGA_CNTL__VI              regCRTC_TRIGA_CNTL__VI;
typedef union CRTC_TRIGA_MANUAL_TRIG__SI__VI   regCRTC_TRIGA_MANUAL_TRIG__SI__VI;
typedef union CRTC_TRIGB_CNTL__SI              regCRTC_TRIGB_CNTL__SI;
typedef union CRTC_TRIGB_CNTL__VI              regCRTC_TRIGB_CNTL__VI;
typedef union CRTC_TRIGB_MANUAL_TRIG__SI__VI   regCRTC_TRIGB_MANUAL_TRIG__SI__VI;
typedef union CRTC_UPDATE_LOCK__SI__VI         regCRTC_UPDATE_LOCK__SI__VI;
typedef union CRTC_VBI_END__SI__VI             regCRTC_VBI_END__SI__VI;
typedef union CRTC_VERT_SYNC_CONTROL__SI__VI   regCRTC_VERT_SYNC_CONTROL__SI__VI;
typedef union CRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI regCRTC_VGA_PARAMETER_CAPTURE_MODE__SI__VI;
typedef union CRTC_VSYNC_NOM_INT_STATUS__SI__VI regCRTC_VSYNC_NOM_INT_STATUS__SI__VI;
typedef union CRTC_V_BLANK_START_END__SI__VI   regCRTC_V_BLANK_START_END__SI__VI;
typedef union CRTC_V_SYNC_A_CNTL__SI__VI       regCRTC_V_SYNC_A_CNTL__SI__VI;
typedef union CRTC_V_SYNC_A__SI__VI            regCRTC_V_SYNC_A__SI__VI;
typedef union CRTC_V_SYNC_B_CNTL__SI__VI       regCRTC_V_SYNC_B_CNTL__SI__VI;
typedef union CRTC_V_SYNC_B__SI__VI            regCRTC_V_SYNC_B__SI__VI;
typedef union CRTC_V_TOTAL_CONTROL__SI__VI     regCRTC_V_TOTAL_CONTROL__SI__VI;
typedef union CRTC_V_TOTAL_INT_STATUS__SI__VI  regCRTC_V_TOTAL_INT_STATUS__SI__VI;
typedef union CRTC_V_TOTAL_MAX__SI__VI         regCRTC_V_TOTAL_MAX__SI__VI;
typedef union CRTC_V_TOTAL_MIN__SI__VI         regCRTC_V_TOTAL_MIN__SI__VI;
typedef union CRTC_V_TOTAL__SI__VI             regCRTC_V_TOTAL__SI__VI;
typedef union CRTC_V_UPDATE_INT_STATUS__SI__VI regCRTC_V_UPDATE_INT_STATUS__SI__VI;
typedef union CSPRIV_CONNECT__CI__VI           regCSPRIV_CONNECT__CI__VI;
typedef union CSPRIV_THREAD_TRACE_EVENT__CI__VI regCSPRIV_THREAD_TRACE_EVENT__CI__VI;
typedef union CSPRIV_THREAD_TRACE_TG0__CI__VI  regCSPRIV_THREAD_TRACE_TG0__CI__VI;
typedef union CSPRIV_THREAD_TRACE_TG1__CI__VI  regCSPRIV_THREAD_TRACE_TG1__CI__VI;
typedef union CSPRIV_THREAD_TRACE_TG2__CI__VI  regCSPRIV_THREAD_TRACE_TG2__CI__VI;
typedef union CSPRIV_THREAD_TRACE_TG3__CI__VI  regCSPRIV_THREAD_TRACE_TG3__CI__VI;
typedef union CS_COPY_STATE                    regCS_COPY_STATE;
typedef union CUR_COLOR1__SI__VI               regCUR_COLOR1__SI__VI;
typedef union CUR_COLOR2__SI__VI               regCUR_COLOR2__SI__VI;
typedef union CUR_CONTROL__SI__VI              regCUR_CONTROL__SI__VI;
typedef union CUR_HOT_SPOT__SI__VI             regCUR_HOT_SPOT__SI__VI;
typedef union CUR_POSITION__SI__VI             regCUR_POSITION__SI__VI;
typedef union CUR_SIZE__SI__VI                 regCUR_SIZE__SI__VI;
typedef union CUR_SURFACE_ADDRESS_HIGH__SI__VI regCUR_SURFACE_ADDRESS_HIGH__SI__VI;
typedef union CUR_SURFACE_ADDRESS__SI__VI      regCUR_SURFACE_ADDRESS__SI__VI;
typedef union CUR_UPDATE__SI__VI               regCUR_UPDATE__SI__VI;
typedef union D1VGA_CONTROL__SI__VI            regD1VGA_CONTROL__SI__VI;
typedef union D2VGA_CONTROL__SI__VI            regD2VGA_CONTROL__SI__VI;
typedef union D3VGA_CONTROL__SI__VI            regD3VGA_CONTROL__SI__VI;
typedef union D4VGA_CONTROL__SI__VI            regD4VGA_CONTROL__SI__VI;
typedef union D5VGA_CONTROL__SI__VI            regD5VGA_CONTROL__SI__VI;
typedef union D6VGA_CONTROL__SI__VI            regD6VGA_CONTROL__SI__VI;
typedef union DAC_AUTODETECT_CONTROL2__SI__VI  regDAC_AUTODETECT_CONTROL2__SI__VI;
typedef union DAC_AUTODETECT_CONTROL3__SI__VI  regDAC_AUTODETECT_CONTROL3__SI__VI;
typedef union DAC_AUTODETECT_CONTROL__SI__VI   regDAC_AUTODETECT_CONTROL__SI__VI;
typedef union DAC_AUTODETECT_INT_CONTROL__SI__VI regDAC_AUTODETECT_INT_CONTROL__SI__VI;
typedef union DAC_AUTODETECT_STATUS__SI__VI    regDAC_AUTODETECT_STATUS__SI__VI;
typedef union DAC_COMPARATOR_ENABLE__SI__VI    regDAC_COMPARATOR_ENABLE__SI__VI;
typedef union DAC_COMPARATOR_OUTPUT__SI__VI    regDAC_COMPARATOR_OUTPUT__SI__VI;
typedef union DAC_CONTROL__SI__VI              regDAC_CONTROL__SI__VI;
typedef union DAC_CRC_CONTROL__SI              regDAC_CRC_CONTROL__SI;
typedef union DAC_CRC_CONTROL__VI              regDAC_CRC_CONTROL__VI;
typedef union DAC_CRC_EN__SI__VI               regDAC_CRC_EN__SI__VI;
typedef union DAC_CRC_SIG_CONTROL_MASK__SI__VI regDAC_CRC_SIG_CONTROL_MASK__SI__VI;
typedef union DAC_CRC_SIG_CONTROL__SI__VI      regDAC_CRC_SIG_CONTROL__SI__VI;
typedef union DAC_CRC_SIG_RGB_MASK__SI__VI     regDAC_CRC_SIG_RGB_MASK__SI__VI;
typedef union DAC_CRC_SIG_RGB__SI__VI          regDAC_CRC_SIG_RGB__SI__VI;
typedef union DAC_DATA__SI__VI                 regDAC_DATA__SI__VI;
typedef union DAC_DFT_CONFIG__SI__VI           regDAC_DFT_CONFIG__SI__VI;
typedef union DAC_ENABLE__SI__VI               regDAC_ENABLE__SI__VI;
typedef union DAC_FORCE_DATA__SI__VI           regDAC_FORCE_DATA__SI__VI;
typedef union DAC_FORCE_OUTPUT_CNTL__SI        regDAC_FORCE_OUTPUT_CNTL__SI;
typedef union DAC_FORCE_OUTPUT_CNTL__VI        regDAC_FORCE_OUTPUT_CNTL__VI;
typedef union DAC_MACRO_CNTL__SI               regDAC_MACRO_CNTL__SI;
typedef union DAC_MASK__SI__VI                 regDAC_MASK__SI__VI;
typedef union DAC_POWERDOWN__SI__VI            regDAC_POWERDOWN__SI__VI;
typedef union DAC_PWR_CNTL__SI__VI             regDAC_PWR_CNTL__SI__VI;
typedef union DAC_R_INDEX__SI__VI              regDAC_R_INDEX__SI__VI;
typedef union DAC_SOURCE_SELECT__SI__VI        regDAC_SOURCE_SELECT__SI__VI;
typedef union DAC_STEREOSYNC_SELECT__SI__VI    regDAC_STEREOSYNC_SELECT__SI__VI;
typedef union DAC_SYNC_TRISTATE_CONTROL__SI__VI regDAC_SYNC_TRISTATE_CONTROL__SI__VI;
typedef union DAC_W_INDEX__SI__VI              regDAC_W_INDEX__SI__VI;
typedef union DBG_BYPASS_SRBM_ACCESS__CI       regDBG_BYPASS_SRBM_ACCESS__CI;
typedef union DB_ALPHA_TO_MASK                 regDB_ALPHA_TO_MASK;
typedef union DB_CGTT_CLK_CTRL_0               regDB_CGTT_CLK_CTRL_0;
typedef union DB_COUNT_CONTROL                 regDB_COUNT_CONTROL;
typedef union DB_CREDIT_LIMIT                  regDB_CREDIT_LIMIT;
typedef union DB_DEBUG                         regDB_DEBUG;
typedef union DB_DEBUG2__CI__VI                regDB_DEBUG2__CI__VI;
typedef union DB_DEBUG2__SI                    regDB_DEBUG2__SI;
typedef union DB_DEBUG3__CI                    regDB_DEBUG3__CI;
typedef union DB_DEBUG3__VI                    regDB_DEBUG3__VI;
typedef union DB_DEBUG3__SI                    regDB_DEBUG3__SI;
typedef union DB_DEBUG4__CI                    regDB_DEBUG4__CI;
typedef union DB_DEBUG4__VI                    regDB_DEBUG4__VI;
typedef union DB_DEBUG4__SI                    regDB_DEBUG4__SI;
typedef union DB_DEPTH_BOUNDS_MAX              regDB_DEPTH_BOUNDS_MAX;
typedef union DB_DEPTH_BOUNDS_MIN              regDB_DEPTH_BOUNDS_MIN;
typedef union DB_DEPTH_CLEAR                   regDB_DEPTH_CLEAR;
typedef union DB_DEPTH_CONTROL                 regDB_DEPTH_CONTROL;
typedef union DB_DEPTH_INFO                    regDB_DEPTH_INFO;
typedef union DB_DEPTH_SIZE                    regDB_DEPTH_SIZE;
typedef union DB_DEPTH_SLICE                   regDB_DEPTH_SLICE;
typedef union DB_DEPTH_VIEW                    regDB_DEPTH_VIEW;
typedef union DB_EQAA                          regDB_EQAA;
typedef union DB_FIFO_DEPTH1                   regDB_FIFO_DEPTH1;
typedef union DB_FIFO_DEPTH2                   regDB_FIFO_DEPTH2;
typedef union DB_FREE_CACHELINES               regDB_FREE_CACHELINES;
typedef union DB_HTILE_DATA_BASE               regDB_HTILE_DATA_BASE;
typedef union DB_HTILE_SURFACE                 regDB_HTILE_SURFACE;
typedef union DB_OCCLUSION_COUNT0_HI__CI__VI   regDB_OCCLUSION_COUNT0_HI__CI__VI;
typedef union DB_OCCLUSION_COUNT0_LOW__CI__VI  regDB_OCCLUSION_COUNT0_LOW__CI__VI;
typedef union DB_OCCLUSION_COUNT1_HI__CI__VI   regDB_OCCLUSION_COUNT1_HI__CI__VI;
typedef union DB_OCCLUSION_COUNT1_LOW__CI__VI  regDB_OCCLUSION_COUNT1_LOW__CI__VI;
typedef union DB_OCCLUSION_COUNT2_HI__CI__VI   regDB_OCCLUSION_COUNT2_HI__CI__VI;
typedef union DB_OCCLUSION_COUNT2_LOW__CI__VI  regDB_OCCLUSION_COUNT2_LOW__CI__VI;
typedef union DB_OCCLUSION_COUNT3_HI__CI__VI   regDB_OCCLUSION_COUNT3_HI__CI__VI;
typedef union DB_OCCLUSION_COUNT3_LOW__CI__VI  regDB_OCCLUSION_COUNT3_LOW__CI__VI;
typedef union DB_PERFCOUNTER0_HI               regDB_PERFCOUNTER0_HI;
typedef union DB_PERFCOUNTER0_LO               regDB_PERFCOUNTER0_LO;
typedef union DB_PERFCOUNTER0_SELECT           regDB_PERFCOUNTER0_SELECT;
typedef union DB_PERFCOUNTER0_SELECT1__CI__VI  regDB_PERFCOUNTER0_SELECT1__CI__VI;
typedef union DB_PERFCOUNTER1_HI               regDB_PERFCOUNTER1_HI;
typedef union DB_PERFCOUNTER1_LO               regDB_PERFCOUNTER1_LO;
typedef union DB_PERFCOUNTER1_SELECT           regDB_PERFCOUNTER1_SELECT;
typedef union DB_PERFCOUNTER1_SELECT1__CI__VI  regDB_PERFCOUNTER1_SELECT1__CI__VI;
typedef union DB_PERFCOUNTER2_HI               regDB_PERFCOUNTER2_HI;
typedef union DB_PERFCOUNTER2_LO               regDB_PERFCOUNTER2_LO;
typedef union DB_PERFCOUNTER2_SELECT           regDB_PERFCOUNTER2_SELECT;
typedef union DB_PERFCOUNTER3_HI               regDB_PERFCOUNTER3_HI;
typedef union DB_PERFCOUNTER3_LO               regDB_PERFCOUNTER3_LO;
typedef union DB_PERFCOUNTER3_SELECT           regDB_PERFCOUNTER3_SELECT;
typedef union DB_PRELOAD_CONTROL               regDB_PRELOAD_CONTROL;
typedef union DB_READ_DEBUG_0                  regDB_READ_DEBUG_0;
typedef union DB_READ_DEBUG_1                  regDB_READ_DEBUG_1;
typedef union DB_READ_DEBUG_2                  regDB_READ_DEBUG_2;
typedef union DB_READ_DEBUG_3                  regDB_READ_DEBUG_3;
typedef union DB_READ_DEBUG_4                  regDB_READ_DEBUG_4;
typedef union DB_READ_DEBUG_5                  regDB_READ_DEBUG_5;
typedef union DB_READ_DEBUG_6                  regDB_READ_DEBUG_6;
typedef union DB_READ_DEBUG_7                  regDB_READ_DEBUG_7;
typedef union DB_READ_DEBUG_8                  regDB_READ_DEBUG_8;
typedef union DB_READ_DEBUG_9                  regDB_READ_DEBUG_9;
typedef union DB_READ_DEBUG_A                  regDB_READ_DEBUG_A;
typedef union DB_READ_DEBUG_B                  regDB_READ_DEBUG_B;
typedef union DB_READ_DEBUG_C                  regDB_READ_DEBUG_C;
typedef union DB_READ_DEBUG_D                  regDB_READ_DEBUG_D;
typedef union DB_READ_DEBUG_E                  regDB_READ_DEBUG_E;
typedef union DB_READ_DEBUG_F                  regDB_READ_DEBUG_F;
typedef union DB_RENDER_CONTROL                regDB_RENDER_CONTROL;
typedef union DB_RENDER_OVERRIDE               regDB_RENDER_OVERRIDE;
typedef union DB_RENDER_OVERRIDE2              regDB_RENDER_OVERRIDE2;
typedef union DB_RING_CONTROL__CI__VI          regDB_RING_CONTROL__CI__VI;
typedef union DB_SHADER_CONTROL                regDB_SHADER_CONTROL;
typedef union DB_SRESULTS_COMPARE_STATE0       regDB_SRESULTS_COMPARE_STATE0;
typedef union DB_SRESULTS_COMPARE_STATE1       regDB_SRESULTS_COMPARE_STATE1;
typedef union DB_STENCILREFMASK                regDB_STENCILREFMASK;
typedef union DB_STENCILREFMASK_BF             regDB_STENCILREFMASK_BF;
typedef union DB_STENCIL_CLEAR                 regDB_STENCIL_CLEAR;
typedef union DB_STENCIL_CONTROL               regDB_STENCIL_CONTROL;
typedef union DB_STENCIL_INFO                  regDB_STENCIL_INFO;
typedef union DB_STENCIL_READ_BASE             regDB_STENCIL_READ_BASE;
typedef union DB_STENCIL_WRITE_BASE            regDB_STENCIL_WRITE_BASE;
typedef union DB_SUBTILE_CONTROL               regDB_SUBTILE_CONTROL;
typedef union DB_WATERMARKS                    regDB_WATERMARKS;
typedef union DB_ZPASS_COUNT_HI                regDB_ZPASS_COUNT_HI;
typedef union DB_ZPASS_COUNT_LOW               regDB_ZPASS_COUNT_LOW;
typedef union DB_Z_INFO                        regDB_Z_INFO;
typedef union DB_Z_READ_BASE                   regDB_Z_READ_BASE;
typedef union DB_Z_WRITE_BASE                  regDB_Z_WRITE_BASE;
typedef union DCCG_AUDIO_DTO0_MODULE__SI       regDCCG_AUDIO_DTO0_MODULE__SI;
typedef union DCCG_AUDIO_DTO0_MODULE__VI       regDCCG_AUDIO_DTO0_MODULE__VI;
typedef union DCCG_AUDIO_DTO0_PHASE__SI        regDCCG_AUDIO_DTO0_PHASE__SI;
typedef union DCCG_AUDIO_DTO0_PHASE__VI        regDCCG_AUDIO_DTO0_PHASE__VI;
typedef union DCCG_GATE_DISABLE_CNTL__SI       regDCCG_GATE_DISABLE_CNTL__SI;
typedef union DCCG_GATE_DISABLE_CNTL__VI       regDCCG_GATE_DISABLE_CNTL__VI;
typedef union DCCG_TEST_CLK_SEL__SI            regDCCG_TEST_CLK_SEL__SI;
typedef union DCCG_TEST_CLK_SEL__VI            regDCCG_TEST_CLK_SEL__VI;
typedef union DCCG_TEST_DEBUG_DATA__SI__VI     regDCCG_TEST_DEBUG_DATA__SI__VI;
typedef union DCCG_TEST_DEBUG_INDEX__SI__VI    regDCCG_TEST_DEBUG_INDEX__SI__VI;
typedef union DCCG_VPCLK_CNTL__SI              regDCCG_VPCLK_CNTL__SI;
typedef union DCDEBUG_BUS_CLK1_SEL__SI__VI     regDCDEBUG_BUS_CLK1_SEL__SI__VI;
typedef union DCDEBUG_BUS_CLK2_SEL__SI__VI     regDCDEBUG_BUS_CLK2_SEL__SI__VI;
typedef union DCDEBUG_BUS_CLK3_SEL__SI__VI     regDCDEBUG_BUS_CLK3_SEL__SI__VI;
typedef union DCDEBUG_BUS_CLK4_SEL__SI__VI     regDCDEBUG_BUS_CLK4_SEL__SI__VI;
typedef union DCDEBUG_OUT_CNTL__SI             regDCDEBUG_OUT_CNTL__SI;
typedef union DCDEBUG_OUT_CNTL__VI             regDCDEBUG_OUT_CNTL__VI;
typedef union DCDEBUG_OUT_PIN_OVERRIDE__SI     regDCDEBUG_OUT_PIN_OVERRIDE__SI;
typedef union DCDEBUG_OUT_PIN_OVERRIDE__VI     regDCDEBUG_OUT_PIN_OVERRIDE__VI;
typedef union DCIO_DEBUG1__SI                  regDCIO_DEBUG1__SI;
typedef union DCIO_DEBUG1__VI                  regDCIO_DEBUG1__VI;
typedef union DCIO_DEBUG2__SI__VI              regDCIO_DEBUG2__SI__VI;
typedef union DCIO_DEBUG3__SI__VI              regDCIO_DEBUG3__SI__VI;
typedef union DCIO_DEBUG4__SI__VI              regDCIO_DEBUG4__SI__VI;
typedef union DCIO_DEBUG5__SI__VI              regDCIO_DEBUG5__SI__VI;
typedef union DCIO_DEBUG6__SI__VI              regDCIO_DEBUG6__SI__VI;
typedef union DCIO_DEBUG7__SI__VI              regDCIO_DEBUG7__SI__VI;
typedef union DCIO_DEBUG__SI__VI               regDCIO_DEBUG__SI__VI;
typedef union DCIO_IMPCAL_CNTL_AB__SI          regDCIO_IMPCAL_CNTL_AB__SI;
typedef union DCIO_IMPCAL_CNTL_CD__SI__VI      regDCIO_IMPCAL_CNTL_CD__SI__VI;
typedef union DCIO_IMPCAL_CNTL_EF__SI__VI      regDCIO_IMPCAL_CNTL_EF__SI__VI;
typedef union DCI_TEST_DEBUG_DATA__SI__VI      regDCI_TEST_DEBUG_DATA__SI__VI;
typedef union DCI_TEST_DEBUG_INDEX__SI__VI     regDCI_TEST_DEBUG_INDEX__SI__VI;
typedef union DCP_CRC_CONTROL__SI__VI          regDCP_CRC_CONTROL__SI__VI;
typedef union DCP_CRC_CURRENT__SI__VI          regDCP_CRC_CURRENT__SI__VI;
typedef union DCP_CRC_LAST__SI__VI             regDCP_CRC_LAST__SI__VI;
typedef union DCP_CRC_MASK__SI__VI             regDCP_CRC_MASK__SI__VI;
typedef union DCP_DEBUG__SI__VI                regDCP_DEBUG__SI__VI;
typedef union DCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI regDCP_LB_DATA_GAP_BETWEEN_CHUNK__SI__VI;
typedef union DCP_TEST_DEBUG_DATA__SI__VI      regDCP_TEST_DEBUG_DATA__SI__VI;
typedef union DCP_TEST_DEBUG_INDEX__SI__VI     regDCP_TEST_DEBUG_INDEX__SI__VI;
typedef union DC_ABM1_ACE_CNTL_MISC__SI__VI    regDC_ABM1_ACE_CNTL_MISC__SI__VI;
typedef union DC_ABM1_ACE_OFFSET_SLOPE_0__SI__VI regDC_ABM1_ACE_OFFSET_SLOPE_0__SI__VI;
typedef union DC_ABM1_ACE_OFFSET_SLOPE_1__SI__VI regDC_ABM1_ACE_OFFSET_SLOPE_1__SI__VI;
typedef union DC_ABM1_ACE_OFFSET_SLOPE_2__SI__VI regDC_ABM1_ACE_OFFSET_SLOPE_2__SI__VI;
typedef union DC_ABM1_ACE_OFFSET_SLOPE_3__SI__VI regDC_ABM1_ACE_OFFSET_SLOPE_3__SI__VI;
typedef union DC_ABM1_ACE_OFFSET_SLOPE_4__SI__VI regDC_ABM1_ACE_OFFSET_SLOPE_4__SI__VI;
typedef union DC_ABM1_ACE_THRES_12__SI__VI     regDC_ABM1_ACE_THRES_12__SI__VI;
typedef union DC_ABM1_ACE_THRES_34__SI__VI     regDC_ABM1_ACE_THRES_34__SI__VI;
typedef union DC_ABM1_BL_MASTER_LOCK__SI__VI   regDC_ABM1_BL_MASTER_LOCK__SI__VI;
typedef union DC_ABM1_CNTL__SI__VI             regDC_ABM1_CNTL__SI__VI;
typedef union DC_ABM1_DEBUG_MISC__SI__VI       regDC_ABM1_DEBUG_MISC__SI__VI;
typedef union DC_ABM1_HGLS_REG_READ_PROGRESS__SI__VI regDC_ABM1_HGLS_REG_READ_PROGRESS__SI__VI;
typedef union DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI__VI regDC_ABM1_HG_BIN_17_24_SHIFT_INDEX__SI__VI;
typedef union DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI__VI regDC_ABM1_HG_BIN_1_32_SHIFT_FLAG__SI__VI;
typedef union DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI__VI regDC_ABM1_HG_BIN_1_8_SHIFT_INDEX__SI__VI;
typedef union DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI__VI regDC_ABM1_HG_BIN_25_32_SHIFT_INDEX__SI__VI;
typedef union DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI__VI regDC_ABM1_HG_BIN_9_16_SHIFT_INDEX__SI__VI;
typedef union DC_ABM1_HG_MISC_CTRL__SI         regDC_ABM1_HG_MISC_CTRL__SI;
typedef union DC_ABM1_HG_MISC_CTRL__VI         regDC_ABM1_HG_MISC_CTRL__VI;
typedef union DC_ABM1_HG_RESULT_10__SI__VI     regDC_ABM1_HG_RESULT_10__SI__VI;
typedef union DC_ABM1_HG_RESULT_11__SI__VI     regDC_ABM1_HG_RESULT_11__SI__VI;
typedef union DC_ABM1_HG_RESULT_12__SI__VI     regDC_ABM1_HG_RESULT_12__SI__VI;
typedef union DC_ABM1_HG_RESULT_13__SI__VI     regDC_ABM1_HG_RESULT_13__SI__VI;
typedef union DC_ABM1_HG_RESULT_14__SI__VI     regDC_ABM1_HG_RESULT_14__SI__VI;
typedef union DC_ABM1_HG_RESULT_15__SI__VI     regDC_ABM1_HG_RESULT_15__SI__VI;
typedef union DC_ABM1_HG_RESULT_16__SI__VI     regDC_ABM1_HG_RESULT_16__SI__VI;
typedef union DC_ABM1_HG_RESULT_17__SI__VI     regDC_ABM1_HG_RESULT_17__SI__VI;
typedef union DC_ABM1_HG_RESULT_18__SI__VI     regDC_ABM1_HG_RESULT_18__SI__VI;
typedef union DC_ABM1_HG_RESULT_19__SI__VI     regDC_ABM1_HG_RESULT_19__SI__VI;
typedef union DC_ABM1_HG_RESULT_1__SI__VI      regDC_ABM1_HG_RESULT_1__SI__VI;
typedef union DC_ABM1_HG_RESULT_20__SI__VI     regDC_ABM1_HG_RESULT_20__SI__VI;
typedef union DC_ABM1_HG_RESULT_21__SI__VI     regDC_ABM1_HG_RESULT_21__SI__VI;
typedef union DC_ABM1_HG_RESULT_22__SI__VI     regDC_ABM1_HG_RESULT_22__SI__VI;
typedef union DC_ABM1_HG_RESULT_23__SI__VI     regDC_ABM1_HG_RESULT_23__SI__VI;
typedef union DC_ABM1_HG_RESULT_24__SI__VI     regDC_ABM1_HG_RESULT_24__SI__VI;
typedef union DC_ABM1_HG_RESULT_2__SI__VI      regDC_ABM1_HG_RESULT_2__SI__VI;
typedef union DC_ABM1_HG_RESULT_3__SI__VI      regDC_ABM1_HG_RESULT_3__SI__VI;
typedef union DC_ABM1_HG_RESULT_4__SI__VI      regDC_ABM1_HG_RESULT_4__SI__VI;
typedef union DC_ABM1_HG_RESULT_5__SI__VI      regDC_ABM1_HG_RESULT_5__SI__VI;
typedef union DC_ABM1_HG_RESULT_6__SI__VI      regDC_ABM1_HG_RESULT_6__SI__VI;
typedef union DC_ABM1_HG_RESULT_7__SI__VI      regDC_ABM1_HG_RESULT_7__SI__VI;
typedef union DC_ABM1_HG_RESULT_8__SI__VI      regDC_ABM1_HG_RESULT_8__SI__VI;
typedef union DC_ABM1_HG_RESULT_9__SI__VI      regDC_ABM1_HG_RESULT_9__SI__VI;
typedef union DC_ABM1_HG_SAMPLE_RATE__SI__VI   regDC_ABM1_HG_SAMPLE_RATE__SI__VI;
typedef union DC_ABM1_IPCSC_COEFF_SEL__SI__VI  regDC_ABM1_IPCSC_COEFF_SEL__SI__VI;
typedef union DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI__VI regDC_ABM1_LS_FILTERED_MIN_MAX_LUMA__SI__VI;
typedef union DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI__VI regDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__SI__VI;
typedef union DC_ABM1_LS_MIN_MAX_LUMA__SI__VI  regDC_ABM1_LS_MIN_MAX_LUMA__SI__VI;
typedef union DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI__VI regDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__SI__VI;
typedef union DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI__VI regDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__SI__VI;
typedef union DC_ABM1_LS_OVR_SCAN_BIN__SI__VI  regDC_ABM1_LS_OVR_SCAN_BIN__SI__VI;
typedef union DC_ABM1_LS_PIXEL_COUNT__SI__VI   regDC_ABM1_LS_PIXEL_COUNT__SI__VI;
typedef union DC_ABM1_LS_SAMPLE_RATE__SI__VI   regDC_ABM1_LS_SAMPLE_RATE__SI__VI;
typedef union DC_ABM1_LS_SUM_OF_LUMA__SI__VI   regDC_ABM1_LS_SUM_OF_LUMA__SI__VI;
typedef union DC_DMCU_SCRATCH__SI__VI          regDC_DMCU_SCRATCH__SI__VI;
typedef union DC_GENERICA__SI                  regDC_GENERICA__SI;
typedef union DC_GENERICA__VI                  regDC_GENERICA__VI;
typedef union DC_GENERICB__SI__VI              regDC_GENERICB__SI__VI;
typedef union DC_GPIO_DDC1_A__SI__VI           regDC_GPIO_DDC1_A__SI__VI;
typedef union DC_GPIO_DDC1_EN__SI__VI          regDC_GPIO_DDC1_EN__SI__VI;
typedef union DC_GPIO_DDC1_MASK__SI__VI        regDC_GPIO_DDC1_MASK__SI__VI;
typedef union DC_GPIO_DDC1_Y__SI__VI           regDC_GPIO_DDC1_Y__SI__VI;
typedef union DC_GPIO_DDC2_A__SI__VI           regDC_GPIO_DDC2_A__SI__VI;
typedef union DC_GPIO_DDC2_EN__SI__VI          regDC_GPIO_DDC2_EN__SI__VI;
typedef union DC_GPIO_DDC2_MASK__SI__VI        regDC_GPIO_DDC2_MASK__SI__VI;
typedef union DC_GPIO_DDC2_Y__SI__VI           regDC_GPIO_DDC2_Y__SI__VI;
typedef union DC_GPIO_DDC3_A__SI__VI           regDC_GPIO_DDC3_A__SI__VI;
typedef union DC_GPIO_DDC3_EN__SI__VI          regDC_GPIO_DDC3_EN__SI__VI;
typedef union DC_GPIO_DDC3_MASK__SI__VI        regDC_GPIO_DDC3_MASK__SI__VI;
typedef union DC_GPIO_DDC3_Y__SI__VI           regDC_GPIO_DDC3_Y__SI__VI;
typedef union DC_GPIO_DDC4_A__SI__VI           regDC_GPIO_DDC4_A__SI__VI;
typedef union DC_GPIO_DDC4_EN__SI__VI          regDC_GPIO_DDC4_EN__SI__VI;
typedef union DC_GPIO_DDC4_MASK__SI__VI        regDC_GPIO_DDC4_MASK__SI__VI;
typedef union DC_GPIO_DDC4_Y__SI__VI           regDC_GPIO_DDC4_Y__SI__VI;
typedef union DC_GPIO_DDC5_A__SI__VI           regDC_GPIO_DDC5_A__SI__VI;
typedef union DC_GPIO_DDC5_EN__SI__VI          regDC_GPIO_DDC5_EN__SI__VI;
typedef union DC_GPIO_DDC5_MASK__SI__VI        regDC_GPIO_DDC5_MASK__SI__VI;
typedef union DC_GPIO_DDC5_Y__SI__VI           regDC_GPIO_DDC5_Y__SI__VI;
typedef union DC_GPIO_DDC6_A__SI__VI           regDC_GPIO_DDC6_A__SI__VI;
typedef union DC_GPIO_DDC6_EN__SI__VI          regDC_GPIO_DDC6_EN__SI__VI;
typedef union DC_GPIO_DDC6_MASK__SI__VI        regDC_GPIO_DDC6_MASK__SI__VI;
typedef union DC_GPIO_DDC6_Y__SI__VI           regDC_GPIO_DDC6_Y__SI__VI;
typedef union DC_GPIO_DEBUG__SI__VI            regDC_GPIO_DEBUG__SI__VI;
typedef union DC_GPIO_DVODATA_A__SI            regDC_GPIO_DVODATA_A__SI;
typedef union DC_GPIO_DVODATA_A__VI            regDC_GPIO_DVODATA_A__VI;
typedef union DC_GPIO_DVODATA_EN__SI           regDC_GPIO_DVODATA_EN__SI;
typedef union DC_GPIO_DVODATA_EN__VI           regDC_GPIO_DVODATA_EN__VI;
typedef union DC_GPIO_DVODATA_MASK__SI         regDC_GPIO_DVODATA_MASK__SI;
typedef union DC_GPIO_DVODATA_MASK__VI         regDC_GPIO_DVODATA_MASK__VI;
typedef union DC_GPIO_DVODATA_Y__SI            regDC_GPIO_DVODATA_Y__SI;
typedef union DC_GPIO_DVODATA_Y__VI            regDC_GPIO_DVODATA_Y__VI;
typedef union DC_GPIO_GENERIC_A__SI__VI        regDC_GPIO_GENERIC_A__SI__VI;
typedef union DC_GPIO_GENERIC_EN__SI__VI       regDC_GPIO_GENERIC_EN__SI__VI;
typedef union DC_GPIO_GENERIC_MASK__SI__VI     regDC_GPIO_GENERIC_MASK__SI__VI;
typedef union DC_GPIO_GENERIC_Y__SI__VI        regDC_GPIO_GENERIC_Y__SI__VI;
typedef union DC_GPIO_HPD_A__SI__VI            regDC_GPIO_HPD_A__SI__VI;
typedef union DC_GPIO_HPD_EN__SI__VI           regDC_GPIO_HPD_EN__SI__VI;
typedef union DC_GPIO_HPD_MASK__SI             regDC_GPIO_HPD_MASK__SI;
typedef union DC_GPIO_HPD_MASK__VI             regDC_GPIO_HPD_MASK__VI;
typedef union DC_GPIO_HPD_Y__SI__VI            regDC_GPIO_HPD_Y__SI__VI;
typedef union DC_GPIO_PAD_STRENGTH_1__SI__VI   regDC_GPIO_PAD_STRENGTH_1__SI__VI;
typedef union DC_GPIO_PAD_STRENGTH_2__SI__VI   regDC_GPIO_PAD_STRENGTH_2__SI__VI;
typedef union DC_GPIO_PWRSEQ_A__SI__VI         regDC_GPIO_PWRSEQ_A__SI__VI;
typedef union DC_GPIO_PWRSEQ_EN__SI__VI        regDC_GPIO_PWRSEQ_EN__SI__VI;
typedef union DC_GPIO_PWRSEQ_MASK__SI__VI      regDC_GPIO_PWRSEQ_MASK__SI__VI;
typedef union DC_GPIO_PWRSEQ_Y__SI__VI         regDC_GPIO_PWRSEQ_Y__SI__VI;
typedef union DC_GPIO_SYNCA_A__SI__VI          regDC_GPIO_SYNCA_A__SI__VI;
typedef union DC_GPIO_SYNCA_EN__SI__VI         regDC_GPIO_SYNCA_EN__SI__VI;
typedef union DC_GPIO_SYNCA_MASK__SI__VI       regDC_GPIO_SYNCA_MASK__SI__VI;
typedef union DC_GPIO_SYNCA_Y__SI__VI          regDC_GPIO_SYNCA_Y__SI__VI;
typedef union DC_GPU_TIMER_READ_CNTL__SI__VI   regDC_GPU_TIMER_READ_CNTL__SI__VI;
typedef union DC_GPU_TIMER_READ__SI__VI        regDC_GPU_TIMER_READ__SI__VI;
typedef union DC_GPU_TIMER_START_POSITION__SI  regDC_GPU_TIMER_START_POSITION__SI;
typedef union DC_HPD1_CONTROL__SI              regDC_HPD1_CONTROL__SI;
typedef union DC_HPD1_INT_CONTROL__SI          regDC_HPD1_INT_CONTROL__SI;
typedef union DC_HPD1_INT_STATUS__SI           regDC_HPD1_INT_STATUS__SI;
typedef union DC_HPD2_CONTROL__SI              regDC_HPD2_CONTROL__SI;
typedef union DC_HPD2_INT_CONTROL__SI          regDC_HPD2_INT_CONTROL__SI;
typedef union DC_HPD2_INT_STATUS__SI           regDC_HPD2_INT_STATUS__SI;
typedef union DC_HPD3_CONTROL__SI              regDC_HPD3_CONTROL__SI;
typedef union DC_HPD3_INT_CONTROL__SI          regDC_HPD3_INT_CONTROL__SI;
typedef union DC_HPD3_INT_STATUS__SI           regDC_HPD3_INT_STATUS__SI;
typedef union DC_HPD4_CONTROL__SI              regDC_HPD4_CONTROL__SI;
typedef union DC_HPD4_INT_CONTROL__SI          regDC_HPD4_INT_CONTROL__SI;
typedef union DC_HPD4_INT_STATUS__SI           regDC_HPD4_INT_STATUS__SI;
typedef union DC_HPD5_CONTROL__SI              regDC_HPD5_CONTROL__SI;
typedef union DC_HPD5_INT_CONTROL__SI          regDC_HPD5_INT_CONTROL__SI;
typedef union DC_HPD5_INT_STATUS__SI           regDC_HPD5_INT_STATUS__SI;
typedef union DC_HPD6_CONTROL__SI              regDC_HPD6_CONTROL__SI;
typedef union DC_HPD6_INT_CONTROL__SI          regDC_HPD6_INT_CONTROL__SI;
typedef union DC_HPD6_INT_STATUS__SI           regDC_HPD6_INT_STATUS__SI;
typedef union DC_I2C_ARBITRATION__SI__VI       regDC_I2C_ARBITRATION__SI__VI;
typedef union DC_I2C_CONTROL__SI__VI           regDC_I2C_CONTROL__SI__VI;
typedef union DC_I2C_DATA__SI__VI              regDC_I2C_DATA__SI__VI;
typedef union DC_I2C_DDC1_HW_STATUS__SI__VI    regDC_I2C_DDC1_HW_STATUS__SI__VI;
typedef union DC_I2C_DDC1_SETUP__SI__VI        regDC_I2C_DDC1_SETUP__SI__VI;
typedef union DC_I2C_DDC1_SPEED__SI__VI        regDC_I2C_DDC1_SPEED__SI__VI;
typedef union DC_I2C_DDC2_HW_STATUS__SI__VI    regDC_I2C_DDC2_HW_STATUS__SI__VI;
typedef union DC_I2C_DDC2_SETUP__SI__VI        regDC_I2C_DDC2_SETUP__SI__VI;
typedef union DC_I2C_DDC2_SPEED__SI__VI        regDC_I2C_DDC2_SPEED__SI__VI;
typedef union DC_I2C_DDC3_HW_STATUS__SI__VI    regDC_I2C_DDC3_HW_STATUS__SI__VI;
typedef union DC_I2C_DDC3_SETUP__SI__VI        regDC_I2C_DDC3_SETUP__SI__VI;
typedef union DC_I2C_DDC3_SPEED__SI__VI        regDC_I2C_DDC3_SPEED__SI__VI;
typedef union DC_I2C_DDC4_HW_STATUS__SI__VI    regDC_I2C_DDC4_HW_STATUS__SI__VI;
typedef union DC_I2C_DDC4_SETUP__SI__VI        regDC_I2C_DDC4_SETUP__SI__VI;
typedef union DC_I2C_DDC4_SPEED__SI__VI        regDC_I2C_DDC4_SPEED__SI__VI;
typedef union DC_I2C_DDC5_HW_STATUS__SI__VI    regDC_I2C_DDC5_HW_STATUS__SI__VI;
typedef union DC_I2C_DDC5_SETUP__SI__VI        regDC_I2C_DDC5_SETUP__SI__VI;
typedef union DC_I2C_DDC5_SPEED__SI__VI        regDC_I2C_DDC5_SPEED__SI__VI;
typedef union DC_I2C_DDC6_HW_STATUS__SI__VI    regDC_I2C_DDC6_HW_STATUS__SI__VI;
typedef union DC_I2C_DDC6_SETUP__SI__VI        regDC_I2C_DDC6_SETUP__SI__VI;
typedef union DC_I2C_DDC6_SPEED__SI__VI        regDC_I2C_DDC6_SPEED__SI__VI;
typedef union DC_I2C_INTERRUPT_CONTROL__SI__VI regDC_I2C_INTERRUPT_CONTROL__SI__VI;
typedef union DC_I2C_SW_STATUS__SI             regDC_I2C_SW_STATUS__SI;
typedef union DC_I2C_SW_STATUS__VI             regDC_I2C_SW_STATUS__VI;
typedef union DC_I2C_TRANSACTION0__SI__VI      regDC_I2C_TRANSACTION0__SI__VI;
typedef union DC_I2C_TRANSACTION1__SI__VI      regDC_I2C_TRANSACTION1__SI__VI;
typedef union DC_I2C_TRANSACTION2__SI__VI      regDC_I2C_TRANSACTION2__SI__VI;
typedef union DC_I2C_TRANSACTION3__SI__VI      regDC_I2C_TRANSACTION3__SI__VI;
typedef union DC_LUT_30_COLOR__SI__VI          regDC_LUT_30_COLOR__SI__VI;
typedef union DC_LUT_AUTOFILL__SI__VI          regDC_LUT_AUTOFILL__SI__VI;
typedef union DC_LUT_BLACK_OFFSET_BLUE__SI__VI regDC_LUT_BLACK_OFFSET_BLUE__SI__VI;
typedef union DC_LUT_BLACK_OFFSET_GREEN__SI__VI regDC_LUT_BLACK_OFFSET_GREEN__SI__VI;
typedef union DC_LUT_BLACK_OFFSET_RED__SI__VI  regDC_LUT_BLACK_OFFSET_RED__SI__VI;
typedef union DC_LUT_CONTROL__SI__VI           regDC_LUT_CONTROL__SI__VI;
typedef union DC_LUT_PWL_DATA__SI__VI          regDC_LUT_PWL_DATA__SI__VI;
typedef union DC_LUT_RW_INDEX__SI__VI          regDC_LUT_RW_INDEX__SI__VI;
typedef union DC_LUT_RW_MODE__SI__VI           regDC_LUT_RW_MODE__SI__VI;
typedef union DC_LUT_SEQ_COLOR__SI__VI         regDC_LUT_SEQ_COLOR__SI__VI;
typedef union DC_LUT_WHITE_OFFSET_BLUE__SI__VI regDC_LUT_WHITE_OFFSET_BLUE__SI__VI;
typedef union DC_LUT_WHITE_OFFSET_GREEN__SI__VI regDC_LUT_WHITE_OFFSET_GREEN__SI__VI;
typedef union DC_LUT_WHITE_OFFSET_RED__SI__VI  regDC_LUT_WHITE_OFFSET_RED__SI__VI;
typedef union DC_LUT_WRITE_EN_MASK__SI__VI     regDC_LUT_WRITE_EN_MASK__SI__VI;
typedef union DC_MVP_LB_CONTROL__SI            regDC_MVP_LB_CONTROL__SI;
typedef union DC_MVP_LB_CONTROL__VI            regDC_MVP_LB_CONTROL__VI;
typedef union DC_PAD_EXTERN_SIG__SI__VI        regDC_PAD_EXTERN_SIG__SI__VI;
typedef union DC_PINSTRAPS__SI                 regDC_PINSTRAPS__SI;
typedef union DC_PINSTRAPS__VI                 regDC_PINSTRAPS__VI;
typedef union DC_REF_CLK_CNTL__SI              regDC_REF_CLK_CNTL__SI;
typedef union DC_REF_CLK_CNTL__VI              regDC_REF_CLK_CNTL__VI;
typedef union DC_TEST_DEBUG_DATA__SI__VI       regDC_TEST_DEBUG_DATA__SI__VI;
typedef union DC_TEST_DEBUG_INDEX__SI__VI      regDC_TEST_DEBUG_INDEX__SI__VI;
typedef union DEBUG_DATA                       regDEBUG_DATA;
typedef union DEBUG_INDEX                      regDEBUG_INDEX;
typedef union DENTIST_DISPCLK_CNTL__SI         regDENTIST_DISPCLK_CNTL__SI;
typedef union DENTIST_DISPCLK_CNTL__VI         regDENTIST_DISPCLK_CNTL__VI;
typedef union DEVICE_CAP                       regDEVICE_CAP;
typedef union DEVICE_CAP2__CI__VI              regDEVICE_CAP2__CI__VI;
typedef union DEVICE_CAP2__SI                  regDEVICE_CAP2__SI;
typedef union DEVICE_CNTL2                     regDEVICE_CNTL2;
typedef union DEVICE_CNTL__CI__VI              regDEVICE_CNTL__CI__VI;
typedef union DEVICE_CNTL__SI                  regDEVICE_CNTL__SI;
typedef union DEVICE_ID                        regDEVICE_ID;
typedef union DEVICE_STATUS                    regDEVICE_STATUS;
typedef union DEVICE_STATUS2                   regDEVICE_STATUS2;
typedef union DH_TEST                          regDH_TEST;
typedef union DIDT_DB_CTRL0__CI__VI            regDIDT_DB_CTRL0__CI__VI;
typedef union DIDT_DB_CTRL1__CI__VI            regDIDT_DB_CTRL1__CI__VI;
typedef union DIDT_DB_CTRL2__CI__VI            regDIDT_DB_CTRL2__CI__VI;
typedef union DIDT_DB_WEIGHT0_3__CI__VI        regDIDT_DB_WEIGHT0_3__CI__VI;
typedef union DIDT_DB_WEIGHT4_7__CI__VI        regDIDT_DB_WEIGHT4_7__CI__VI;
typedef union DIDT_DB_WEIGHT8_11__CI__VI       regDIDT_DB_WEIGHT8_11__CI__VI;
typedef union DIDT_IND_DATA__CI__VI            regDIDT_IND_DATA__CI__VI;
typedef union DIDT_IND_INDEX__CI__VI           regDIDT_IND_INDEX__CI__VI;
typedef union DIDT_SQ_CTRL0__CI__VI            regDIDT_SQ_CTRL0__CI__VI;
typedef union DIDT_SQ_CTRL1__CI__VI            regDIDT_SQ_CTRL1__CI__VI;
typedef union DIDT_SQ_CTRL2__CI__VI            regDIDT_SQ_CTRL2__CI__VI;
typedef union DIDT_SQ_WEIGHT0_3__CI__VI        regDIDT_SQ_WEIGHT0_3__CI__VI;
typedef union DIDT_SQ_WEIGHT4_7__CI__VI        regDIDT_SQ_WEIGHT4_7__CI__VI;
typedef union DIDT_SQ_WEIGHT8_11__CI__VI       regDIDT_SQ_WEIGHT8_11__CI__VI;
typedef union DIDT_TCP_CTRL0__CI__VI           regDIDT_TCP_CTRL0__CI__VI;
typedef union DIDT_TCP_CTRL1__CI__VI           regDIDT_TCP_CTRL1__CI__VI;
typedef union DIDT_TCP_CTRL2__CI__VI           regDIDT_TCP_CTRL2__CI__VI;
typedef union DIDT_TCP_WEIGHT0_3__CI__VI       regDIDT_TCP_WEIGHT0_3__CI__VI;
typedef union DIDT_TCP_WEIGHT4_7__CI__VI       regDIDT_TCP_WEIGHT4_7__CI__VI;
typedef union DIDT_TCP_WEIGHT8_11__CI__VI      regDIDT_TCP_WEIGHT8_11__CI__VI;
typedef union DIDT_TD_CTRL0__CI__VI            regDIDT_TD_CTRL0__CI__VI;
typedef union DIDT_TD_CTRL1__CI__VI            regDIDT_TD_CTRL1__CI__VI;
typedef union DIDT_TD_CTRL2__CI__VI            regDIDT_TD_CTRL2__CI__VI;
typedef union DIDT_TD_WEIGHT0_3__CI__VI        regDIDT_TD_WEIGHT0_3__CI__VI;
typedef union DIDT_TD_WEIGHT4_7__CI__VI        regDIDT_TD_WEIGHT4_7__CI__VI;
typedef union DIDT_TD_WEIGHT8_11__CI__VI       regDIDT_TD_WEIGHT8_11__CI__VI;
typedef union DIG_CLOCK_PATTERN__SI__VI        regDIG_CLOCK_PATTERN__SI__VI;
typedef union DIG_OUTPUT_CRC_CNTL__SI__VI      regDIG_OUTPUT_CRC_CNTL__SI__VI;
typedef union DIG_OUTPUT_CRC_RESULT__SI__VI    regDIG_OUTPUT_CRC_RESULT__SI__VI;
typedef union DIG_RANDOM_PATTERN_SEED__SI__VI  regDIG_RANDOM_PATTERN_SEED__SI__VI;
typedef union DIG_TEST_PATTERN__SI__VI         regDIG_TEST_PATTERN__SI__VI;
typedef union DISPCLK_CGTT_BLK_CTRL_REG__SI__VI regDISPCLK_CGTT_BLK_CTRL_REG__SI__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE2__SI regDISP_INTERRUPT_STATUS_CONTINUE2__SI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE2__VI regDISP_INTERRUPT_STATUS_CONTINUE2__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE__SI regDISP_INTERRUPT_STATUS_CONTINUE__SI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE__VI regDISP_INTERRUPT_STATUS_CONTINUE__VI;
typedef union DISP_INTERRUPT_STATUS__SI        regDISP_INTERRUPT_STATUS__SI;
typedef union DISP_INTERRUPT_STATUS__VI        regDISP_INTERRUPT_STATUS__VI;
typedef union DISP_TIMER_CONTROL__SI           regDISP_TIMER_CONTROL__SI;
typedef union DLL_CNTL__SI__CI                 regDLL_CNTL__SI__CI;
typedef union DMA_POSITION_LOWER_BASE_ADDRESS__SI__VI regDMA_POSITION_LOWER_BASE_ADDRESS__SI__VI;
typedef union DMA_POSITION_UPPER_BASE_ADDRESS__SI__VI regDMA_POSITION_UPPER_BASE_ADDRESS__SI__VI;
typedef union DMCU_CTRL__SI                    regDMCU_CTRL__SI;
typedef union DMCU_CTRL__VI                    regDMCU_CTRL__VI;
typedef union DMCU_ERAM_RD_CTRL__SI__VI        regDMCU_ERAM_RD_CTRL__SI__VI;
typedef union DMCU_ERAM_RD_DATA__SI__VI        regDMCU_ERAM_RD_DATA__SI__VI;
typedef union DMCU_ERAM_WR_CTRL__SI__VI        regDMCU_ERAM_WR_CTRL__SI__VI;
typedef union DMCU_ERAM_WR_DATA__SI__VI        regDMCU_ERAM_WR_DATA__SI__VI;
typedef union DMCU_EVENT_TRIGGER__SI__VI       regDMCU_EVENT_TRIGGER__SI__VI;
typedef union DMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI__VI regDMCU_FW_CHECKSUM_SMPL_BYTE_POS__SI__VI;
typedef union DMCU_FW_CS_HI__SI__VI            regDMCU_FW_CS_HI__SI__VI;
typedef union DMCU_FW_CS_LO__SI__VI            regDMCU_FW_CS_LO__SI__VI;
typedef union DMCU_FW_END_ADDR__SI__VI         regDMCU_FW_END_ADDR__SI__VI;
typedef union DMCU_FW_ISR_START_ADDR__SI__VI   regDMCU_FW_ISR_START_ADDR__SI__VI;
typedef union DMCU_FW_START_ADDR__SI__VI       regDMCU_FW_START_ADDR__SI__VI;
typedef union DMCU_INTERRUPT_STATUS__SI        regDMCU_INTERRUPT_STATUS__SI;
typedef union DMCU_INTERRUPT_STATUS__VI        regDMCU_INTERRUPT_STATUS__VI;
typedef union DMCU_INTERRUPT_TO_HOST_EN_MASK__SI__VI regDMCU_INTERRUPT_TO_HOST_EN_MASK__SI__VI;
typedef union DMCU_INTERRUPT_TO_UC_EN_MASK__SI regDMCU_INTERRUPT_TO_UC_EN_MASK__SI;
typedef union DMCU_INTERRUPT_TO_UC_EN_MASK__VI regDMCU_INTERRUPT_TO_UC_EN_MASK__VI;
typedef union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__SI;
typedef union DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VI regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VI;
typedef union DMCU_INT_CNT__SI__VI             regDMCU_INT_CNT__SI__VI;
typedef union DMCU_IRAM_RD_CTRL__SI__VI        regDMCU_IRAM_RD_CTRL__SI__VI;
typedef union DMCU_IRAM_RD_DATA__SI__VI        regDMCU_IRAM_RD_DATA__SI__VI;
typedef union DMCU_IRAM_WR_CTRL__SI__VI        regDMCU_IRAM_WR_CTRL__SI__VI;
typedef union DMCU_IRAM_WR_DATA__SI__VI        regDMCU_IRAM_WR_DATA__SI__VI;
typedef union DMCU_PC_START_ADDR__SI__VI       regDMCU_PC_START_ADDR__SI__VI;
typedef union DMCU_RAM_ACCESS_CTRL__SI__VI     regDMCU_RAM_ACCESS_CTRL__SI__VI;
typedef union DMCU_STATUS__SI__VI              regDMCU_STATUS__SI__VI;
typedef union DMCU_TEST_DEBUG_DATA__SI__VI     regDMCU_TEST_DEBUG_DATA__SI__VI;
typedef union DMCU_TEST_DEBUG_INDEX__SI__VI    regDMCU_TEST_DEBUG_INDEX__SI__VI;
typedef union DMCU_UC_INTERNAL_INT_STATUS__SI__VI regDMCU_UC_INTERNAL_INT_STATUS__SI__VI;
typedef union DMIF_ARBITRATION_CONTROL__SI__VI regDMIF_ARBITRATION_CONTROL__SI__VI;
typedef union DMIF_CONTROL__SI__VI             regDMIF_CONTROL__SI__VI;
typedef union DMIF_DEBUG02__SI                 regDMIF_DEBUG02__SI;
typedef union DMIF_HW_DEBUG__SI__VI            regDMIF_HW_DEBUG__SI__VI;
typedef union DMIF_STATUS__SI__VI              regDMIF_STATUS__SI__VI;
typedef union DMIF_TEST_DEBUG_DATA__SI__VI     regDMIF_TEST_DEBUG_DATA__SI__VI;
typedef union DMIF_TEST_DEBUG_INDEX__SI__VI    regDMIF_TEST_DEBUG_INDEX__SI__VI;
typedef union DOUT_POWER_MANAGEMENT_CNTL__SI   regDOUT_POWER_MANAGEMENT_CNTL__SI;
typedef union DOUT_SCRATCH0__SI                regDOUT_SCRATCH0__SI;
typedef union DOUT_SCRATCH1__SI                regDOUT_SCRATCH1__SI;
typedef union DOUT_SCRATCH2__SI                regDOUT_SCRATCH2__SI;
typedef union DOUT_SCRATCH3__SI                regDOUT_SCRATCH3__SI;
typedef union DOUT_SCRATCH4__SI                regDOUT_SCRATCH4__SI;
typedef union DOUT_SCRATCH5__SI                regDOUT_SCRATCH5__SI;
typedef union DOUT_SCRATCH6__SI                regDOUT_SCRATCH6__SI;
typedef union DOUT_SCRATCH7__SI                regDOUT_SCRATCH7__SI;
typedef union DOUT_TEST_DEBUG_DATA__SI         regDOUT_TEST_DEBUG_DATA__SI;
typedef union DOUT_TEST_DEBUG_INDEX__SI        regDOUT_TEST_DEBUG_INDEX__SI;
typedef union DP_AUX1_DEBUG_A__SI              regDP_AUX1_DEBUG_A__SI;
typedef union DP_AUX1_DEBUG_B__SI              regDP_AUX1_DEBUG_B__SI;
typedef union DP_AUX1_DEBUG_C__SI              regDP_AUX1_DEBUG_C__SI;
typedef union DP_AUX1_DEBUG_D__SI              regDP_AUX1_DEBUG_D__SI;
typedef union DP_AUX1_DEBUG_E__SI              regDP_AUX1_DEBUG_E__SI;
typedef union DP_AUX1_DEBUG_F__SI              regDP_AUX1_DEBUG_F__SI;
typedef union DP_AUX1_DEBUG_G__SI              regDP_AUX1_DEBUG_G__SI;
typedef union DP_AUX1_DEBUG_H__SI              regDP_AUX1_DEBUG_H__SI;
typedef union DP_AUX1_DEBUG_I__SI              regDP_AUX1_DEBUG_I__SI;
typedef union DP_AUX2_DEBUG_A__SI              regDP_AUX2_DEBUG_A__SI;
typedef union DP_AUX2_DEBUG_B__SI              regDP_AUX2_DEBUG_B__SI;
typedef union DP_AUX2_DEBUG_C__SI              regDP_AUX2_DEBUG_C__SI;
typedef union DP_AUX2_DEBUG_D__SI              regDP_AUX2_DEBUG_D__SI;
typedef union DP_AUX2_DEBUG_E__SI              regDP_AUX2_DEBUG_E__SI;
typedef union DP_AUX2_DEBUG_F__SI              regDP_AUX2_DEBUG_F__SI;
typedef union DP_AUX2_DEBUG_G__SI              regDP_AUX2_DEBUG_G__SI;
typedef union DP_AUX2_DEBUG_H__SI              regDP_AUX2_DEBUG_H__SI;
typedef union DP_AUX2_DEBUG_I__SI              regDP_AUX2_DEBUG_I__SI;
typedef union DP_AUX3_DEBUG_A__SI              regDP_AUX3_DEBUG_A__SI;
typedef union DP_AUX3_DEBUG_B__SI              regDP_AUX3_DEBUG_B__SI;
typedef union DP_AUX3_DEBUG_C__SI              regDP_AUX3_DEBUG_C__SI;
typedef union DP_AUX3_DEBUG_D__SI              regDP_AUX3_DEBUG_D__SI;
typedef union DP_AUX3_DEBUG_E__SI              regDP_AUX3_DEBUG_E__SI;
typedef union DP_AUX3_DEBUG_F__SI              regDP_AUX3_DEBUG_F__SI;
typedef union DP_AUX3_DEBUG_G__SI              regDP_AUX3_DEBUG_G__SI;
typedef union DP_AUX3_DEBUG_H__SI              regDP_AUX3_DEBUG_H__SI;
typedef union DP_AUX3_DEBUG_I__SI              regDP_AUX3_DEBUG_I__SI;
typedef union DP_AUX4_DEBUG_A__SI              regDP_AUX4_DEBUG_A__SI;
typedef union DP_AUX4_DEBUG_B__SI              regDP_AUX4_DEBUG_B__SI;
typedef union DP_AUX4_DEBUG_C__SI              regDP_AUX4_DEBUG_C__SI;
typedef union DP_AUX4_DEBUG_D__SI              regDP_AUX4_DEBUG_D__SI;
typedef union DP_AUX4_DEBUG_E__SI              regDP_AUX4_DEBUG_E__SI;
typedef union DP_AUX4_DEBUG_F__SI              regDP_AUX4_DEBUG_F__SI;
typedef union DP_AUX4_DEBUG_G__SI              regDP_AUX4_DEBUG_G__SI;
typedef union DP_AUX4_DEBUG_H__SI              regDP_AUX4_DEBUG_H__SI;
typedef union DP_AUX4_DEBUG_I__SI              regDP_AUX4_DEBUG_I__SI;
typedef union DP_AUX5_DEBUG_A__SI              regDP_AUX5_DEBUG_A__SI;
typedef union DP_AUX5_DEBUG_B__SI              regDP_AUX5_DEBUG_B__SI;
typedef union DP_AUX5_DEBUG_C__SI              regDP_AUX5_DEBUG_C__SI;
typedef union DP_AUX5_DEBUG_D__SI              regDP_AUX5_DEBUG_D__SI;
typedef union DP_AUX5_DEBUG_E__SI              regDP_AUX5_DEBUG_E__SI;
typedef union DP_AUX5_DEBUG_F__SI              regDP_AUX5_DEBUG_F__SI;
typedef union DP_AUX5_DEBUG_G__SI              regDP_AUX5_DEBUG_G__SI;
typedef union DP_AUX5_DEBUG_H__SI              regDP_AUX5_DEBUG_H__SI;
typedef union DP_AUX5_DEBUG_I__SI              regDP_AUX5_DEBUG_I__SI;
typedef union DP_AUX6_DEBUG_A__SI              regDP_AUX6_DEBUG_A__SI;
typedef union DP_AUX6_DEBUG_B__SI              regDP_AUX6_DEBUG_B__SI;
typedef union DP_AUX6_DEBUG_C__SI              regDP_AUX6_DEBUG_C__SI;
typedef union DP_AUX6_DEBUG_D__SI              regDP_AUX6_DEBUG_D__SI;
typedef union DP_AUX6_DEBUG_E__SI              regDP_AUX6_DEBUG_E__SI;
typedef union DP_AUX6_DEBUG_F__SI              regDP_AUX6_DEBUG_F__SI;
typedef union DP_AUX6_DEBUG_G__SI              regDP_AUX6_DEBUG_G__SI;
typedef union DP_AUX6_DEBUG_H__SI              regDP_AUX6_DEBUG_H__SI;
typedef union DP_AUX6_DEBUG_I__SI              regDP_AUX6_DEBUG_I__SI;
typedef union DP_CONFIG__SI__VI                regDP_CONFIG__SI__VI;
typedef union DP_DPHY_8B10B_CNTL__SI           regDP_DPHY_8B10B_CNTL__SI;
typedef union DP_DPHY_8B10B_CNTL__VI           regDP_DPHY_8B10B_CNTL__VI;
typedef union DP_DPHY_CNTL__SI__VI             regDP_DPHY_CNTL__SI__VI;
typedef union DP_DPHY_CRC_CNTL__SI__VI         regDP_DPHY_CRC_CNTL__SI__VI;
typedef union DP_DPHY_CRC_EN__SI__VI           regDP_DPHY_CRC_EN__SI__VI;
typedef union DP_DPHY_CRC_RESULT__SI__VI       regDP_DPHY_CRC_RESULT__SI__VI;
typedef union DP_DPHY_FAST_TRAINING__SI        regDP_DPHY_FAST_TRAINING__SI;
typedef union DP_DPHY_FAST_TRAINING__VI        regDP_DPHY_FAST_TRAINING__VI;
typedef union DP_DPHY_PRBS_CNTL__SI__VI        regDP_DPHY_PRBS_CNTL__SI__VI;
typedef union DP_DPHY_SYM__SI                  regDP_DPHY_SYM__SI;
typedef union DP_DPHY_TRAINING_PATTERN_SEL__SI__VI regDP_DPHY_TRAINING_PATTERN_SEL__SI__VI;
typedef union DP_DTO0_MODULO__SI__VI           regDP_DTO0_MODULO__SI__VI;
typedef union DP_DTO0_PHASE__SI__VI            regDP_DTO0_PHASE__SI__VI;
typedef union DP_DTO1_MODULO__SI__VI           regDP_DTO1_MODULO__SI__VI;
typedef union DP_DTO1_PHASE__SI__VI            regDP_DTO1_PHASE__SI__VI;
typedef union DP_DTO2_MODULO__SI__VI           regDP_DTO2_MODULO__SI__VI;
typedef union DP_DTO2_PHASE__SI__VI            regDP_DTO2_PHASE__SI__VI;
typedef union DP_DTO3_MODULO__SI__VI           regDP_DTO3_MODULO__SI__VI;
typedef union DP_DTO3_PHASE__SI__VI            regDP_DTO3_PHASE__SI__VI;
typedef union DP_DTO4_MODULO__SI__VI           regDP_DTO4_MODULO__SI__VI;
typedef union DP_DTO4_PHASE__SI__VI            regDP_DTO4_PHASE__SI__VI;
typedef union DP_DTO5_MODULO__SI__VI           regDP_DTO5_MODULO__SI__VI;
typedef union DP_DTO5_PHASE__SI__VI            regDP_DTO5_PHASE__SI__VI;
typedef union DP_LINK_CNTL__SI                 regDP_LINK_CNTL__SI;
typedef union DP_LINK_CNTL__VI                 regDP_LINK_CNTL__VI;
typedef union DP_PIXEL_FORMAT__SI__VI          regDP_PIXEL_FORMAT__SI__VI;
typedef union DP_SEC_AUD_M_READBACK__SI__VI    regDP_SEC_AUD_M_READBACK__SI__VI;
typedef union DP_SEC_AUD_M__SI__VI             regDP_SEC_AUD_M__SI__VI;
typedef union DP_SEC_AUD_N_READBACK__SI__VI    regDP_SEC_AUD_N_READBACK__SI__VI;
typedef union DP_SEC_AUD_N__SI__VI             regDP_SEC_AUD_N__SI__VI;
typedef union DP_SEC_CNTL__SI                  regDP_SEC_CNTL__SI;
typedef union DP_SEC_CNTL__VI                  regDP_SEC_CNTL__VI;
typedef union DP_SEC_FRAMING1__SI__VI          regDP_SEC_FRAMING1__SI__VI;
typedef union DP_SEC_FRAMING2__SI__VI          regDP_SEC_FRAMING2__SI__VI;
typedef union DP_SEC_FRAMING3__SI__VI          regDP_SEC_FRAMING3__SI__VI;
typedef union DP_SEC_FRAMING4__SI__VI          regDP_SEC_FRAMING4__SI__VI;
typedef union DP_SEC_PACKET_CNTL__SI           regDP_SEC_PACKET_CNTL__SI;
typedef union DP_SEC_PACKET_CNTL__VI           regDP_SEC_PACKET_CNTL__VI;
typedef union DP_SEC_TIMESTAMP__SI__VI         regDP_SEC_TIMESTAMP__SI__VI;
typedef union DP_STEER_FIFO__SI__VI            regDP_STEER_FIFO__SI__VI;
typedef union DP_TEST_DEBUG_DATA__SI__VI       regDP_TEST_DEBUG_DATA__SI__VI;
typedef union DP_TEST_DEBUG_INDEX__SI__VI      regDP_TEST_DEBUG_INDEX__SI__VI;
typedef union DP_VID_INTERRUPT_CNTL__SI__VI    regDP_VID_INTERRUPT_CNTL__SI__VI;
typedef union DP_VID_MSA_VBID__SI__VI          regDP_VID_MSA_VBID__SI__VI;
typedef union DP_VID_M__SI__VI                 regDP_VID_M__SI__VI;
typedef union DP_VID_N__SI__VI                 regDP_VID_N__SI__VI;
typedef union DP_VID_STREAM_CNTL__SI__VI       regDP_VID_STREAM_CNTL__SI__VI;
typedef union DP_VID_TIMING__SI__VI            regDP_VID_TIMING__SI__VI;
typedef union DVOACLKC_CNTL__SI__VI            regDVOACLKC_CNTL__SI__VI;
typedef union DVOACLKC_MVP_CNTL__SI__VI        regDVOACLKC_MVP_CNTL__SI__VI;
typedef union DVOACLKD_CNTL__SI__VI            regDVOACLKD_CNTL__SI__VI;
typedef union DVO_CONTROL__SI                  regDVO_CONTROL__SI;
typedef union DVO_CONTROL__VI                  regDVO_CONTROL__VI;
typedef union DVO_CRC2_SIG_MASK__SI__VI        regDVO_CRC2_SIG_MASK__SI__VI;
typedef union DVO_CRC2_SIG_RESULT__SI__VI      regDVO_CRC2_SIG_RESULT__SI__VI;
typedef union DVO_CRC_EN__SI__VI               regDVO_CRC_EN__SI__VI;
typedef union DVO_ENABLE__SI                   regDVO_ENABLE__SI;
typedef union DVO_ENABLE__VI                   regDVO_ENABLE__VI;
typedef union DVO_OUTPUT__SI__VI               regDVO_OUTPUT__SI__VI;
typedef union DVO_SOURCE_SELECT__SI__VI        regDVO_SOURCE_SELECT__SI__VI;
typedef union DVO_STRENGTH_CONTROL__SI         regDVO_STRENGTH_CONTROL__SI;
typedef union DVO_STRENGTH_CONTROL__VI         regDVO_STRENGTH_CONTROL__VI;
typedef union EXP0                             regEXP0;
typedef union EXP1                             regEXP1;
typedef union EXP2                             regEXP2;
typedef union EXP3                             regEXP3;
typedef union EXP4                             regEXP4;
typedef union EXP5                             regEXP5;
typedef union EXP6                             regEXP6;
typedef union EXP7                             regEXP7;
typedef union EXT_OVERSCAN_LEFT_RIGHT__SI__VI  regEXT_OVERSCAN_LEFT_RIGHT__SI__VI;
typedef union EXT_OVERSCAN_TOP_BOTTOM__SI__VI  regEXT_OVERSCAN_TOP_BOTTOM__SI__VI;
typedef union FBC_CLIENT_REGION_MASK__SI__VI   regFBC_CLIENT_REGION_MASK__SI__VI;
typedef union FBC_CNTL__SI__VI                 regFBC_CNTL__SI__VI;
typedef union FBC_COMP_CNTL__SI__VI            regFBC_COMP_CNTL__SI__VI;
typedef union FBC_COMP_MODE__SI__VI            regFBC_COMP_MODE__SI__VI;
typedef union FBC_CSM_REGION_OFFSET_01__SI__VI regFBC_CSM_REGION_OFFSET_01__SI__VI;
typedef union FBC_CSM_REGION_OFFSET_23__SI__VI regFBC_CSM_REGION_OFFSET_23__SI__VI;
typedef union FBC_DEBUG0__SI__VI               regFBC_DEBUG0__SI__VI;
typedef union FBC_DEBUG1__SI__VI               regFBC_DEBUG1__SI__VI;
typedef union FBC_DEBUG2__SI__VI               regFBC_DEBUG2__SI__VI;
typedef union FBC_DEBUG_COMP__SI__VI           regFBC_DEBUG_COMP__SI__VI;
typedef union FBC_DEBUG_CSR_RDATA__SI__VI      regFBC_DEBUG_CSR_RDATA__SI__VI;
typedef union FBC_DEBUG_CSR_WDATA__SI__VI      regFBC_DEBUG_CSR_WDATA__SI__VI;
typedef union FBC_DEBUG_CSR__SI__VI            regFBC_DEBUG_CSR__SI__VI;
typedef union FBC_IDLE_FORCE_CLEAR_MASK__SI__VI regFBC_IDLE_FORCE_CLEAR_MASK__SI__VI;
typedef union FBC_IDLE_MASK__SI__VI            regFBC_IDLE_MASK__SI__VI;
typedef union FBC_IND_LUT0__SI__VI             regFBC_IND_LUT0__SI__VI;
typedef union FBC_IND_LUT10__SI__VI            regFBC_IND_LUT10__SI__VI;
typedef union FBC_IND_LUT11__SI__VI            regFBC_IND_LUT11__SI__VI;
typedef union FBC_IND_LUT12__SI__VI            regFBC_IND_LUT12__SI__VI;
typedef union FBC_IND_LUT13__SI__VI            regFBC_IND_LUT13__SI__VI;
typedef union FBC_IND_LUT14__SI__VI            regFBC_IND_LUT14__SI__VI;
typedef union FBC_IND_LUT15__SI__VI            regFBC_IND_LUT15__SI__VI;
typedef union FBC_IND_LUT1__SI__VI             regFBC_IND_LUT1__SI__VI;
typedef union FBC_IND_LUT2__SI__VI             regFBC_IND_LUT2__SI__VI;
typedef union FBC_IND_LUT3__SI__VI             regFBC_IND_LUT3__SI__VI;
typedef union FBC_IND_LUT4__SI__VI             regFBC_IND_LUT4__SI__VI;
typedef union FBC_IND_LUT5__SI__VI             regFBC_IND_LUT5__SI__VI;
typedef union FBC_IND_LUT6__SI__VI             regFBC_IND_LUT6__SI__VI;
typedef union FBC_IND_LUT7__SI__VI             regFBC_IND_LUT7__SI__VI;
typedef union FBC_IND_LUT8__SI__VI             regFBC_IND_LUT8__SI__VI;
typedef union FBC_IND_LUT9__SI__VI             regFBC_IND_LUT9__SI__VI;
typedef union FBC_MISC__SI__VI                 regFBC_MISC__SI__VI;
typedef union FBC_START_STOP_DELAY__SI__VI     regFBC_START_STOP_DELAY__SI__VI;
typedef union FBC_TEST_DEBUG_DATA__SI__VI      regFBC_TEST_DEBUG_DATA__SI__VI;
typedef union FBC_TEST_DEBUG_INDEX__SI__VI     regFBC_TEST_DEBUG_INDEX__SI__VI;
typedef union FIRMWARE_FLAGS__CI__VI           regFIRMWARE_FLAGS__CI__VI;
typedef union FMT_BIT_DEPTH_CONTROL__SI        regFMT_BIT_DEPTH_CONTROL__SI;
typedef union FMT_BIT_DEPTH_CONTROL__VI        regFMT_BIT_DEPTH_CONTROL__VI;
typedef union FMT_CLAMP_CNTL__SI__VI           regFMT_CLAMP_CNTL__SI__VI;
typedef union FMT_CONTROL__SI__VI              regFMT_CONTROL__SI__VI;
typedef union FMT_CRC_CNTL__SI                 regFMT_CRC_CNTL__SI;
typedef union FMT_CRC_CNTL__VI                 regFMT_CRC_CNTL__VI;
typedef union FMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI regFMT_CRC_SIG_BLUE_CONTROL_MASK__SI__VI;
typedef union FMT_CRC_SIG_BLUE_CONTROL__SI__VI regFMT_CRC_SIG_BLUE_CONTROL__SI__VI;
typedef union FMT_CRC_SIG_RED_GREEN_MASK__SI__VI regFMT_CRC_SIG_RED_GREEN_MASK__SI__VI;
typedef union FMT_CRC_SIG_RED_GREEN__SI__VI    regFMT_CRC_SIG_RED_GREEN__SI__VI;
typedef union FMT_DEBUG_CNTL__SI__VI           regFMT_DEBUG_CNTL__SI__VI;
typedef union FMT_DITHER_RAND_B_SEED__SI__VI   regFMT_DITHER_RAND_B_SEED__SI__VI;
typedef union FMT_DITHER_RAND_G_SEED__SI__VI   regFMT_DITHER_RAND_G_SEED__SI__VI;
typedef union FMT_DITHER_RAND_R_SEED__SI__VI   regFMT_DITHER_RAND_R_SEED__SI__VI;
typedef union FMT_DYNAMIC_EXP_CNTL__SI__VI     regFMT_DYNAMIC_EXP_CNTL__SI__VI;
typedef union FMT_FORCE_DATA_0_1__SI__VI       regFMT_FORCE_DATA_0_1__SI__VI;
typedef union FMT_FORCE_DATA_2_3__SI__VI       regFMT_FORCE_DATA_2_3__SI__VI;
typedef union FMT_FORCE_OUTPUT_CNTL__SI        regFMT_FORCE_OUTPUT_CNTL__SI;
typedef union FMT_FORCE_OUTPUT_CNTL__VI        regFMT_FORCE_OUTPUT_CNTL__VI;
typedef union FMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI regFMT_TEMPORAL_DITHER_PATTERN_CONTROL__SI__VI;
typedef union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI regFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SI__VI;
typedef union FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI regFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SI__VI;
typedef union GARLIC_FLUSH_ADDR_END_0__CI__VI  regGARLIC_FLUSH_ADDR_END_0__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_1__CI__VI  regGARLIC_FLUSH_ADDR_END_1__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_2__CI__VI  regGARLIC_FLUSH_ADDR_END_2__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_3__CI__VI  regGARLIC_FLUSH_ADDR_END_3__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_4__CI__VI  regGARLIC_FLUSH_ADDR_END_4__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_5__CI__VI  regGARLIC_FLUSH_ADDR_END_5__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_6__CI__VI  regGARLIC_FLUSH_ADDR_END_6__CI__VI;
typedef union GARLIC_FLUSH_ADDR_END_7__CI__VI  regGARLIC_FLUSH_ADDR_END_7__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_0__CI__VI regGARLIC_FLUSH_ADDR_START_0__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_1__CI__VI regGARLIC_FLUSH_ADDR_START_1__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_2__CI__VI regGARLIC_FLUSH_ADDR_START_2__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_3__CI__VI regGARLIC_FLUSH_ADDR_START_3__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_4__CI__VI regGARLIC_FLUSH_ADDR_START_4__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_5__CI__VI regGARLIC_FLUSH_ADDR_START_5__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_6__CI__VI regGARLIC_FLUSH_ADDR_START_6__CI__VI;
typedef union GARLIC_FLUSH_ADDR_START_7__CI__VI regGARLIC_FLUSH_ADDR_START_7__CI__VI;
typedef union GARLIC_FLUSH_CNTL__CI            regGARLIC_FLUSH_CNTL__CI;
typedef union GARLIC_FLUSH_CNTL__VI            regGARLIC_FLUSH_CNTL__VI;
typedef union GARLIC_FLUSH_REQ__CI__VI         regGARLIC_FLUSH_REQ__CI__VI;
typedef union GB_ADDR_CONFIG                   regGB_ADDR_CONFIG;
typedef union GB_BACKEND_MAP                   regGB_BACKEND_MAP;
typedef union GB_EDC_MODE                      regGB_EDC_MODE;
typedef union GB_GPU_ID                        regGB_GPU_ID;
typedef union GB_MACROTILE_MODE0__CI__VI       regGB_MACROTILE_MODE0__CI__VI;
typedef union GB_MACROTILE_MODE10__CI__VI      regGB_MACROTILE_MODE10__CI__VI;
typedef union GB_MACROTILE_MODE11__CI__VI      regGB_MACROTILE_MODE11__CI__VI;
typedef union GB_MACROTILE_MODE12__CI__VI      regGB_MACROTILE_MODE12__CI__VI;
typedef union GB_MACROTILE_MODE13__CI__VI      regGB_MACROTILE_MODE13__CI__VI;
typedef union GB_MACROTILE_MODE14__CI__VI      regGB_MACROTILE_MODE14__CI__VI;
typedef union GB_MACROTILE_MODE15__CI__VI      regGB_MACROTILE_MODE15__CI__VI;
typedef union GB_MACROTILE_MODE1__CI__VI       regGB_MACROTILE_MODE1__CI__VI;
typedef union GB_MACROTILE_MODE2__CI__VI       regGB_MACROTILE_MODE2__CI__VI;
typedef union GB_MACROTILE_MODE3__CI__VI       regGB_MACROTILE_MODE3__CI__VI;
typedef union GB_MACROTILE_MODE4__CI__VI       regGB_MACROTILE_MODE4__CI__VI;
typedef union GB_MACROTILE_MODE5__CI__VI       regGB_MACROTILE_MODE5__CI__VI;
typedef union GB_MACROTILE_MODE6__CI__VI       regGB_MACROTILE_MODE6__CI__VI;
typedef union GB_MACROTILE_MODE7__CI__VI       regGB_MACROTILE_MODE7__CI__VI;
typedef union GB_MACROTILE_MODE8__CI__VI       regGB_MACROTILE_MODE8__CI__VI;
typedef union GB_MACROTILE_MODE9__CI__VI       regGB_MACROTILE_MODE9__CI__VI;
typedef union GB_TILE_MODE0                    regGB_TILE_MODE0;
typedef union GB_TILE_MODE1                    regGB_TILE_MODE1;
typedef union GB_TILE_MODE10                   regGB_TILE_MODE10;
typedef union GB_TILE_MODE11                   regGB_TILE_MODE11;
typedef union GB_TILE_MODE12                   regGB_TILE_MODE12;
typedef union GB_TILE_MODE13                   regGB_TILE_MODE13;
typedef union GB_TILE_MODE14                   regGB_TILE_MODE14;
typedef union GB_TILE_MODE15                   regGB_TILE_MODE15;
typedef union GB_TILE_MODE16                   regGB_TILE_MODE16;
typedef union GB_TILE_MODE17                   regGB_TILE_MODE17;
typedef union GB_TILE_MODE18                   regGB_TILE_MODE18;
typedef union GB_TILE_MODE19                   regGB_TILE_MODE19;
typedef union GB_TILE_MODE2                    regGB_TILE_MODE2;
typedef union GB_TILE_MODE20                   regGB_TILE_MODE20;
typedef union GB_TILE_MODE21                   regGB_TILE_MODE21;
typedef union GB_TILE_MODE22                   regGB_TILE_MODE22;
typedef union GB_TILE_MODE23                   regGB_TILE_MODE23;
typedef union GB_TILE_MODE24                   regGB_TILE_MODE24;
typedef union GB_TILE_MODE25                   regGB_TILE_MODE25;
typedef union GB_TILE_MODE26                   regGB_TILE_MODE26;
typedef union GB_TILE_MODE27                   regGB_TILE_MODE27;
typedef union GB_TILE_MODE28                   regGB_TILE_MODE28;
typedef union GB_TILE_MODE29                   regGB_TILE_MODE29;
typedef union GB_TILE_MODE3                    regGB_TILE_MODE3;
typedef union GB_TILE_MODE30                   regGB_TILE_MODE30;
typedef union GB_TILE_MODE31                   regGB_TILE_MODE31;
typedef union GB_TILE_MODE4                    regGB_TILE_MODE4;
typedef union GB_TILE_MODE5                    regGB_TILE_MODE5;
typedef union GB_TILE_MODE6                    regGB_TILE_MODE6;
typedef union GB_TILE_MODE7                    regGB_TILE_MODE7;
typedef union GB_TILE_MODE8                    regGB_TILE_MODE8;
typedef union GB_TILE_MODE9                    regGB_TILE_MODE9;
typedef union GCK_PLL_TEST_CNTL__CI            regGCK_PLL_TEST_CNTL__CI;
typedef union GCK_PLL_TEST_CNTL__VI            regGCK_PLL_TEST_CNTL__VI;
typedef union GCK_SMC_IND_DATA__CI__VI         regGCK_SMC_IND_DATA__CI__VI;
typedef union GCK_SMC_IND_INDEX__CI__VI        regGCK_SMC_IND_INDEX__CI__VI;
typedef union GC_USER_PRIM_CONFIG__CI__VI      regGC_USER_PRIM_CONFIG__CI__VI;
typedef union GC_USER_RB_BACKEND_DISABLE       regGC_USER_RB_BACKEND_DISABLE;
typedef union GC_USER_RB_REDUNDANCY__CI__VI    regGC_USER_RB_REDUNDANCY__CI__VI;
typedef union GC_USER_SHADER_ARRAY_CONFIG__SI__CI regGC_USER_SHADER_ARRAY_CONFIG__SI__CI;
typedef union GC_USER_SHADER_ARRAY_CONFIG__VI  regGC_USER_SHADER_ARRAY_CONFIG__VI;
typedef union GC_USER_SYS_RB_BACKEND_DISABLE   regGC_USER_SYS_RB_BACKEND_DISABLE;
typedef union GDS_ATOM_BASE                    regGDS_ATOM_BASE;
typedef union GDS_ATOM_CNTL                    regGDS_ATOM_CNTL;
typedef union GDS_ATOM_COMPLETE                regGDS_ATOM_COMPLETE;
typedef union GDS_ATOM_DST                     regGDS_ATOM_DST;
typedef union GDS_ATOM_OFFSET0                 regGDS_ATOM_OFFSET0;
typedef union GDS_ATOM_OFFSET1                 regGDS_ATOM_OFFSET1;
typedef union GDS_ATOM_OP                      regGDS_ATOM_OP;
typedef union GDS_ATOM_READ0                   regGDS_ATOM_READ0;
typedef union GDS_ATOM_READ0_U                 regGDS_ATOM_READ0_U;
typedef union GDS_ATOM_READ1                   regGDS_ATOM_READ1;
typedef union GDS_ATOM_READ1_U                 regGDS_ATOM_READ1_U;
typedef union GDS_ATOM_SIZE                    regGDS_ATOM_SIZE;
typedef union GDS_ATOM_SRC0                    regGDS_ATOM_SRC0;
typedef union GDS_ATOM_SRC0_U                  regGDS_ATOM_SRC0_U;
typedef union GDS_ATOM_SRC1                    regGDS_ATOM_SRC1;
typedef union GDS_ATOM_SRC1_U                  regGDS_ATOM_SRC1_U;
typedef union GDS_CNTL_STATUS                  regGDS_CNTL_STATUS;
typedef union GDS_COMPUTE_MAX_WAVE_ID__CI__VI  regGDS_COMPUTE_MAX_WAVE_ID__CI__VI;
typedef union GDS_CONFIG                       regGDS_CONFIG;
typedef union GDS_DEBUG_CNTL                   regGDS_DEBUG_CNTL;
typedef union GDS_DEBUG_DATA                   regGDS_DEBUG_DATA;
typedef union GDS_DEBUG_REG0__CI__VI           regGDS_DEBUG_REG0__CI__VI;
typedef union GDS_DEBUG_REG0__SI               regGDS_DEBUG_REG0__SI;
typedef union GDS_DEBUG_REG1__CI__VI           regGDS_DEBUG_REG1__CI__VI;
typedef union GDS_DEBUG_REG1__SI               regGDS_DEBUG_REG1__SI;
typedef union GDS_DEBUG_REG2__CI__VI           regGDS_DEBUG_REG2__CI__VI;
typedef union GDS_DEBUG_REG2__SI               regGDS_DEBUG_REG2__SI;
typedef union GDS_DEBUG_REG3__CI__VI           regGDS_DEBUG_REG3__CI__VI;
typedef union GDS_DEBUG_REG3__SI               regGDS_DEBUG_REG3__SI;
typedef union GDS_DEBUG_REG4__CI__VI           regGDS_DEBUG_REG4__CI__VI;
typedef union GDS_DEBUG_REG4__SI               regGDS_DEBUG_REG4__SI;
typedef union GDS_DEBUG_REG5__CI__VI           regGDS_DEBUG_REG5__CI__VI;
typedef union GDS_DEBUG_REG5__SI               regGDS_DEBUG_REG5__SI;
typedef union GDS_DEBUG_REG6__CI__VI           regGDS_DEBUG_REG6__CI__VI;
typedef union GDS_DEBUG_REG6__SI               regGDS_DEBUG_REG6__SI;
typedef union GDS_ENHANCE2__CI__VI             regGDS_ENHANCE2__CI__VI;
typedef union GDS_ENHANCE__CI__VI              regGDS_ENHANCE__CI__VI;
typedef union GDS_ENHANCE__SI                  regGDS_ENHANCE__SI;
typedef union GDS_GRBM_SECDED_CNT__CI          regGDS_GRBM_SECDED_CNT__CI;
typedef union GDS_GRBM_SECDED_CNT__SI          regGDS_GRBM_SECDED_CNT__SI;
typedef union GDS_GWS_RESET0__CI__VI           regGDS_GWS_RESET0__CI__VI;
typedef union GDS_GWS_RESET1__CI__VI           regGDS_GWS_RESET1__CI__VI;
typedef union GDS_GWS_RESOURCE_CNTL            regGDS_GWS_RESOURCE_CNTL;
typedef union GDS_GWS_RESOURCE_CNT__CI__VI     regGDS_GWS_RESOURCE_CNT__CI__VI;
typedef union GDS_GWS_RESOURCE_RESET__CI__VI   regGDS_GWS_RESOURCE_RESET__CI__VI;
typedef union GDS_GWS_RESOURCE__CI             regGDS_GWS_RESOURCE__CI;
typedef union GDS_GWS_RESOURCE__VI             regGDS_GWS_RESOURCE__VI;
typedef union GDS_GWS_RESOURCE__SI             regGDS_GWS_RESOURCE__SI;
typedef union GDS_GWS_VMID0__CI__VI            regGDS_GWS_VMID0__CI__VI;
typedef union GDS_GWS_VMID10__CI__VI           regGDS_GWS_VMID10__CI__VI;
typedef union GDS_GWS_VMID11__CI__VI           regGDS_GWS_VMID11__CI__VI;
typedef union GDS_GWS_VMID12__CI__VI           regGDS_GWS_VMID12__CI__VI;
typedef union GDS_GWS_VMID13__CI__VI           regGDS_GWS_VMID13__CI__VI;
typedef union GDS_GWS_VMID14__CI__VI           regGDS_GWS_VMID14__CI__VI;
typedef union GDS_GWS_VMID15__CI__VI           regGDS_GWS_VMID15__CI__VI;
typedef union GDS_GWS_VMID1__CI__VI            regGDS_GWS_VMID1__CI__VI;
typedef union GDS_GWS_VMID2__CI__VI            regGDS_GWS_VMID2__CI__VI;
typedef union GDS_GWS_VMID3__CI__VI            regGDS_GWS_VMID3__CI__VI;
typedef union GDS_GWS_VMID4__CI__VI            regGDS_GWS_VMID4__CI__VI;
typedef union GDS_GWS_VMID5__CI__VI            regGDS_GWS_VMID5__CI__VI;
typedef union GDS_GWS_VMID6__CI__VI            regGDS_GWS_VMID6__CI__VI;
typedef union GDS_GWS_VMID7__CI__VI            regGDS_GWS_VMID7__CI__VI;
typedef union GDS_GWS_VMID8__CI__VI            regGDS_GWS_VMID8__CI__VI;
typedef union GDS_GWS_VMID9__CI__VI            regGDS_GWS_VMID9__CI__VI;
typedef union GDS_OA_ADDRESS__CI               regGDS_OA_ADDRESS__CI;
typedef union GDS_OA_ADDRESS__VI               regGDS_OA_ADDRESS__VI;
typedef union GDS_OA_CGPG_RESTORE__CI__VI      regGDS_OA_CGPG_RESTORE__CI__VI;
typedef union GDS_OA_CNTL__CI__VI              regGDS_OA_CNTL__CI__VI;
typedef union GDS_OA_COUNTER__CI__VI           regGDS_OA_COUNTER__CI__VI;
typedef union GDS_OA_DED__CI                   regGDS_OA_DED__CI;
typedef union GDS_OA_DED__SI                   regGDS_OA_DED__SI;
typedef union GDS_OA_INCDEC__CI__VI            regGDS_OA_INCDEC__CI__VI;
typedef union GDS_OA_RESET_MASK__CI__VI        regGDS_OA_RESET_MASK__CI__VI;
typedef union GDS_OA_RESET__CI__VI             regGDS_OA_RESET__CI__VI;
typedef union GDS_OA_RING_SIZE__CI__VI         regGDS_OA_RING_SIZE__CI__VI;
typedef union GDS_OA_VMID0__CI__VI             regGDS_OA_VMID0__CI__VI;
typedef union GDS_OA_VMID10__CI__VI            regGDS_OA_VMID10__CI__VI;
typedef union GDS_OA_VMID11__CI__VI            regGDS_OA_VMID11__CI__VI;
typedef union GDS_OA_VMID12__CI__VI            regGDS_OA_VMID12__CI__VI;
typedef union GDS_OA_VMID13__CI__VI            regGDS_OA_VMID13__CI__VI;
typedef union GDS_OA_VMID14__CI__VI            regGDS_OA_VMID14__CI__VI;
typedef union GDS_OA_VMID15__CI__VI            regGDS_OA_VMID15__CI__VI;
typedef union GDS_OA_VMID1__CI__VI             regGDS_OA_VMID1__CI__VI;
typedef union GDS_OA_VMID2__CI__VI             regGDS_OA_VMID2__CI__VI;
typedef union GDS_OA_VMID3__CI__VI             regGDS_OA_VMID3__CI__VI;
typedef union GDS_OA_VMID4__CI__VI             regGDS_OA_VMID4__CI__VI;
typedef union GDS_OA_VMID5__CI__VI             regGDS_OA_VMID5__CI__VI;
typedef union GDS_OA_VMID6__CI__VI             regGDS_OA_VMID6__CI__VI;
typedef union GDS_OA_VMID7__CI__VI             regGDS_OA_VMID7__CI__VI;
typedef union GDS_OA_VMID8__CI__VI             regGDS_OA_VMID8__CI__VI;
typedef union GDS_OA_VMID9__CI__VI             regGDS_OA_VMID9__CI__VI;
typedef union GDS_PERFCOUNTER0_HI              regGDS_PERFCOUNTER0_HI;
typedef union GDS_PERFCOUNTER0_LO              regGDS_PERFCOUNTER0_LO;
typedef union GDS_PERFCOUNTER0_SELECT          regGDS_PERFCOUNTER0_SELECT;
typedef union GDS_PERFCOUNTER0_SELECT1__CI__VI regGDS_PERFCOUNTER0_SELECT1__CI__VI;
typedef union GDS_PERFCOUNTER1_HI              regGDS_PERFCOUNTER1_HI;
typedef union GDS_PERFCOUNTER1_LO              regGDS_PERFCOUNTER1_LO;
typedef union GDS_PERFCOUNTER1_SELECT          regGDS_PERFCOUNTER1_SELECT;
typedef union GDS_PERFCOUNTER2_HI              regGDS_PERFCOUNTER2_HI;
typedef union GDS_PERFCOUNTER2_LO              regGDS_PERFCOUNTER2_LO;
typedef union GDS_PERFCOUNTER2_SELECT          regGDS_PERFCOUNTER2_SELECT;
typedef union GDS_PERFCOUNTER3_HI              regGDS_PERFCOUNTER3_HI;
typedef union GDS_PERFCOUNTER3_LO              regGDS_PERFCOUNTER3_LO;
typedef union GDS_PERFCOUNTER3_SELECT          regGDS_PERFCOUNTER3_SELECT;
typedef union GDS_PROTECTION_FAULT__CI__VI     regGDS_PROTECTION_FAULT__CI__VI;
typedef union GDS_RD_ADDR                      regGDS_RD_ADDR;
typedef union GDS_RD_BURST_ADDR                regGDS_RD_BURST_ADDR;
typedef union GDS_RD_BURST_COUNT               regGDS_RD_BURST_COUNT;
typedef union GDS_RD_BURST_DATA                regGDS_RD_BURST_DATA;
typedef union GDS_RD_DATA                      regGDS_RD_DATA;
typedef union GDS_SECDED_CNT__CI               regGDS_SECDED_CNT__CI;
typedef union GDS_SECDED_CNT__SI               regGDS_SECDED_CNT__SI;
typedef union GDS_VMID0_BASE__CI__VI           regGDS_VMID0_BASE__CI__VI;
typedef union GDS_VMID0_SIZE__CI__VI           regGDS_VMID0_SIZE__CI__VI;
typedef union GDS_VMID10_BASE__CI__VI          regGDS_VMID10_BASE__CI__VI;
typedef union GDS_VMID10_SIZE__CI__VI          regGDS_VMID10_SIZE__CI__VI;
typedef union GDS_VMID11_BASE__CI__VI          regGDS_VMID11_BASE__CI__VI;
typedef union GDS_VMID11_SIZE__CI__VI          regGDS_VMID11_SIZE__CI__VI;
typedef union GDS_VMID12_BASE__CI__VI          regGDS_VMID12_BASE__CI__VI;
typedef union GDS_VMID12_SIZE__CI__VI          regGDS_VMID12_SIZE__CI__VI;
typedef union GDS_VMID13_BASE__CI__VI          regGDS_VMID13_BASE__CI__VI;
typedef union GDS_VMID13_SIZE__CI__VI          regGDS_VMID13_SIZE__CI__VI;
typedef union GDS_VMID14_BASE__CI__VI          regGDS_VMID14_BASE__CI__VI;
typedef union GDS_VMID14_SIZE__CI__VI          regGDS_VMID14_SIZE__CI__VI;
typedef union GDS_VMID15_BASE__CI__VI          regGDS_VMID15_BASE__CI__VI;
typedef union GDS_VMID15_SIZE__CI__VI          regGDS_VMID15_SIZE__CI__VI;
typedef union GDS_VMID1_BASE__CI__VI           regGDS_VMID1_BASE__CI__VI;
typedef union GDS_VMID1_SIZE__CI__VI           regGDS_VMID1_SIZE__CI__VI;
typedef union GDS_VMID2_BASE__CI__VI           regGDS_VMID2_BASE__CI__VI;
typedef union GDS_VMID2_SIZE__CI__VI           regGDS_VMID2_SIZE__CI__VI;
typedef union GDS_VMID3_BASE__CI__VI           regGDS_VMID3_BASE__CI__VI;
typedef union GDS_VMID3_SIZE__CI__VI           regGDS_VMID3_SIZE__CI__VI;
typedef union GDS_VMID4_BASE__CI__VI           regGDS_VMID4_BASE__CI__VI;
typedef union GDS_VMID4_SIZE__CI__VI           regGDS_VMID4_SIZE__CI__VI;
typedef union GDS_VMID5_BASE__CI__VI           regGDS_VMID5_BASE__CI__VI;
typedef union GDS_VMID5_SIZE__CI__VI           regGDS_VMID5_SIZE__CI__VI;
typedef union GDS_VMID6_BASE__CI__VI           regGDS_VMID6_BASE__CI__VI;
typedef union GDS_VMID6_SIZE__CI__VI           regGDS_VMID6_SIZE__CI__VI;
typedef union GDS_VMID7_BASE__CI__VI           regGDS_VMID7_BASE__CI__VI;
typedef union GDS_VMID7_SIZE__CI__VI           regGDS_VMID7_SIZE__CI__VI;
typedef union GDS_VMID8_BASE__CI__VI           regGDS_VMID8_BASE__CI__VI;
typedef union GDS_VMID8_SIZE__CI__VI           regGDS_VMID8_SIZE__CI__VI;
typedef union GDS_VMID9_BASE__CI__VI           regGDS_VMID9_BASE__CI__VI;
typedef union GDS_VMID9_SIZE__CI__VI           regGDS_VMID9_SIZE__CI__VI;
typedef union GDS_VM_PROTECTION_FAULT__CI__VI  regGDS_VM_PROTECTION_FAULT__CI__VI;
typedef union GDS_WRITE_COMPLETE               regGDS_WRITE_COMPLETE;
typedef union GDS_WR_ADDR                      regGDS_WR_ADDR;
typedef union GDS_WR_BURST_ADDR                regGDS_WR_BURST_ADDR;
typedef union GDS_WR_BURST_DATA                regGDS_WR_BURST_DATA;
typedef union GDS_WR_DATA                      regGDS_WR_DATA;
typedef union GENENB__SI__VI                   regGENENB__SI__VI;
typedef union GENERAL_PWRMGT__CI__VI           regGENERAL_PWRMGT__CI__VI;
typedef union GENERAL_PWRMGT__SI               regGENERAL_PWRMGT__SI;
typedef union GENERIC_I2C_CONTROL__SI__VI      regGENERIC_I2C_CONTROL__SI__VI;
typedef union GENERIC_I2C_DATA__SI__VI         regGENERIC_I2C_DATA__SI__VI;
typedef union GENERIC_I2C_INTERRUPT_CONTROL__SI__VI regGENERIC_I2C_INTERRUPT_CONTROL__SI__VI;
typedef union GENERIC_I2C_PIN_DEBUG__SI__VI    regGENERIC_I2C_PIN_DEBUG__SI__VI;
typedef union GENERIC_I2C_PIN_SELECTION__SI__VI regGENERIC_I2C_PIN_SELECTION__SI__VI;
typedef union GENERIC_I2C_SETUP__SI__VI        regGENERIC_I2C_SETUP__SI__VI;
typedef union GENERIC_I2C_SPEED__SI__VI        regGENERIC_I2C_SPEED__SI__VI;
typedef union GENERIC_I2C_STATUS__SI__VI       regGENERIC_I2C_STATUS__SI__VI;
typedef union GENERIC_I2C_TRANSACTION__SI__VI  regGENERIC_I2C_TRANSACTION__SI__VI;
typedef union GENFC_RD__SI__VI                 regGENFC_RD__SI__VI;
typedef union GENFC_WT__SI__VI                 regGENFC_WT__SI__VI;
typedef union GENMO_RD__SI__VI                 regGENMO_RD__SI__VI;
typedef union GENMO_WT__SI__VI                 regGENMO_WT__SI__VI;
typedef union GENS0__SI__VI                    regGENS0__SI__VI;
typedef union GENS1__SI__VI                    regGENS1__SI__VI;
typedef union GFX_COPY_STATE                   regGFX_COPY_STATE;
typedef union GFX_PIPE_CONTROL__CI__VI         regGFX_PIPE_CONTROL__CI__VI;
typedef union GFX_PIPE_PRIORITY__CI__VI        regGFX_PIPE_PRIORITY__CI__VI;
typedef union GLOBAL_CAPABILITIES__SI__VI      regGLOBAL_CAPABILITIES__SI__VI;
typedef union GLOBAL_CONTROL__SI__VI           regGLOBAL_CONTROL__SI__VI;
typedef union GLOBAL_STATUS__SI__VI            regGLOBAL_STATUS__SI__VI;
typedef union GMCON_DEBUG__CI                  regGMCON_DEBUG__CI;
typedef union GMCON_DEBUG__VI                  regGMCON_DEBUG__VI;
typedef union GMCON_MASK__CI__VI               regGMCON_MASK__CI__VI;
typedef union GMCON_MISC2__CI                  regGMCON_MISC2__CI;
typedef union GMCON_MISC2__VI                  regGMCON_MISC2__VI;
typedef union GMCON_MISC3__CI                  regGMCON_MISC3__CI;
typedef union GMCON_MISC3__VI                  regGMCON_MISC3__VI;
typedef union GMCON_MISC__CI__VI               regGMCON_MISC__CI__VI;
typedef union GMCON_PERF_MON_CNTL0__CI__VI     regGMCON_PERF_MON_CNTL0__CI__VI;
typedef union GMCON_PERF_MON_CNTL1__CI         regGMCON_PERF_MON_CNTL1__CI;
typedef union GMCON_PERF_MON_CNTL1__VI         regGMCON_PERF_MON_CNTL1__VI;
typedef union GMCON_PERF_MON_RSLT0__CI__VI     regGMCON_PERF_MON_RSLT0__CI__VI;
typedef union GMCON_PERF_MON_RSLT1__CI__VI     regGMCON_PERF_MON_RSLT1__CI__VI;
typedef union GMCON_PGFSM_CONFIG__CI__VI       regGMCON_PGFSM_CONFIG__CI__VI;
typedef union GMCON_PGFSM_READ__CI__VI         regGMCON_PGFSM_READ__CI__VI;
typedef union GMCON_PGFSM_WRITE__CI__VI        regGMCON_PGFSM_WRITE__CI__VI;
typedef union GMCON_RENG_EXECUTE__CI__VI       regGMCON_RENG_EXECUTE__CI__VI;
typedef union GMCON_RENG_RAM_DATA__CI__VI      regGMCON_RENG_RAM_DATA__CI__VI;
typedef union GMCON_RENG_RAM_INDEX__CI__VI     regGMCON_RENG_RAM_INDEX__CI__VI;
typedef union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI regGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__CI__VI;
typedef union GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI regGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__CI__VI;
typedef union GMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI regGMCON_STCTRL_REGISTER_SAVE_RANGE0__CI__VI;
typedef union GMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI regGMCON_STCTRL_REGISTER_SAVE_RANGE1__CI__VI;
typedef union GMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI regGMCON_STCTRL_REGISTER_SAVE_RANGE2__CI__VI;
typedef union GPIOPAD_A                        regGPIOPAD_A;
typedef union GPIOPAD_EN                       regGPIOPAD_EN;
typedef union GPIOPAD_EXTERN_TRIG_CNTL         regGPIOPAD_EXTERN_TRIG_CNTL;
typedef union GPIOPAD_INT_EN                   regGPIOPAD_INT_EN;
typedef union GPIOPAD_INT_POLARITY             regGPIOPAD_INT_POLARITY;
typedef union GPIOPAD_INT_STAT                 regGPIOPAD_INT_STAT;
typedef union GPIOPAD_INT_STAT_AK              regGPIOPAD_INT_STAT_AK;
typedef union GPIOPAD_INT_STAT_EN              regGPIOPAD_INT_STAT_EN;
typedef union GPIOPAD_INT_TYPE                 regGPIOPAD_INT_TYPE;
typedef union GPIOPAD_MASK                     regGPIOPAD_MASK;
typedef union GPIOPAD_PD_EN                    regGPIOPAD_PD_EN;
typedef union GPIOPAD_PINSTRAPS                regGPIOPAD_PINSTRAPS;
typedef union GPIOPAD_PU_EN                    regGPIOPAD_PU_EN;
typedef union GPIOPAD_RCVR_SEL                 regGPIOPAD_RCVR_SEL;
typedef union GPIOPAD_STRENGTH                 regGPIOPAD_STRENGTH;
typedef union GPIOPAD_SW_INT_STAT              regGPIOPAD_SW_INT_STAT;
typedef union GPIOPAD_Y                        regGPIOPAD_Y;
typedef union GPU_GARLIC_FLUSH_DONE__CI__VI    regGPU_GARLIC_FLUSH_DONE__CI__VI;
typedef union GPU_GARLIC_FLUSH_REQ__CI__VI     regGPU_GARLIC_FLUSH_REQ__CI__VI;
typedef union GPU_HDP_FLUSH_DONE__CI__VI       regGPU_HDP_FLUSH_DONE__CI__VI;
typedef union GPU_HDP_FLUSH_REQ__CI__VI        regGPU_HDP_FLUSH_REQ__CI__VI;
typedef union GRA00__SI__VI                    regGRA00__SI__VI;
typedef union GRA01__SI__VI                    regGRA01__SI__VI;
typedef union GRA02__SI__VI                    regGRA02__SI__VI;
typedef union GRA03__SI__VI                    regGRA03__SI__VI;
typedef union GRA04__SI__VI                    regGRA04__SI__VI;
typedef union GRA05__SI__VI                    regGRA05__SI__VI;
typedef union GRA06__SI__VI                    regGRA06__SI__VI;
typedef union GRA07__SI__VI                    regGRA07__SI__VI;
typedef union GRA08__SI__VI                    regGRA08__SI__VI;
typedef union GRBM_CAM_DATA                    regGRBM_CAM_DATA;
typedef union GRBM_CAM_INDEX                   regGRBM_CAM_INDEX;
typedef union GRBM_CNTL                        regGRBM_CNTL;
typedef union GRBM_DEBUG                       regGRBM_DEBUG;
typedef union GRBM_DEBUG_CNTL                  regGRBM_DEBUG_CNTL;
typedef union GRBM_DEBUG_DATA                  regGRBM_DEBUG_DATA;
typedef union GRBM_DEBUG_SNAPSHOT__CI__VI      regGRBM_DEBUG_SNAPSHOT__CI__VI;
typedef union GRBM_DEBUG_SNAPSHOT__SI          regGRBM_DEBUG_SNAPSHOT__SI;
typedef union GRBM_GFX_CLKEN_CNTL              regGRBM_GFX_CLKEN_CNTL;
typedef union GRBM_GFX_INDEX                   regGRBM_GFX_INDEX;
typedef union GRBM_INT_CNTL                    regGRBM_INT_CNTL;
typedef union GRBM_NOWHERE                     regGRBM_NOWHERE;
typedef union GRBM_PERFCOUNTER0_HI             regGRBM_PERFCOUNTER0_HI;
typedef union GRBM_PERFCOUNTER0_LO             regGRBM_PERFCOUNTER0_LO;
typedef union GRBM_PERFCOUNTER0_SELECT         regGRBM_PERFCOUNTER0_SELECT;
typedef union GRBM_PERFCOUNTER1_HI             regGRBM_PERFCOUNTER1_HI;
typedef union GRBM_PERFCOUNTER1_LO             regGRBM_PERFCOUNTER1_LO;
typedef union GRBM_PERFCOUNTER1_SELECT         regGRBM_PERFCOUNTER1_SELECT;
typedef union GRBM_PWR_CNTL__SI__CI            regGRBM_PWR_CNTL__SI__CI;
typedef union GRBM_PWR_CNTL__VI                regGRBM_PWR_CNTL__VI;
typedef union GRBM_READ_ERROR2__CI__VI         regGRBM_READ_ERROR2__CI__VI;
typedef union GRBM_READ_ERROR__CI__VI          regGRBM_READ_ERROR__CI__VI;
typedef union GRBM_READ_ERROR__SI              regGRBM_READ_ERROR__SI;
typedef union GRBM_SCRATCH_REG0                regGRBM_SCRATCH_REG0;
typedef union GRBM_SCRATCH_REG1                regGRBM_SCRATCH_REG1;
typedef union GRBM_SCRATCH_REG2                regGRBM_SCRATCH_REG2;
typedef union GRBM_SCRATCH_REG3                regGRBM_SCRATCH_REG3;
typedef union GRBM_SCRATCH_REG4                regGRBM_SCRATCH_REG4;
typedef union GRBM_SCRATCH_REG5                regGRBM_SCRATCH_REG5;
typedef union GRBM_SCRATCH_REG6                regGRBM_SCRATCH_REG6;
typedef union GRBM_SCRATCH_REG7                regGRBM_SCRATCH_REG7;
typedef union GRBM_SE0_PERFCOUNTER_HI          regGRBM_SE0_PERFCOUNTER_HI;
typedef union GRBM_SE0_PERFCOUNTER_LO          regGRBM_SE0_PERFCOUNTER_LO;
typedef union GRBM_SE0_PERFCOUNTER_SELECT      regGRBM_SE0_PERFCOUNTER_SELECT;
typedef union GRBM_SE1_PERFCOUNTER_HI          regGRBM_SE1_PERFCOUNTER_HI;
typedef union GRBM_SE1_PERFCOUNTER_LO          regGRBM_SE1_PERFCOUNTER_LO;
typedef union GRBM_SE1_PERFCOUNTER_SELECT      regGRBM_SE1_PERFCOUNTER_SELECT;
typedef union GRBM_SE2_PERFCOUNTER_HI__CI__VI  regGRBM_SE2_PERFCOUNTER_HI__CI__VI;
typedef union GRBM_SE2_PERFCOUNTER_LO__CI__VI  regGRBM_SE2_PERFCOUNTER_LO__CI__VI;
typedef union GRBM_SE2_PERFCOUNTER_SELECT__CI__VI regGRBM_SE2_PERFCOUNTER_SELECT__CI__VI;
typedef union GRBM_SE3_PERFCOUNTER_HI__CI__VI  regGRBM_SE3_PERFCOUNTER_HI__CI__VI;
typedef union GRBM_SE3_PERFCOUNTER_LO__CI__VI  regGRBM_SE3_PERFCOUNTER_LO__CI__VI;
typedef union GRBM_SE3_PERFCOUNTER_SELECT__CI__VI regGRBM_SE3_PERFCOUNTER_SELECT__CI__VI;
typedef union GRBM_SKEW_CNTL                   regGRBM_SKEW_CNTL;
typedef union GRBM_SOFT_RESET                  regGRBM_SOFT_RESET;
typedef union GRBM_STATUS2__CI__VI             regGRBM_STATUS2__CI__VI;
typedef union GRBM_STATUS2__SI                 regGRBM_STATUS2__SI;
typedef union GRBM_STATUS_SE0                  regGRBM_STATUS_SE0;
typedef union GRBM_STATUS_SE1                  regGRBM_STATUS_SE1;
typedef union GRBM_STATUS_SE2__CI__VI          regGRBM_STATUS_SE2__CI__VI;
typedef union GRBM_STATUS_SE3__CI__VI          regGRBM_STATUS_SE3__CI__VI;
typedef union GRBM_STATUS__CI__VI              regGRBM_STATUS__CI__VI;
typedef union GRBM_STATUS__SI                  regGRBM_STATUS__SI;
typedef union GRBM_WAIT_IDLE_CLOCKS            regGRBM_WAIT_IDLE_CLOCKS;
typedef union GRPH8_DATA__SI__VI               regGRPH8_DATA__SI__VI;
typedef union GRPH8_IDX__SI__VI                regGRPH8_IDX__SI__VI;
typedef union GRPH_COMPRESS_PITCH__SI__VI      regGRPH_COMPRESS_PITCH__SI__VI;
typedef union GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI regGRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SI__VI;
typedef union GRPH_COMPRESS_SURFACE_ADDRESS__SI__VI regGRPH_COMPRESS_SURFACE_ADDRESS__SI__VI;
typedef union GRPH_CONTROL                     regGRPH_CONTROL;
typedef union GRPH_DFQ_CONTROL__SI__VI         regGRPH_DFQ_CONTROL__SI__VI;
typedef union GRPH_DFQ_STATUS__SI__VI          regGRPH_DFQ_STATUS__SI__VI;
typedef union GRPH_ENABLE__SI__VI              regGRPH_ENABLE__SI__VI;
typedef union GRPH_FLIP_CONTROL                regGRPH_FLIP_CONTROL;
typedef union GRPH_INTERRUPT_CONTROL__SI__VI   regGRPH_INTERRUPT_CONTROL__SI__VI;
typedef union GRPH_INTERRUPT_STATUS__SI__VI    regGRPH_INTERRUPT_STATUS__SI__VI;
typedef union GRPH_LUT_10BIT_BYPASS__SI__VI    regGRPH_LUT_10BIT_BYPASS__SI__VI;
typedef union GRPH_PITCH                       regGRPH_PITCH;
typedef union GRPH_PRIMARY_SURFACE_ADDRESS     regGRPH_PRIMARY_SURFACE_ADDRESS;
typedef union GRPH_PRIMARY_SURFACE_ADDRESS_HIGH regGRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
typedef union GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI regGRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SI__VI;
typedef union GRPH_SECONDARY_SURFACE_ADDRESS__SI__VI regGRPH_SECONDARY_SURFACE_ADDRESS__SI__VI;
typedef union GRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI regGRPH_SURFACE_ADDRESS_HIGH_INUSE__SI__VI;
typedef union GRPH_SURFACE_ADDRESS_INUSE__SI__VI regGRPH_SURFACE_ADDRESS_INUSE__SI__VI;
typedef union GRPH_SURFACE_OFFSET_X__SI__VI    regGRPH_SURFACE_OFFSET_X__SI__VI;
typedef union GRPH_SURFACE_OFFSET_Y__SI__VI    regGRPH_SURFACE_OFFSET_Y__SI__VI;
typedef union GRPH_SWAP_CNTL__SI__VI           regGRPH_SWAP_CNTL__SI__VI;
typedef union GRPH_UPDATE                      regGRPH_UPDATE;
typedef union GRPH_X_END__SI__VI               regGRPH_X_END__SI__VI;
typedef union GRPH_X_START__SI__VI             regGRPH_X_START__SI__VI;
typedef union GRPH_Y_END__SI__VI               regGRPH_Y_END__SI__VI;
typedef union GRPH_Y_START__SI__VI             regGRPH_Y_START__SI__VI;
typedef union HDMI_ACR_32_0__SI__VI            regHDMI_ACR_32_0__SI__VI;
typedef union HDMI_ACR_32_1__SI__VI            regHDMI_ACR_32_1__SI__VI;
typedef union HDMI_ACR_44_0__SI__VI            regHDMI_ACR_44_0__SI__VI;
typedef union HDMI_ACR_44_1__SI__VI            regHDMI_ACR_44_1__SI__VI;
typedef union HDMI_ACR_48_0__SI__VI            regHDMI_ACR_48_0__SI__VI;
typedef union HDMI_ACR_48_1__SI__VI            regHDMI_ACR_48_1__SI__VI;
typedef union HDMI_ACR_PACKET_CONTROL__SI__VI  regHDMI_ACR_PACKET_CONTROL__SI__VI;
typedef union HDMI_ACR_STATUS_0__SI__VI        regHDMI_ACR_STATUS_0__SI__VI;
typedef union HDMI_ACR_STATUS_1__SI__VI        regHDMI_ACR_STATUS_1__SI__VI;
typedef union HDMI_AUDIO_PACKET_CONTROL__SI__VI regHDMI_AUDIO_PACKET_CONTROL__SI__VI;
typedef union HDMI_CONTROL__SI__VI             regHDMI_CONTROL__SI__VI;
typedef union HDMI_GC__SI__VI                  regHDMI_GC__SI__VI;
typedef union HDMI_GENERIC_PACKET_CONTROL__SI  regHDMI_GENERIC_PACKET_CONTROL__SI;
typedef union HDMI_INFOFRAME_CONTROL0__SI__VI  regHDMI_INFOFRAME_CONTROL0__SI__VI;
typedef union HDMI_INFOFRAME_CONTROL1__SI__VI  regHDMI_INFOFRAME_CONTROL1__SI__VI;
typedef union HDMI_STATUS__SI__VI              regHDMI_STATUS__SI__VI;
typedef union HDMI_VBI_PACKET_CONTROL__SI__VI  regHDMI_VBI_PACKET_CONTROL__SI__VI;
typedef union HDP_DEBUG0                       regHDP_DEBUG0;
typedef union HDP_DEBUG1                       regHDP_DEBUG1;
typedef union HDP_HOST_PATH_CNTL               regHDP_HOST_PATH_CNTL;
typedef union HDP_LAST_SURFACE_HIT             regHDP_LAST_SURFACE_HIT;
typedef union HDP_MEM_COHERENCY_FLUSH_CNTL     regHDP_MEM_COHERENCY_FLUSH_CNTL;
typedef union HDP_NONSURFACE_BASE              regHDP_NONSURFACE_BASE;
typedef union HDP_NONSURFACE_INFO              regHDP_NONSURFACE_INFO;
typedef union HDP_NONSURFACE_SIZE              regHDP_NONSURFACE_SIZE;
typedef union HDP_NONSURF_FLAGS                regHDP_NONSURF_FLAGS;
typedef union HDP_NONSURF_FLAGS_CLR            regHDP_NONSURF_FLAGS_CLR;
typedef union HDP_OUTSTANDING_REQ              regHDP_OUTSTANDING_REQ;
typedef union HDP_REG_COHERENCY_FLUSH_CNTL     regHDP_REG_COHERENCY_FLUSH_CNTL;
typedef union HDP_SC_MULTI_CHIP_CNTL           regHDP_SC_MULTI_CHIP_CNTL;
typedef union HDP_SW_SEMAPHORE                 regHDP_SW_SEMAPHORE;
typedef union HDP_TILING_CONFIG                regHDP_TILING_CONFIG;
typedef union HDP_XDP_BUSY_STS                 regHDP_XDP_BUSY_STS;
typedef union HDP_XDP_CGTT_BLK_CTRL            regHDP_XDP_CGTT_BLK_CTRL;
typedef union HDP_XDP_CHKN                     regHDP_XDP_CHKN;
typedef union HDP_XDP_D2H_BAR_UPDATE           regHDP_XDP_D2H_BAR_UPDATE;
typedef union HDP_XDP_D2H_FLUSH                regHDP_XDP_D2H_FLUSH;
typedef union HDP_XDP_D2H_RSVD_10              regHDP_XDP_D2H_RSVD_10;
typedef union HDP_XDP_D2H_RSVD_11              regHDP_XDP_D2H_RSVD_11;
typedef union HDP_XDP_D2H_RSVD_12              regHDP_XDP_D2H_RSVD_12;
typedef union HDP_XDP_D2H_RSVD_13              regHDP_XDP_D2H_RSVD_13;
typedef union HDP_XDP_D2H_RSVD_14              regHDP_XDP_D2H_RSVD_14;
typedef union HDP_XDP_D2H_RSVD_15              regHDP_XDP_D2H_RSVD_15;
typedef union HDP_XDP_D2H_RSVD_16              regHDP_XDP_D2H_RSVD_16;
typedef union HDP_XDP_D2H_RSVD_17              regHDP_XDP_D2H_RSVD_17;
typedef union HDP_XDP_D2H_RSVD_18              regHDP_XDP_D2H_RSVD_18;
typedef union HDP_XDP_D2H_RSVD_19              regHDP_XDP_D2H_RSVD_19;
typedef union HDP_XDP_D2H_RSVD_20              regHDP_XDP_D2H_RSVD_20;
typedef union HDP_XDP_D2H_RSVD_21              regHDP_XDP_D2H_RSVD_21;
typedef union HDP_XDP_D2H_RSVD_22              regHDP_XDP_D2H_RSVD_22;
typedef union HDP_XDP_D2H_RSVD_23              regHDP_XDP_D2H_RSVD_23;
typedef union HDP_XDP_D2H_RSVD_24              regHDP_XDP_D2H_RSVD_24;
typedef union HDP_XDP_D2H_RSVD_25              regHDP_XDP_D2H_RSVD_25;
typedef union HDP_XDP_D2H_RSVD_26              regHDP_XDP_D2H_RSVD_26;
typedef union HDP_XDP_D2H_RSVD_27              regHDP_XDP_D2H_RSVD_27;
typedef union HDP_XDP_D2H_RSVD_28              regHDP_XDP_D2H_RSVD_28;
typedef union HDP_XDP_D2H_RSVD_29              regHDP_XDP_D2H_RSVD_29;
typedef union HDP_XDP_D2H_RSVD_3               regHDP_XDP_D2H_RSVD_3;
typedef union HDP_XDP_D2H_RSVD_30              regHDP_XDP_D2H_RSVD_30;
typedef union HDP_XDP_D2H_RSVD_31              regHDP_XDP_D2H_RSVD_31;
typedef union HDP_XDP_D2H_RSVD_32              regHDP_XDP_D2H_RSVD_32;
typedef union HDP_XDP_D2H_RSVD_33              regHDP_XDP_D2H_RSVD_33;
typedef union HDP_XDP_D2H_RSVD_34              regHDP_XDP_D2H_RSVD_34;
typedef union HDP_XDP_D2H_RSVD_4               regHDP_XDP_D2H_RSVD_4;
typedef union HDP_XDP_D2H_RSVD_5               regHDP_XDP_D2H_RSVD_5;
typedef union HDP_XDP_D2H_RSVD_6               regHDP_XDP_D2H_RSVD_6;
typedef union HDP_XDP_D2H_RSVD_7               regHDP_XDP_D2H_RSVD_7;
typedef union HDP_XDP_D2H_RSVD_8               regHDP_XDP_D2H_RSVD_8;
typedef union HDP_XDP_D2H_RSVD_9               regHDP_XDP_D2H_RSVD_9;
typedef union HDP_XDP_DBG_ADDR                 regHDP_XDP_DBG_ADDR;
typedef union HDP_XDP_DBG_DATA                 regHDP_XDP_DBG_DATA;
typedef union HDP_XDP_DBG_MASK                 regHDP_XDP_DBG_MASK;
typedef union HDP_XDP_DIRECT2HDP_FIRST         regHDP_XDP_DIRECT2HDP_FIRST;
typedef union HDP_XDP_DIRECT2HDP_LAST          regHDP_XDP_DIRECT2HDP_LAST;
typedef union HDP_XDP_FLUSH_ARMED_STS          regHDP_XDP_FLUSH_ARMED_STS;
typedef union HDP_XDP_FLUSH_CNTR0_STS          regHDP_XDP_FLUSH_CNTR0_STS;
typedef union HDP_XDP_HDP_IPH_CFG              regHDP_XDP_HDP_IPH_CFG;
typedef union HDP_XDP_HDP_MBX_MC_CFG           regHDP_XDP_HDP_MBX_MC_CFG;
typedef union HDP_XDP_HDP_MC_CFG               regHDP_XDP_HDP_MC_CFG;
typedef union HDP_XDP_HST_CFG                  regHDP_XDP_HST_CFG;
typedef union HDP_XDP_P2P_BAR0                 regHDP_XDP_P2P_BAR0;
typedef union HDP_XDP_P2P_BAR1                 regHDP_XDP_P2P_BAR1;
typedef union HDP_XDP_P2P_BAR2                 regHDP_XDP_P2P_BAR2;
typedef union HDP_XDP_P2P_BAR3                 regHDP_XDP_P2P_BAR3;
typedef union HDP_XDP_P2P_BAR4                 regHDP_XDP_P2P_BAR4;
typedef union HDP_XDP_P2P_BAR5                 regHDP_XDP_P2P_BAR5;
typedef union HDP_XDP_P2P_BAR6                 regHDP_XDP_P2P_BAR6;
typedef union HDP_XDP_P2P_BAR7                 regHDP_XDP_P2P_BAR7;
typedef union HDP_XDP_P2P_BAR_CFG              regHDP_XDP_P2P_BAR_CFG;
typedef union HDP_XDP_P2P_MBX_ADDR0            regHDP_XDP_P2P_MBX_ADDR0;
typedef union HDP_XDP_P2P_MBX_ADDR1            regHDP_XDP_P2P_MBX_ADDR1;
typedef union HDP_XDP_P2P_MBX_ADDR2            regHDP_XDP_P2P_MBX_ADDR2;
typedef union HDP_XDP_P2P_MBX_ADDR3            regHDP_XDP_P2P_MBX_ADDR3;
typedef union HDP_XDP_P2P_MBX_ADDR4            regHDP_XDP_P2P_MBX_ADDR4;
typedef union HDP_XDP_P2P_MBX_ADDR5            regHDP_XDP_P2P_MBX_ADDR5;
typedef union HDP_XDP_P2P_MBX_ADDR6            regHDP_XDP_P2P_MBX_ADDR6;
typedef union HDP_XDP_P2P_MBX_OFFSET           regHDP_XDP_P2P_MBX_OFFSET;
typedef union HDP_XDP_SID_CFG                  regHDP_XDP_SID_CFG;
typedef union HDP_XDP_SRBM_CFG                 regHDP_XDP_SRBM_CFG;
typedef union HDP_XDP_STICKY                   regHDP_XDP_STICKY;
typedef union HEADER                           regHEADER;
typedef union HFS_SEED0                        regHFS_SEED0;
typedef union HFS_SEED1                        regHFS_SEED1;
typedef union HFS_SEED2                        regHFS_SEED2;
typedef union HFS_SEED3                        regHFS_SEED3;
typedef union HOST_BUSNUM                      regHOST_BUSNUM;
typedef union HW_DEBUG                         regHW_DEBUG;
typedef union IA_CNTL_STATUS                   regIA_CNTL_STATUS;
typedef union IA_DEBUG_CNTL                    regIA_DEBUG_CNTL;
typedef union IA_DEBUG_DATA                    regIA_DEBUG_DATA;
typedef union IA_DEBUG_REG0__CI__VI            regIA_DEBUG_REG0__CI__VI;
typedef union IA_DEBUG_REG0__SI                regIA_DEBUG_REG0__SI;
typedef union IA_DEBUG_REG1__CI__VI            regIA_DEBUG_REG1__CI__VI;
typedef union IA_DEBUG_REG1__SI                regIA_DEBUG_REG1__SI;
typedef union IA_DEBUG_REG2__CI__VI            regIA_DEBUG_REG2__CI__VI;
typedef union IA_DEBUG_REG2__SI                regIA_DEBUG_REG2__SI;
typedef union IA_DEBUG_REG3__CI__VI            regIA_DEBUG_REG3__CI__VI;
typedef union IA_DEBUG_REG3__SI                regIA_DEBUG_REG3__SI;
typedef union IA_DEBUG_REG4__CI__VI            regIA_DEBUG_REG4__CI__VI;
typedef union IA_DEBUG_REG4__SI                regIA_DEBUG_REG4__SI;
typedef union IA_DEBUG_REG5__CI__VI            regIA_DEBUG_REG5__CI__VI;
typedef union IA_DEBUG_REG5__SI                regIA_DEBUG_REG5__SI;
typedef union IA_DEBUG_REG6__CI__VI            regIA_DEBUG_REG6__CI__VI;
typedef union IA_DEBUG_REG6__SI                regIA_DEBUG_REG6__SI;
typedef union IA_DEBUG_REG7__CI__VI            regIA_DEBUG_REG7__CI__VI;
typedef union IA_DEBUG_REG7__SI                regIA_DEBUG_REG7__SI;
typedef union IA_DEBUG_REG8                    regIA_DEBUG_REG8;
typedef union IA_DEBUG_REG9__CI__VI            regIA_DEBUG_REG9__CI__VI;
typedef union IA_DEBUG_REG9__SI                regIA_DEBUG_REG9__SI;
typedef union IA_ENHANCE                       regIA_ENHANCE;
typedef union IA_MULTI_VGT_PARAM               regIA_MULTI_VGT_PARAM;
typedef union IA_PERFCOUNTER0_HI               regIA_PERFCOUNTER0_HI;
typedef union IA_PERFCOUNTER0_LO               regIA_PERFCOUNTER0_LO;
typedef union IA_PERFCOUNTER0_SELECT1__CI__VI  regIA_PERFCOUNTER0_SELECT1__CI__VI;
typedef union IA_PERFCOUNTER0_SELECT__CI__VI   regIA_PERFCOUNTER0_SELECT__CI__VI;
typedef union IA_PERFCOUNTER0_SELECT__SI       regIA_PERFCOUNTER0_SELECT__SI;
typedef union IA_PERFCOUNTER1_HI               regIA_PERFCOUNTER1_HI;
typedef union IA_PERFCOUNTER1_LO               regIA_PERFCOUNTER1_LO;
typedef union IA_PERFCOUNTER1_SELECT           regIA_PERFCOUNTER1_SELECT;
typedef union IA_PERFCOUNTER2_HI               regIA_PERFCOUNTER2_HI;
typedef union IA_PERFCOUNTER2_LO               regIA_PERFCOUNTER2_LO;
typedef union IA_PERFCOUNTER2_SELECT           regIA_PERFCOUNTER2_SELECT;
typedef union IA_PERFCOUNTER3_HI               regIA_PERFCOUNTER3_HI;
typedef union IA_PERFCOUNTER3_LO               regIA_PERFCOUNTER3_LO;
typedef union IA_PERFCOUNTER3_SELECT           regIA_PERFCOUNTER3_SELECT;
typedef union IA_VMID_OVERRIDE__SI__CI         regIA_VMID_OVERRIDE__SI__CI;
typedef union IDDCCIF02_DBG_DCCIF_C__SI__VI    regIDDCCIF02_DBG_DCCIF_C__SI__VI;
typedef union IDDCCIF04_DBG_DCCIF_E__SI__VI    regIDDCCIF04_DBG_DCCIF_E__SI__VI;
typedef union IDDCCIF05_DBG_DCCIF_F__SI__VI    regIDDCCIF05_DBG_DCCIF_F__SI__VI;
typedef union IH_ADVFAULT_CNTL__SI__CI         regIH_ADVFAULT_CNTL__SI__CI;
typedef union IH_CNTL                          regIH_CNTL;
typedef union IH_LEVEL_STATUS                  regIH_LEVEL_STATUS;
typedef union IH_PERFCOUNTER0_RESULT__CI__VI   regIH_PERFCOUNTER0_RESULT__CI__VI;
typedef union IH_PERFCOUNTER1_RESULT__CI__VI   regIH_PERFCOUNTER1_RESULT__CI__VI;
typedef union IH_PERFMON_CNTL__CI__VI          regIH_PERFMON_CNTL__CI__VI;
typedef union IH_RB_BASE                       regIH_RB_BASE;
typedef union IH_RB_CNTL                       regIH_RB_CNTL;
typedef union IH_RB_RPTR                       regIH_RB_RPTR;
typedef union IH_RB_WPTR                       regIH_RB_WPTR;
typedef union IH_RB_WPTR_ADDR_HI               regIH_RB_WPTR_ADDR_HI;
typedef union IH_RB_WPTR_ADDR_LO               regIH_RB_WPTR_ADDR_LO;
typedef union IH_STATUS                        regIH_STATUS;
typedef union IH_VMID_0_LUT__CI__VI            regIH_VMID_0_LUT__CI__VI;
typedef union IH_VMID_10_LUT__CI__VI           regIH_VMID_10_LUT__CI__VI;
typedef union IH_VMID_11_LUT__CI__VI           regIH_VMID_11_LUT__CI__VI;
typedef union IH_VMID_12_LUT__CI__VI           regIH_VMID_12_LUT__CI__VI;
typedef union IH_VMID_13_LUT__CI__VI           regIH_VMID_13_LUT__CI__VI;
typedef union IH_VMID_14_LUT__CI__VI           regIH_VMID_14_LUT__CI__VI;
typedef union IH_VMID_15_LUT__CI__VI           regIH_VMID_15_LUT__CI__VI;
typedef union IH_VMID_1_LUT__CI__VI            regIH_VMID_1_LUT__CI__VI;
typedef union IH_VMID_2_LUT__CI__VI            regIH_VMID_2_LUT__CI__VI;
typedef union IH_VMID_3_LUT__CI__VI            regIH_VMID_3_LUT__CI__VI;
typedef union IH_VMID_4_LUT__CI__VI            regIH_VMID_4_LUT__CI__VI;
typedef union IH_VMID_5_LUT__CI__VI            regIH_VMID_5_LUT__CI__VI;
typedef union IH_VMID_6_LUT__CI__VI            regIH_VMID_6_LUT__CI__VI;
typedef union IH_VMID_7_LUT__CI__VI            regIH_VMID_7_LUT__CI__VI;
typedef union IH_VMID_8_LUT__CI__VI            regIH_VMID_8_LUT__CI__VI;
typedef union IH_VMID_9_LUT__CI__VI            regIH_VMID_9_LUT__CI__VI;
typedef union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__SI__VI regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__SI__VI;
typedef union IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__SI__VI regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__SI__VI;
typedef union IMMEDIATE_COMMAND_OUTPUT_INTERFACE__SI__VI regIMMEDIATE_COMMAND_OUTPUT_INTERFACE__SI__VI;
typedef union IMMEDIATE_COMMAND_STATUS__SI__VI regIMMEDIATE_COMMAND_STATUS__SI__VI;
typedef union IMMEDIATE_RESPONSE_INPUT_INTERFACE__SI__VI regIMMEDIATE_RESPONSE_INPUT_INTERFACE__SI__VI;
typedef union IMPCTL_RESET__CI__VI             regIMPCTL_RESET__CI__VI;
typedef union INPUT_PAYLOAD_CAPABILITY__SI__VI regINPUT_PAYLOAD_CAPABILITY__SI__VI;
typedef union INTERRUPT_CNTL                   regINTERRUPT_CNTL;
typedef union INTERRUPT_CNTL2                  regINTERRUPT_CNTL2;
typedef union INTERRUPT_CONTROL__SI            regINTERRUPT_CONTROL__SI;
typedef union INTERRUPT_CONTROL__VI            regINTERRUPT_CONTROL__VI;
typedef union INTERRUPT_LINE                   regINTERRUPT_LINE;
typedef union INTERRUPT_PIN                    regINTERRUPT_PIN;
typedef union INTERRUPT_STATUS__SI             regINTERRUPT_STATUS__SI;
typedef union INTERRUPT_STATUS__VI             regINTERRUPT_STATUS__VI;
typedef union KEFUSE0                          regKEFUSE0;
typedef union KEFUSE1                          regKEFUSE1;
typedef union KEFUSE2                          regKEFUSE2;
typedef union KEFUSE3                          regKEFUSE3;
typedef union KHFS0                            regKHFS0;
typedef union KHFS1                            regKHFS1;
typedef union KHFS2                            regKHFS2;
typedef union KHFS3                            regKHFS3;
typedef union KSESSION0                        regKSESSION0;
typedef union KSESSION1                        regKSESSION1;
typedef union KSESSION2                        regKSESSION2;
typedef union KSESSION3                        regKSESSION3;
typedef union KSIG0                            regKSIG0;
typedef union KSIG1                            regKSIG1;
typedef union KSIG2                            regKSIG2;
typedef union KSIG3                            regKSIG3;
typedef union LATENCY                          regLATENCY;
typedef union LB_DEBUG__SI__VI                 regLB_DEBUG__SI__VI;
typedef union LB_SYNC_RESET_SEL__SI__VI        regLB_SYNC_RESET_SEL__SI__VI;
typedef union LB_TEST_DEBUG_DATA__SI__VI       regLB_TEST_DEBUG_DATA__SI__VI;
typedef union LB_TEST_DEBUG_INDEX__SI__VI      regLB_TEST_DEBUG_INDEX__SI__VI;
typedef union LCAC_CPL_CNTL__CI__VI            regLCAC_CPL_CNTL__CI__VI;
typedef union LCAC_CPL_OVR_SEL__CI__VI         regLCAC_CPL_OVR_SEL__CI__VI;
typedef union LCAC_CPL_OVR_VAL__CI__VI         regLCAC_CPL_OVR_VAL__CI__VI;
typedef union LCAC_MC0_CNTL                    regLCAC_MC0_CNTL;
typedef union LCAC_MC0_OVR_SEL                 regLCAC_MC0_OVR_SEL;
typedef union LCAC_MC0_OVR_VAL                 regLCAC_MC0_OVR_VAL;
typedef union LCAC_MC1_CNTL                    regLCAC_MC1_CNTL;
typedef union LCAC_MC1_OVR_SEL                 regLCAC_MC1_OVR_SEL;
typedef union LCAC_MC1_OVR_VAL                 regLCAC_MC1_OVR_VAL;
typedef union LCAC_MC2_CNTL                    regLCAC_MC2_CNTL;
typedef union LCAC_MC2_OVR_SEL                 regLCAC_MC2_OVR_SEL;
typedef union LCAC_MC2_OVR_VAL                 regLCAC_MC2_OVR_VAL;
typedef union LCAC_MC3_CNTL                    regLCAC_MC3_CNTL;
typedef union LCAC_MC3_OVR_SEL                 regLCAC_MC3_OVR_SEL;
typedef union LCAC_MC3_OVR_VAL                 regLCAC_MC3_OVR_VAL;
typedef union LCAC_MC4_CNTL__SI__VI            regLCAC_MC4_CNTL__SI__VI;
typedef union LCAC_MC4_OVR_SEL__SI__VI         regLCAC_MC4_OVR_SEL__SI__VI;
typedef union LCAC_MC4_OVR_VAL__SI__VI         regLCAC_MC4_OVR_VAL__SI__VI;
typedef union LCAC_MC5_CNTL__SI__VI            regLCAC_MC5_CNTL__SI__VI;
typedef union LCAC_MC5_OVR_SEL__SI__VI         regLCAC_MC5_OVR_SEL__SI__VI;
typedef union LCAC_MC5_OVR_VAL__SI__VI         regLCAC_MC5_OVR_VAL__SI__VI;
typedef union LCAC_SX0_CNTL__CI                regLCAC_SX0_CNTL__CI;
typedef union LCAC_SX0_OVR_SEL__CI             regLCAC_SX0_OVR_SEL__CI;
typedef union LCAC_SX0_OVR_VAL__CI             regLCAC_SX0_OVR_VAL__CI;
typedef union LCLK_DEEP_SLEEP_CNTL2__CI__VI    regLCLK_DEEP_SLEEP_CNTL2__CI__VI;
typedef union LCLK_DEEP_SLEEP_CNTL__CI__VI     regLCLK_DEEP_SLEEP_CNTL__CI__VI;
typedef union LINK_CAP                         regLINK_CAP;
typedef union LINK_CAP2__CI__VI                regLINK_CAP2__CI__VI;
typedef union LINK_CAP2__SI                    regLINK_CAP2__SI;
typedef union LINK_CNTL                        regLINK_CNTL;
typedef union LINK_CNTL2                       regLINK_CNTL2;
typedef union LINK_STATUS                      regLINK_STATUS;
typedef union LINK_STATUS2                     regLINK_STATUS2;
typedef union LNCNT_CONTROL__CI                regLNCNT_CONTROL__CI;
typedef union LNCNT_CONTROL__VI                regLNCNT_CONTROL__VI;
typedef union LVDS_DATA_CNTL__SI__VI           regLVDS_DATA_CNTL__SI__VI;
typedef union LVTMA_PWRSEQ_CNTL__SI__VI        regLVTMA_PWRSEQ_CNTL__SI__VI;
typedef union LVTMA_PWRSEQ_DELAY1__SI__VI      regLVTMA_PWRSEQ_DELAY1__SI__VI;
typedef union LVTMA_PWRSEQ_DELAY2__SI__VI      regLVTMA_PWRSEQ_DELAY2__SI__VI;
typedef union LVTMA_PWRSEQ_REF_DIV__SI__VI     regLVTMA_PWRSEQ_REF_DIV__SI__VI;
typedef union LVTMA_PWRSEQ_STATE__SI__VI       regLVTMA_PWRSEQ_STATE__SI__VI;
typedef union LX0                              regLX0;
typedef union LX1                              regLX1;
typedef union LX2                              regLX2;
typedef union LX3                              regLX3;
typedef union MAJOR_VERSION__SI__VI            regMAJOR_VERSION__SI__VI;
typedef union MASTER_COMM_CMD_REG__SI__VI      regMASTER_COMM_CMD_REG__SI__VI;
typedef union MASTER_COMM_CNTL_REG__SI__VI     regMASTER_COMM_CNTL_REG__SI__VI;
typedef union MASTER_COMM_DATA_REG1__SI__VI    regMASTER_COMM_DATA_REG1__SI__VI;
typedef union MASTER_COMM_DATA_REG2__SI__VI    regMASTER_COMM_DATA_REG2__SI__VI;
typedef union MASTER_COMM_DATA_REG3__SI__VI    regMASTER_COMM_DATA_REG3__SI__VI;
typedef union MASTER_CREDIT_CNTL               regMASTER_CREDIT_CNTL;
typedef union MASTER_UPDATE_LOCK__SI__VI       regMASTER_UPDATE_LOCK__SI__VI;
typedef union MASTER_UPDATE_MODE               regMASTER_UPDATE_MODE;
typedef union MAX_LATENCY                      regMAX_LATENCY;
typedef union MCIF_CONTROL__SI__VI             regMCIF_CONTROL__SI__VI;
typedef union MCIF_TEST_DEBUG_DATA__SI__VI     regMCIF_TEST_DEBUG_DATA__SI__VI;
typedef union MCIF_TEST_DEBUG_INDEX__SI__VI    regMCIF_TEST_DEBUG_INDEX__SI__VI;
typedef union MCIF_WRITE_COMBINE_CONTROL__SI__VI regMCIF_WRITE_COMBINE_CONTROL__SI__VI;
typedef union MCLK_PWRMGT_CNTL__SI__CI         regMCLK_PWRMGT_CNTL__SI__CI;
typedef union MC_ARB_ADDR_HASH                 regMC_ARB_ADDR_HASH;
typedef union MC_ARB_ADDR_SWIZ0__CI__VI        regMC_ARB_ADDR_SWIZ0__CI__VI;
typedef union MC_ARB_ADDR_SWIZ1__CI__VI        regMC_ARB_ADDR_SWIZ1__CI__VI;
typedef union MC_ARB_AGE_CNTL__CI__VI          regMC_ARB_AGE_CNTL__CI__VI;
typedef union MC_ARB_AGE_RD                    regMC_ARB_AGE_RD;
typedef union MC_ARB_AGE_WR                    regMC_ARB_AGE_WR;
typedef union MC_ARB_BANKMAP                   regMC_ARB_BANKMAP;
typedef union MC_ARB_BURST_TIME                regMC_ARB_BURST_TIME;
typedef union MC_ARB_BUSY_STATUS__CI           regMC_ARB_BUSY_STATUS__CI;
typedef union MC_ARB_BUSY_STATUS__VI           regMC_ARB_BUSY_STATUS__VI;
typedef union MC_ARB_CAC_CNTL                  regMC_ARB_CAC_CNTL;
typedef union MC_ARB_CG__CI__VI                regMC_ARB_CG__CI__VI;
typedef union MC_ARB_CG__SI                    regMC_ARB_CG__SI;
typedef union MC_ARB_DRAM_TIMING               regMC_ARB_DRAM_TIMING;
typedef union MC_ARB_DRAM_TIMING2              regMC_ARB_DRAM_TIMING2;
typedef union MC_ARB_DRAM_TIMING2_1            regMC_ARB_DRAM_TIMING2_1;
typedef union MC_ARB_DRAM_TIMING_1             regMC_ARB_DRAM_TIMING_1;
typedef union MC_ARB_FED_CNTL                  regMC_ARB_FED_CNTL;
typedef union MC_ARB_GDEC_RD_CNTL              regMC_ARB_GDEC_RD_CNTL;
typedef union MC_ARB_GDEC_WR_CNTL              regMC_ARB_GDEC_WR_CNTL;
typedef union MC_ARB_GECC2                     regMC_ARB_GECC2;
typedef union MC_ARB_GECC2_CLI                 regMC_ARB_GECC2_CLI;
typedef union MC_ARB_GECC2_DEBUG               regMC_ARB_GECC2_DEBUG;
typedef union MC_ARB_GECC2_DEBUG2              regMC_ARB_GECC2_DEBUG2;
typedef union MC_ARB_GECC2_MISC__SI__CI        regMC_ARB_GECC2_MISC__SI__CI;
typedef union MC_ARB_GECC2_MISC__VI            regMC_ARB_GECC2_MISC__VI;
typedef union MC_ARB_GECC2_STATUS              regMC_ARB_GECC2_STATUS;
typedef union MC_ARB_HARSH_BWCNT0_RD__CI__VI   regMC_ARB_HARSH_BWCNT0_RD__CI__VI;
typedef union MC_ARB_HARSH_BWCNT0_WR__CI__VI   regMC_ARB_HARSH_BWCNT0_WR__CI__VI;
typedef union MC_ARB_HARSH_BWCNT1_RD__CI__VI   regMC_ARB_HARSH_BWCNT1_RD__CI__VI;
typedef union MC_ARB_HARSH_BWCNT1_WR__CI__VI   regMC_ARB_HARSH_BWCNT1_WR__CI__VI;
typedef union MC_ARB_HARSH_BWPERIOD0_RD__CI__VI regMC_ARB_HARSH_BWPERIOD0_RD__CI__VI;
typedef union MC_ARB_HARSH_BWPERIOD0_WR__CI__VI regMC_ARB_HARSH_BWPERIOD0_WR__CI__VI;
typedef union MC_ARB_HARSH_BWPERIOD1_RD__CI__VI regMC_ARB_HARSH_BWPERIOD1_RD__CI__VI;
typedef union MC_ARB_HARSH_BWPERIOD1_WR__CI__VI regMC_ARB_HARSH_BWPERIOD1_WR__CI__VI;
typedef union MC_ARB_HARSH_CTL_RD__CI__VI      regMC_ARB_HARSH_CTL_RD__CI__VI;
typedef union MC_ARB_HARSH_CTL_WR__CI__VI      regMC_ARB_HARSH_CTL_WR__CI__VI;
typedef union MC_ARB_HARSH_EN_RD__CI__VI       regMC_ARB_HARSH_EN_RD__CI__VI;
typedef union MC_ARB_HARSH_EN_WR__CI__VI       regMC_ARB_HARSH_EN_WR__CI__VI;
typedef union MC_ARB_HARSH_SAT0_RD__CI__VI     regMC_ARB_HARSH_SAT0_RD__CI__VI;
typedef union MC_ARB_HARSH_SAT0_WR__CI__VI     regMC_ARB_HARSH_SAT0_WR__CI__VI;
typedef union MC_ARB_HARSH_SAT1_RD__CI__VI     regMC_ARB_HARSH_SAT1_RD__CI__VI;
typedef union MC_ARB_HARSH_SAT1_WR__CI__VI     regMC_ARB_HARSH_SAT1_WR__CI__VI;
typedef union MC_ARB_HARSH_TX_HI0_RD__CI__VI   regMC_ARB_HARSH_TX_HI0_RD__CI__VI;
typedef union MC_ARB_HARSH_TX_HI0_WR__CI__VI   regMC_ARB_HARSH_TX_HI0_WR__CI__VI;
typedef union MC_ARB_HARSH_TX_HI1_RD__CI__VI   regMC_ARB_HARSH_TX_HI1_RD__CI__VI;
typedef union MC_ARB_HARSH_TX_HI1_WR__CI__VI   regMC_ARB_HARSH_TX_HI1_WR__CI__VI;
typedef union MC_ARB_HARSH_TX_LO0_RD__CI__VI   regMC_ARB_HARSH_TX_LO0_RD__CI__VI;
typedef union MC_ARB_HARSH_TX_LO0_WR__CI__VI   regMC_ARB_HARSH_TX_LO0_WR__CI__VI;
typedef union MC_ARB_HARSH_TX_LO1_RD__CI__VI   regMC_ARB_HARSH_TX_LO1_RD__CI__VI;
typedef union MC_ARB_HARSH_TX_LO1_WR__CI__VI   regMC_ARB_HARSH_TX_LO1_WR__CI__VI;
typedef union MC_ARB_LAZY0_RD                  regMC_ARB_LAZY0_RD;
typedef union MC_ARB_LAZY0_WR                  regMC_ARB_LAZY0_WR;
typedef union MC_ARB_LAZY1_RD                  regMC_ARB_LAZY1_RD;
typedef union MC_ARB_LAZY1_WR                  regMC_ARB_LAZY1_WR;
typedef union MC_ARB_LM_RD                     regMC_ARB_LM_RD;
typedef union MC_ARB_LM_WR                     regMC_ARB_LM_WR;
typedef union MC_ARB_MAX_LAT_CID__CI__VI       regMC_ARB_MAX_LAT_CID__CI__VI;
typedef union MC_ARB_MAX_LAT_RSLT0__CI__VI     regMC_ARB_MAX_LAT_RSLT0__CI__VI;
typedef union MC_ARB_MAX_LAT_RSLT1__CI__VI     regMC_ARB_MAX_LAT_RSLT1__CI__VI;
typedef union MC_ARB_MINCLKS                   regMC_ARB_MINCLKS;
typedef union MC_ARB_MISC                      regMC_ARB_MISC;
typedef union MC_ARB_MISC2                     regMC_ARB_MISC2;
typedef union MC_ARB_MISC3__CI                 regMC_ARB_MISC3__CI;
typedef union MC_ARB_MISC3__VI                 regMC_ARB_MISC3__VI;
typedef union MC_ARB_PERFCOUNTER0_CFG__CI__VI  regMC_ARB_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_ARB_PERFCOUNTER1_CFG__CI__VI  regMC_ARB_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_ARB_PERFCOUNTER2_CFG__CI__VI  regMC_ARB_PERFCOUNTER2_CFG__CI__VI;
typedef union MC_ARB_PERFCOUNTER3_CFG__CI__VI  regMC_ARB_PERFCOUNTER3_CFG__CI__VI;
typedef union MC_ARB_PERFCOUNTER_HI__CI__VI    regMC_ARB_PERFCOUNTER_HI__CI__VI;
typedef union MC_ARB_PERFCOUNTER_LO__CI__VI    regMC_ARB_PERFCOUNTER_LO__CI__VI;
typedef union MC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_ARB_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_ARB_PERF_MON_CNTL0_ECC__CI    regMC_ARB_PERF_MON_CNTL0_ECC__CI;
typedef union MC_ARB_PERF_MON_CNTL0__SI        regMC_ARB_PERF_MON_CNTL0__SI;
typedef union MC_ARB_PM_CNTL__CI               regMC_ARB_PM_CNTL__CI;
typedef union MC_ARB_PM_CNTL__VI               regMC_ARB_PM_CNTL__VI;
typedef union MC_ARB_PM_CNTL__SI               regMC_ARB_PM_CNTL__SI;
typedef union MC_ARB_POP                       regMC_ARB_POP;
typedef union MC_ARB_RAMCFG__CI__VI            regMC_ARB_RAMCFG__CI__VI;
typedef union MC_ARB_RAMCFG__SI                regMC_ARB_RAMCFG__SI;
typedef union MC_ARB_REMREQ                    regMC_ARB_REMREQ;
typedef union MC_ARB_REPLAY                    regMC_ARB_REPLAY;
typedef union MC_ARB_RET_CREDITS2__CI__VI      regMC_ARB_RET_CREDITS2__CI__VI;
typedef union MC_ARB_RET_CREDITS_RD            regMC_ARB_RET_CREDITS_RD;
typedef union MC_ARB_RET_CREDITS_WR            regMC_ARB_RET_CREDITS_WR;
typedef union MC_ARB_RFSH_CNTL                 regMC_ARB_RFSH_CNTL;
typedef union MC_ARB_RFSH_RATE                 regMC_ARB_RFSH_RATE;
typedef union MC_ARB_RTT_CNTL0                 regMC_ARB_RTT_CNTL0;
typedef union MC_ARB_RTT_CNTL1                 regMC_ARB_RTT_CNTL1;
typedef union MC_ARB_RTT_CNTL2                 regMC_ARB_RTT_CNTL2;
typedef union MC_ARB_RTT_DATA                  regMC_ARB_RTT_DATA;
typedef union MC_ARB_RTT_DEBUG                 regMC_ARB_RTT_DEBUG;
typedef union MC_ARB_SQM_CNTL__CI__VI          regMC_ARB_SQM_CNTL__CI__VI;
typedef union MC_ARB_SQM_CNTL__SI              regMC_ARB_SQM_CNTL__SI;
typedef union MC_ARB_SSM__CI                   regMC_ARB_SSM__CI;
typedef union MC_ARB_TM_CNTL_RD                regMC_ARB_TM_CNTL_RD;
typedef union MC_ARB_TM_CNTL_WR                regMC_ARB_TM_CNTL_WR;
typedef union MC_ARB_WCDR__SI__CI              regMC_ARB_WCDR__SI__CI;
typedef union MC_ARB_WCDR_2__SI__CI            regMC_ARB_WCDR_2__SI__CI;
typedef union MC_ARB_WTM_CNTL_RD               regMC_ARB_WTM_CNTL_RD;
typedef union MC_ARB_WTM_CNTL_WR               regMC_ARB_WTM_CNTL_WR;
typedef union MC_ARB_WTM_GRPWT_RD              regMC_ARB_WTM_GRPWT_RD;
typedef union MC_ARB_WTM_GRPWT_WR              regMC_ARB_WTM_GRPWT_WR;
typedef union MC_BIST_AUTO_CNTL__SI__CI        regMC_BIST_AUTO_CNTL__SI__CI;
typedef union MC_BIST_CMD_CNTL__SI__CI         regMC_BIST_CMD_CNTL__SI__CI;
typedef union MC_BIST_CMP_CNTL__SI__CI         regMC_BIST_CMP_CNTL__SI__CI;
typedef union MC_BIST_CMP_CNTL_2__SI__CI       regMC_BIST_CMP_CNTL_2__SI__CI;
typedef union MC_BIST_CNTL__SI__CI             regMC_BIST_CNTL__SI__CI;
typedef union MC_BIST_CNTL__VI                 regMC_BIST_CNTL__VI;
typedef union MC_BIST_DATA_MASK__SI__CI        regMC_BIST_DATA_MASK__SI__CI;
typedef union MC_BIST_DATA_WORD0               regMC_BIST_DATA_WORD0;
typedef union MC_BIST_DATA_WORD1               regMC_BIST_DATA_WORD1;
typedef union MC_BIST_DATA_WORD2               regMC_BIST_DATA_WORD2;
typedef union MC_BIST_DATA_WORD3               regMC_BIST_DATA_WORD3;
typedef union MC_BIST_DATA_WORD4               regMC_BIST_DATA_WORD4;
typedef union MC_BIST_DATA_WORD5               regMC_BIST_DATA_WORD5;
typedef union MC_BIST_DATA_WORD6               regMC_BIST_DATA_WORD6;
typedef union MC_BIST_DATA_WORD7               regMC_BIST_DATA_WORD7;
typedef union MC_BIST_DIR_CNTL__SI__CI         regMC_BIST_DIR_CNTL__SI__CI;
typedef union MC_BIST_EADDR__SI__CI            regMC_BIST_EADDR__SI__CI;
typedef union MC_BIST_MISMATCH_ADDR__SI__CI    regMC_BIST_MISMATCH_ADDR__SI__CI;
typedef union MC_BIST_MISMATCH_ADDR__VI        regMC_BIST_MISMATCH_ADDR__VI;
typedef union MC_BIST_RDATA_EDC__SI__CI        regMC_BIST_RDATA_EDC__SI__CI;
typedef union MC_BIST_RDATA_MASK__SI__CI       regMC_BIST_RDATA_MASK__SI__CI;
typedef union MC_BIST_RDATA_WORD0              regMC_BIST_RDATA_WORD0;
typedef union MC_BIST_RDATA_WORD1              regMC_BIST_RDATA_WORD1;
typedef union MC_BIST_RDATA_WORD2              regMC_BIST_RDATA_WORD2;
typedef union MC_BIST_RDATA_WORD3              regMC_BIST_RDATA_WORD3;
typedef union MC_BIST_RDATA_WORD4              regMC_BIST_RDATA_WORD4;
typedef union MC_BIST_RDATA_WORD5              regMC_BIST_RDATA_WORD5;
typedef union MC_BIST_RDATA_WORD6              regMC_BIST_RDATA_WORD6;
typedef union MC_BIST_RDATA_WORD7              regMC_BIST_RDATA_WORD7;
typedef union MC_BIST_SADDR__SI__CI            regMC_BIST_SADDR__SI__CI;
typedef union MC_CG_CONFIG                     regMC_CG_CONFIG;
typedef union MC_CG_CONFIG_MCD                 regMC_CG_CONFIG_MCD;
typedef union MC_CG_DATAPORT                   regMC_CG_DATAPORT;
typedef union MC_CITF_CNTL__CI                 regMC_CITF_CNTL__CI;
typedef union MC_CITF_CNTL__VI                 regMC_CITF_CNTL__VI;
typedef union MC_CITF_CNTL__SI                 regMC_CITF_CNTL__SI;
typedef union MC_CITF_CREDITS_ARB_RD           regMC_CITF_CREDITS_ARB_RD;
typedef union MC_CITF_CREDITS_ARB_WR__SI__CI   regMC_CITF_CREDITS_ARB_WR__SI__CI;
typedef union MC_CITF_CREDITS_ARB_WR__VI       regMC_CITF_CREDITS_ARB_WR__VI;
typedef union MC_CITF_CREDITS_VM               regMC_CITF_CREDITS_VM;
typedef union MC_CITF_CREDITS_XBAR             regMC_CITF_CREDITS_XBAR;
typedef union MC_CITF_DAGB_CNTL                regMC_CITF_DAGB_CNTL;
typedef union MC_CITF_DAGB_DLY                 regMC_CITF_DAGB_DLY;
typedef union MC_CITF_INT_CREDITS              regMC_CITF_INT_CREDITS;
typedef union MC_CITF_INT_CREDITS_WR__CI__VI   regMC_CITF_INT_CREDITS_WR__CI__VI;
typedef union MC_CITF_MISC_RD_CG               regMC_CITF_MISC_RD_CG;
typedef union MC_CITF_MISC_VM_CG               regMC_CITF_MISC_VM_CG;
typedef union MC_CITF_MISC_WR_CG               regMC_CITF_MISC_WR_CG;
typedef union MC_CITF_PERFCOUNTER0_CFG__CI__VI regMC_CITF_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_CITF_PERFCOUNTER1_CFG__CI__VI regMC_CITF_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_CITF_PERFCOUNTER2_CFG__CI__VI regMC_CITF_PERFCOUNTER2_CFG__CI__VI;
typedef union MC_CITF_PERFCOUNTER3_CFG__CI__VI regMC_CITF_PERFCOUNTER3_CFG__CI__VI;
typedef union MC_CITF_PERFCOUNTER_HI__CI__VI   regMC_CITF_PERFCOUNTER_HI__CI__VI;
typedef union MC_CITF_PERFCOUNTER_LO__CI__VI   regMC_CITF_PERFCOUNTER_LO__CI__VI;
typedef union MC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_CITF_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_CITF_PERF_MON_CNTL2           regMC_CITF_PERF_MON_CNTL2;
typedef union MC_CITF_PERF_MON_RSLT2__SI__CI   regMC_CITF_PERF_MON_RSLT2__SI__CI;
typedef union MC_CITF_PERF_MON_RSLT2__VI       regMC_CITF_PERF_MON_RSLT2__VI;
typedef union MC_CITF_REMREQ                   regMC_CITF_REMREQ;
typedef union MC_CITF_RET_MODE                 regMC_CITF_RET_MODE;
typedef union MC_CITF_WTM_RD_CNTL__CI__VI      regMC_CITF_WTM_RD_CNTL__CI__VI;
typedef union MC_CITF_WTM_RD_CNTL__SI          regMC_CITF_WTM_RD_CNTL__SI;
typedef union MC_CITF_WTM_WR_CNTL__CI__VI      regMC_CITF_WTM_WR_CNTL__CI__VI;
typedef union MC_CITF_WTM_WR_CNTL__SI          regMC_CITF_WTM_WR_CNTL__SI;
typedef union MC_CITF_XTRA_ENABLE              regMC_CITF_XTRA_ENABLE;
typedef union MC_CONFIG__SI__CI                regMC_CONFIG__SI__CI;
typedef union MC_CONFIG__VI                    regMC_CONFIG__VI;
typedef union MC_CONFIG_MCD                    regMC_CONFIG_MCD;
typedef union MC_DC_INTERFACE_NACK_STATUS__SI__VI regMC_DC_INTERFACE_NACK_STATUS__SI__VI;
typedef union MC_DLB_CONFIG0__CI               regMC_DLB_CONFIG0__CI;
typedef union MC_DLB_CONFIG1__CI               regMC_DLB_CONFIG1__CI;
typedef union MC_DLB_MISCCTRL0__CI             regMC_DLB_MISCCTRL0__CI;
typedef union MC_DLB_MISCCTRL1__CI             regMC_DLB_MISCCTRL1__CI;
typedef union MC_DLB_MISCCTRL2__CI             regMC_DLB_MISCCTRL2__CI;
typedef union MC_DLB_SETUPFIFO__CI             regMC_DLB_SETUPFIFO__CI;
typedef union MC_DLB_SETUPSWEEP__CI            regMC_DLB_SETUPSWEEP__CI;
typedef union MC_DLB_SETUP__CI                 regMC_DLB_SETUP__CI;
typedef union MC_DLB_STATUS_MISC0__CI          regMC_DLB_STATUS_MISC0__CI;
typedef union MC_DLB_STATUS_MISC1__CI          regMC_DLB_STATUS_MISC1__CI;
typedef union MC_DLB_STATUS_MISC2__CI          regMC_DLB_STATUS_MISC2__CI;
typedef union MC_DLB_STATUS_MISC3__CI          regMC_DLB_STATUS_MISC3__CI;
typedef union MC_DLB_STATUS_MISC4__CI          regMC_DLB_STATUS_MISC4__CI;
typedef union MC_DLB_STATUS_MISC5__CI          regMC_DLB_STATUS_MISC5__CI;
typedef union MC_DLB_STATUS_MISC6__CI          regMC_DLB_STATUS_MISC6__CI;
typedef union MC_DLB_STATUS_MISC7__CI          regMC_DLB_STATUS_MISC7__CI;
typedef union MC_DLB_STATUS__CI                regMC_DLB_STATUS__CI;
typedef union MC_DLB_WRITE_MASK__CI            regMC_DLB_WRITE_MASK__CI;
typedef union MC_HUB_MISC_DBG__SI__CI          regMC_HUB_MISC_DBG__SI__CI;
typedef union MC_HUB_MISC_FRAMING              regMC_HUB_MISC_FRAMING;
typedef union MC_HUB_MISC_HUB_CG               regMC_HUB_MISC_HUB_CG;
typedef union MC_HUB_MISC_IDLE_STATUS__CI      regMC_HUB_MISC_IDLE_STATUS__CI;
typedef union MC_HUB_MISC_IDLE_STATUS__VI      regMC_HUB_MISC_IDLE_STATUS__VI;
typedef union MC_HUB_MISC_IDLE_STATUS__SI      regMC_HUB_MISC_IDLE_STATUS__SI;
typedef union MC_HUB_MISC_OVERRIDE             regMC_HUB_MISC_OVERRIDE;
typedef union MC_HUB_MISC_POWER                regMC_HUB_MISC_POWER;
typedef union MC_HUB_MISC_SIP_CG               regMC_HUB_MISC_SIP_CG;
typedef union MC_HUB_MISC_STATUS__SI__CI       regMC_HUB_MISC_STATUS__SI__CI;
typedef union MC_HUB_MISC_STATUS__VI           regMC_HUB_MISC_STATUS__VI;
typedef union MC_HUB_MISC_VM_CG                regMC_HUB_MISC_VM_CG;
typedef union MC_HUB_PERFCOUNTER0_CFG__CI__VI  regMC_HUB_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_HUB_PERFCOUNTER1_CFG__CI__VI  regMC_HUB_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_HUB_PERFCOUNTER2_CFG__CI__VI  regMC_HUB_PERFCOUNTER2_CFG__CI__VI;
typedef union MC_HUB_PERFCOUNTER3_CFG__CI__VI  regMC_HUB_PERFCOUNTER3_CFG__CI__VI;
typedef union MC_HUB_PERFCOUNTER_HI__CI__VI    regMC_HUB_PERFCOUNTER_HI__CI__VI;
typedef union MC_HUB_PERFCOUNTER_LO__CI__VI    regMC_HUB_PERFCOUNTER_LO__CI__VI;
typedef union MC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_HUB_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_HUB_RDREQ_ACPG_LIMIT__CI__VI  regMC_HUB_RDREQ_ACPG_LIMIT__CI__VI;
typedef union MC_HUB_RDREQ_ACPG__CI__VI        regMC_HUB_RDREQ_ACPG__CI__VI;
typedef union MC_HUB_RDREQ_ACPO__CI__VI        regMC_HUB_RDREQ_ACPO__CI__VI;
typedef union MC_HUB_RDREQ_CNTL__SI__CI        regMC_HUB_RDREQ_CNTL__SI__CI;
typedef union MC_HUB_RDREQ_CNTL__VI            regMC_HUB_RDREQ_CNTL__VI;
typedef union MC_HUB_RDREQ_CPC__CI             regMC_HUB_RDREQ_CPC__CI;
typedef union MC_HUB_RDREQ_CPF__CI             regMC_HUB_RDREQ_CPF__CI;
typedef union MC_HUB_RDREQ_CPG__CI             regMC_HUB_RDREQ_CPG__CI;
typedef union MC_HUB_RDREQ_CP__SI              regMC_HUB_RDREQ_CP__SI;
typedef union MC_HUB_RDREQ_CREDITS             regMC_HUB_RDREQ_CREDITS;
typedef union MC_HUB_RDREQ_CREDITS2__SI__CI    regMC_HUB_RDREQ_CREDITS2__SI__CI;
typedef union MC_HUB_RDREQ_CREDITS2__VI        regMC_HUB_RDREQ_CREDITS2__VI;
typedef union MC_HUB_RDREQ_DMIF                regMC_HUB_RDREQ_DMIF;
typedef union MC_HUB_RDREQ_DMIF_LIMIT          regMC_HUB_RDREQ_DMIF_LIMIT;
typedef union MC_HUB_RDREQ_GBL0                regMC_HUB_RDREQ_GBL0;
typedef union MC_HUB_RDREQ_GBL1                regMC_HUB_RDREQ_GBL1;
typedef union MC_HUB_RDREQ_HDP                 regMC_HUB_RDREQ_HDP;
typedef union MC_HUB_RDREQ_IA0__CI             regMC_HUB_RDREQ_IA0__CI;
typedef union MC_HUB_RDREQ_IA1__CI             regMC_HUB_RDREQ_IA1__CI;
typedef union MC_HUB_RDREQ_IA__CI              regMC_HUB_RDREQ_IA__CI;
typedef union MC_HUB_RDREQ_MCDW__SI__CI        regMC_HUB_RDREQ_MCDW__SI__CI;
typedef union MC_HUB_RDREQ_MCDW__VI            regMC_HUB_RDREQ_MCDW__VI;
typedef union MC_HUB_RDREQ_MCDX__SI__CI        regMC_HUB_RDREQ_MCDX__SI__CI;
typedef union MC_HUB_RDREQ_MCDX__VI            regMC_HUB_RDREQ_MCDX__VI;
typedef union MC_HUB_RDREQ_MCDY__SI__CI        regMC_HUB_RDREQ_MCDY__SI__CI;
typedef union MC_HUB_RDREQ_MCDY__VI            regMC_HUB_RDREQ_MCDY__VI;
typedef union MC_HUB_RDREQ_MCDZ__SI__CI        regMC_HUB_RDREQ_MCDZ__SI__CI;
typedef union MC_HUB_RDREQ_MCDZ__VI            regMC_HUB_RDREQ_MCDZ__VI;
typedef union MC_HUB_RDREQ_MCIF                regMC_HUB_RDREQ_MCIF;
typedef union MC_HUB_RDREQ_RLC                 regMC_HUB_RDREQ_RLC;
typedef union MC_HUB_RDREQ_SAM__CI             regMC_HUB_RDREQ_SAM__CI;
typedef union MC_HUB_RDREQ_SDMA0__CI__VI       regMC_HUB_RDREQ_SDMA0__CI__VI;
typedef union MC_HUB_RDREQ_SDMA1__CI__VI       regMC_HUB_RDREQ_SDMA1__CI__VI;
typedef union MC_HUB_RDREQ_SEM                 regMC_HUB_RDREQ_SEM;
typedef union MC_HUB_RDREQ_SIP__SI__CI         regMC_HUB_RDREQ_SIP__SI__CI;
typedef union MC_HUB_RDREQ_SIP__VI             regMC_HUB_RDREQ_SIP__VI;
typedef union MC_HUB_RDREQ_SMU                 regMC_HUB_RDREQ_SMU;
typedef union MC_HUB_RDREQ_STATUS__SI__CI      regMC_HUB_RDREQ_STATUS__SI__CI;
typedef union MC_HUB_RDREQ_STATUS__VI          regMC_HUB_RDREQ_STATUS__VI;
typedef union MC_HUB_RDREQ_UMC                 regMC_HUB_RDREQ_UMC;
typedef union MC_HUB_RDREQ_UVD                 regMC_HUB_RDREQ_UVD;
typedef union MC_HUB_RDREQ_VCE__SI__CI         regMC_HUB_RDREQ_VCE__SI__CI;
typedef union MC_HUB_RDREQ_VCEU__SI__CI        regMC_HUB_RDREQ_VCEU__SI__CI;
typedef union MC_HUB_RDREQ_VMC                 regMC_HUB_RDREQ_VMC;
typedef union MC_HUB_RDREQ_WTM_CNTL            regMC_HUB_RDREQ_WTM_CNTL;
typedef union MC_HUB_RDREQ_XDMAM               regMC_HUB_RDREQ_XDMAM;
typedef union MC_HUB_SHARED_DAGB_DLY           regMC_HUB_SHARED_DAGB_DLY;
typedef union MC_HUB_WDP_ACPG__CI__VI          regMC_HUB_WDP_ACPG__CI__VI;
typedef union MC_HUB_WDP_ACPO__CI__VI          regMC_HUB_WDP_ACPO__CI__VI;
typedef union MC_HUB_WDP_BP                    regMC_HUB_WDP_BP;
typedef union MC_HUB_WDP_CNTL                  regMC_HUB_WDP_CNTL;
typedef union MC_HUB_WDP_CPC__CI               regMC_HUB_WDP_CPC__CI;
typedef union MC_HUB_WDP_CPF__CI               regMC_HUB_WDP_CPF__CI;
typedef union MC_HUB_WDP_CPG__CI               regMC_HUB_WDP_CPG__CI;
typedef union MC_HUB_WDP_CP__SI                regMC_HUB_WDP_CP__SI;
typedef union MC_HUB_WDP_CREDITS               regMC_HUB_WDP_CREDITS;
typedef union MC_HUB_WDP_ERR                   regMC_HUB_WDP_ERR;
typedef union MC_HUB_WDP_GBL0                  regMC_HUB_WDP_GBL0;
typedef union MC_HUB_WDP_GBL1                  regMC_HUB_WDP_GBL1;
typedef union MC_HUB_WDP_HDP                   regMC_HUB_WDP_HDP;
typedef union MC_HUB_WDP_IH                    regMC_HUB_WDP_IH;
typedef union MC_HUB_WDP_MCDW                  regMC_HUB_WDP_MCDW;
typedef union MC_HUB_WDP_MCDX                  regMC_HUB_WDP_MCDX;
typedef union MC_HUB_WDP_MCDY                  regMC_HUB_WDP_MCDY;
typedef union MC_HUB_WDP_MCDZ                  regMC_HUB_WDP_MCDZ;
typedef union MC_HUB_WDP_MCIF                  regMC_HUB_WDP_MCIF;
typedef union MC_HUB_WDP_MGPU__SI__CI          regMC_HUB_WDP_MGPU__SI__CI;
typedef union MC_HUB_WDP_MGPU2__SI__CI         regMC_HUB_WDP_MGPU2__SI__CI;
typedef union MC_HUB_WDP_RLC                   regMC_HUB_WDP_RLC;
typedef union MC_HUB_WDP_SAM__CI               regMC_HUB_WDP_SAM__CI;
typedef union MC_HUB_WDP_SDMA0__CI__VI         regMC_HUB_WDP_SDMA0__CI__VI;
typedef union MC_HUB_WDP_SDMA1__CI__VI         regMC_HUB_WDP_SDMA1__CI__VI;
typedef union MC_HUB_WDP_SEM                   regMC_HUB_WDP_SEM;
typedef union MC_HUB_WDP_SH0                   regMC_HUB_WDP_SH0;
typedef union MC_HUB_WDP_SH1                   regMC_HUB_WDP_SH1;
typedef union MC_HUB_WDP_SH2__CI__VI           regMC_HUB_WDP_SH2__CI__VI;
typedef union MC_HUB_WDP_SH3__CI__VI           regMC_HUB_WDP_SH3__CI__VI;
typedef union MC_HUB_WDP_SIP                   regMC_HUB_WDP_SIP;
typedef union MC_HUB_WDP_SMU                   regMC_HUB_WDP_SMU;
typedef union MC_HUB_WDP_STATUS__SI__CI        regMC_HUB_WDP_STATUS__SI__CI;
typedef union MC_HUB_WDP_STATUS__VI            regMC_HUB_WDP_STATUS__VI;
typedef union MC_HUB_WDP_UMC                   regMC_HUB_WDP_UMC;
typedef union MC_HUB_WDP_UVD                   regMC_HUB_WDP_UVD;
typedef union MC_HUB_WDP_VCE__SI__CI           regMC_HUB_WDP_VCE__SI__CI;
typedef union MC_HUB_WDP_VCEU__SI__CI          regMC_HUB_WDP_VCEU__SI__CI;
typedef union MC_HUB_WDP_WTM_CNTL              regMC_HUB_WDP_WTM_CNTL;
typedef union MC_HUB_WDP_XDMA                  regMC_HUB_WDP_XDMA;
typedef union MC_HUB_WDP_XDMAM                 regMC_HUB_WDP_XDMAM;
typedef union MC_HUB_WDP_XDP                   regMC_HUB_WDP_XDP;
typedef union MC_HUB_WRRET_CNTL                regMC_HUB_WRRET_CNTL;
typedef union MC_HUB_WRRET_MCDW                regMC_HUB_WRRET_MCDW;
typedef union MC_HUB_WRRET_MCDX                regMC_HUB_WRRET_MCDX;
typedef union MC_HUB_WRRET_MCDY                regMC_HUB_WRRET_MCDY;
typedef union MC_HUB_WRRET_MCDZ                regMC_HUB_WRRET_MCDZ;
typedef union MC_HUB_WRRET_STATUS              regMC_HUB_WRRET_STATUS;
typedef union MC_IMP_CNTL__SI__CI              regMC_IMP_CNTL__SI__CI;
typedef union MC_IMP_DEBUG__SI__CI             regMC_IMP_DEBUG__SI__CI;
typedef union MC_IMP_DQ_STATUS__SI__CI         regMC_IMP_DQ_STATUS__SI__CI;
typedef union MC_IMP_STATUS__SI__CI            regMC_IMP_STATUS__SI__CI;
typedef union MC_IO_APHY_STR_CNTL_D0__SI__CI   regMC_IO_APHY_STR_CNTL_D0__SI__CI;
typedef union MC_IO_APHY_STR_CNTL_D1__SI__CI   regMC_IO_APHY_STR_CNTL_D1__SI__CI;
typedef union MC_IO_CDRCNTL1_D0__SI__CI        regMC_IO_CDRCNTL1_D0__SI__CI;
typedef union MC_IO_CDRCNTL1_D1__SI__CI        regMC_IO_CDRCNTL1_D1__SI__CI;
typedef union MC_IO_CDRCNTL2_D0__SI__CI        regMC_IO_CDRCNTL2_D0__SI__CI;
typedef union MC_IO_CDRCNTL2_D1__SI__CI        regMC_IO_CDRCNTL2_D1__SI__CI;
typedef union MC_IO_CDRCNTL_D0__SI__CI         regMC_IO_CDRCNTL_D0__SI__CI;
typedef union MC_IO_CDRCNTL_D1__SI__CI         regMC_IO_CDRCNTL_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_CLKSEL_D0__SI__CI regMC_IO_DEBUG_ACMD_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_CLKSEL_D1__SI__CI regMC_IO_DEBUG_ACMD_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_MISC_D0__SI__CI regMC_IO_DEBUG_ACMD_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_MISC_D1__SI__CI regMC_IO_DEBUG_ACMD_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_OFSCAL_D0__SI__CI regMC_IO_DEBUG_ACMD_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_OFSCAL_D1__SI__CI regMC_IO_DEBUG_ACMD_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_RXPHASE_D0__SI__CI regMC_IO_DEBUG_ACMD_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_RXPHASE_D1__SI__CI regMC_IO_DEBUG_ACMD_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_ACMD_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXPHASE_D0__SI__CI regMC_IO_DEBUG_ACMD_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXPHASE_D1__SI__CI regMC_IO_DEBUG_ACMD_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXSLF_D0__SI__CI regMC_IO_DEBUG_ACMD_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_ACMD_TXSLF_D1__SI__CI regMC_IO_DEBUG_ACMD_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_CLKSEL_D0__SI__CI regMC_IO_DEBUG_ADDRH_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_CLKSEL_D1__SI__CI regMC_IO_DEBUG_ADDRH_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_MISC_D0__SI__CI regMC_IO_DEBUG_ADDRH_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_MISC_D1__SI__CI regMC_IO_DEBUG_ADDRH_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_RXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRH_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_RXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRH_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXSLF_D0__SI__CI regMC_IO_DEBUG_ADDRH_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRH_TXSLF_D1__SI__CI regMC_IO_DEBUG_ADDRH_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_CLKSEL_D0__SI__CI regMC_IO_DEBUG_ADDRL_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_CLKSEL_D1__SI__CI regMC_IO_DEBUG_ADDRL_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_MISC_D0__SI__CI regMC_IO_DEBUG_ADDRL_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_MISC_D1__SI__CI regMC_IO_DEBUG_ADDRL_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_RXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRL_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_RXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRL_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXPHASE_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXPHASE_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXSLF_D0__SI__CI regMC_IO_DEBUG_ADDRL_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_ADDRL_TXSLF_D1__SI__CI regMC_IO_DEBUG_ADDRL_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_CLKSEL_D0__SI__CI regMC_IO_DEBUG_CK_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_CLKSEL_D1__SI__CI regMC_IO_DEBUG_CK_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_MISC_D0__SI__CI   regMC_IO_DEBUG_CK_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_MISC_D1__SI__CI   regMC_IO_DEBUG_CK_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_RXPHASE_D0__SI__CI regMC_IO_DEBUG_CK_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_RXPHASE_D1__SI__CI regMC_IO_DEBUG_CK_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_CK_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_CK_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_CK_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_CK_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_TXPHASE_D0__SI__CI regMC_IO_DEBUG_CK_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_TXPHASE_D1__SI__CI regMC_IO_DEBUG_CK_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_CK_TXSLF_D0__SI__CI  regMC_IO_DEBUG_CK_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_CK_TXSLF_D1__SI__CI  regMC_IO_DEBUG_CK_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_CLKSEL_D0__SI__CI regMC_IO_DEBUG_CMD_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_CLKSEL_D1__SI__CI regMC_IO_DEBUG_CMD_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_MISC_D0__SI__CI  regMC_IO_DEBUG_CMD_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_MISC_D1__SI__CI  regMC_IO_DEBUG_CMD_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_OFSCAL_D0__SI__CI regMC_IO_DEBUG_CMD_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_OFSCAL_D1__SI__CI regMC_IO_DEBUG_CMD_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_RXPHASE_D0__SI__CI regMC_IO_DEBUG_CMD_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_RXPHASE_D1__SI__CI regMC_IO_DEBUG_CMD_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_RX_EQ_D0__SI__CI regMC_IO_DEBUG_CMD_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_RX_EQ_D1__SI__CI regMC_IO_DEBUG_CMD_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_CMD_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_CMD_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_CMD_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_CMD_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXPHASE_D0__SI__CI regMC_IO_DEBUG_CMD_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXPHASE_D1__SI__CI regMC_IO_DEBUG_CMD_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXSLF_D0__SI__CI regMC_IO_DEBUG_CMD_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_CMD_TXSLF_D1__SI__CI regMC_IO_DEBUG_CMD_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DBI_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DBI_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DBI_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DBI_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_MISC_D0__SI__CI  regMC_IO_DEBUG_DBI_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_MISC_D1__SI__CI  regMC_IO_DEBUG_DBI_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DBI_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DBI_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DBI_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DBI_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DBI_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DBI_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DBI_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DBI_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DBI_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DBI_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DBI_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DBI_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DBI_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DBI_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXSLF_D0__SI__CI regMC_IO_DEBUG_DBI_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DBI_TXSLF_D1__SI__CI regMC_IO_DEBUG_DBI_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_DQ0_RX_DYN_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_DQ0_RX_DYN_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_DQ0_RX_EQ_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_DQ0_RX_EQ_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_DQ1_RX_DYN_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_DQ1_RX_DYN_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_DQ1_RX_EQ_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_DQ1_RX_EQ_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB0H_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB0H_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB0H_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB0H_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB0H_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB0H_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0H_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0H_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB0H_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB0H_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB0H_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB0H_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB0L_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB0L_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB0L_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB0L_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB0L_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB0L_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0L_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0L_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB0L_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB0L_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB0L_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB0L_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB1H_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB1H_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB1H_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB1H_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB1H_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB1H_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1H_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1H_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB1H_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB1H_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB1H_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB1H_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB1L_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB1L_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB1L_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB1L_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB1L_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB1L_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1L_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1L_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB1L_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB1L_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB1L_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB1L_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB2H_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB2H_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB2H_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB2H_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB2H_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB2H_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2H_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2H_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB2H_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB2H_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB2H_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB2H_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB2L_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB2L_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB2L_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB2L_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB2L_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB2L_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2L_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2L_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB2L_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB2L_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB2L_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB2L_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB3H_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB3H_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_MISC_D0__SI__CI regMC_IO_DEBUG_DQB3H_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_MISC_D1__SI__CI regMC_IO_DEBUG_DQB3H_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB3H_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB3H_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3H_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3H_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB3H_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB3H_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB3H_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3H_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB3H_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_CLKSEL_D0__SI__CI regMC_IO_DEBUG_DQB3L_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_CLKSEL_D1__SI__CI regMC_IO_DEBUG_DQB3L_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_MISC_D0__SI__CI regMC_IO_DEBUG_DQB3L_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_MISC_D1__SI__CI regMC_IO_DEBUG_DQB3L_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_OFSCAL_D0__SI__CI regMC_IO_DEBUG_DQB3L_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_OFSCAL_D1__SI__CI regMC_IO_DEBUG_DQB3L_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_RXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3L_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_RXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3L_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_RX_EQ_D0__SI__CI regMC_IO_DEBUG_DQB3L_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_RX_EQ_D1__SI__CI regMC_IO_DEBUG_DQB3L_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXPHASE_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXPHASE_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXSLF_D0__SI__CI regMC_IO_DEBUG_DQB3L_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3L_TXSLF_D1__SI__CI regMC_IO_DEBUG_DQB3L_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_EDC_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_EDC_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_CLKSEL_D0__SI__CI regMC_IO_DEBUG_EDC_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_CLKSEL_D1__SI__CI regMC_IO_DEBUG_EDC_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_MISC_D0__SI__CI  regMC_IO_DEBUG_EDC_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_MISC_D1__SI__CI  regMC_IO_DEBUG_EDC_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_OFSCAL_D0__SI__CI regMC_IO_DEBUG_EDC_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_OFSCAL_D1__SI__CI regMC_IO_DEBUG_EDC_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_RXPHASE_D0__SI__CI regMC_IO_DEBUG_EDC_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_RXPHASE_D1__SI__CI regMC_IO_DEBUG_EDC_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_EDC_RX_DYN_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_EDC_RX_DYN_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_EQ_D0__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_EQ_D1__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_EDC_RX_EQ_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_EDC_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_EDC_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_EDC_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_EDC_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_EDC_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_EDC_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXPHASE_D0__SI__CI regMC_IO_DEBUG_EDC_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXPHASE_D1__SI__CI regMC_IO_DEBUG_EDC_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXSLF_D0__SI__CI regMC_IO_DEBUG_EDC_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_EDC_TXSLF_D1__SI__CI regMC_IO_DEBUG_EDC_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_UP_0                 regMC_IO_DEBUG_UP_0;
typedef union MC_IO_DEBUG_UP_1                 regMC_IO_DEBUG_UP_1;
typedef union MC_IO_DEBUG_UP_10                regMC_IO_DEBUG_UP_10;
typedef union MC_IO_DEBUG_UP_100               regMC_IO_DEBUG_UP_100;
typedef union MC_IO_DEBUG_UP_101               regMC_IO_DEBUG_UP_101;
typedef union MC_IO_DEBUG_UP_102               regMC_IO_DEBUG_UP_102;
typedef union MC_IO_DEBUG_UP_103               regMC_IO_DEBUG_UP_103;
typedef union MC_IO_DEBUG_UP_104               regMC_IO_DEBUG_UP_104;
typedef union MC_IO_DEBUG_UP_105               regMC_IO_DEBUG_UP_105;
typedef union MC_IO_DEBUG_UP_106               regMC_IO_DEBUG_UP_106;
typedef union MC_IO_DEBUG_UP_107               regMC_IO_DEBUG_UP_107;
typedef union MC_IO_DEBUG_UP_108               regMC_IO_DEBUG_UP_108;
typedef union MC_IO_DEBUG_UP_109               regMC_IO_DEBUG_UP_109;
typedef union MC_IO_DEBUG_UP_11                regMC_IO_DEBUG_UP_11;
typedef union MC_IO_DEBUG_UP_110               regMC_IO_DEBUG_UP_110;
typedef union MC_IO_DEBUG_UP_111               regMC_IO_DEBUG_UP_111;
typedef union MC_IO_DEBUG_UP_112               regMC_IO_DEBUG_UP_112;
typedef union MC_IO_DEBUG_UP_113               regMC_IO_DEBUG_UP_113;
typedef union MC_IO_DEBUG_UP_114               regMC_IO_DEBUG_UP_114;
typedef union MC_IO_DEBUG_UP_115               regMC_IO_DEBUG_UP_115;
typedef union MC_IO_DEBUG_UP_116               regMC_IO_DEBUG_UP_116;
typedef union MC_IO_DEBUG_UP_117               regMC_IO_DEBUG_UP_117;
typedef union MC_IO_DEBUG_UP_118               regMC_IO_DEBUG_UP_118;
typedef union MC_IO_DEBUG_UP_119               regMC_IO_DEBUG_UP_119;
typedef union MC_IO_DEBUG_UP_12                regMC_IO_DEBUG_UP_12;
typedef union MC_IO_DEBUG_UP_120               regMC_IO_DEBUG_UP_120;
typedef union MC_IO_DEBUG_UP_121               regMC_IO_DEBUG_UP_121;
typedef union MC_IO_DEBUG_UP_122               regMC_IO_DEBUG_UP_122;
typedef union MC_IO_DEBUG_UP_123               regMC_IO_DEBUG_UP_123;
typedef union MC_IO_DEBUG_UP_124               regMC_IO_DEBUG_UP_124;
typedef union MC_IO_DEBUG_UP_125               regMC_IO_DEBUG_UP_125;
typedef union MC_IO_DEBUG_UP_126               regMC_IO_DEBUG_UP_126;
typedef union MC_IO_DEBUG_UP_127               regMC_IO_DEBUG_UP_127;
typedef union MC_IO_DEBUG_UP_128               regMC_IO_DEBUG_UP_128;
typedef union MC_IO_DEBUG_UP_129               regMC_IO_DEBUG_UP_129;
typedef union MC_IO_DEBUG_UP_13                regMC_IO_DEBUG_UP_13;
typedef union MC_IO_DEBUG_UP_130               regMC_IO_DEBUG_UP_130;
typedef union MC_IO_DEBUG_UP_131               regMC_IO_DEBUG_UP_131;
typedef union MC_IO_DEBUG_UP_132               regMC_IO_DEBUG_UP_132;
typedef union MC_IO_DEBUG_UP_133               regMC_IO_DEBUG_UP_133;
typedef union MC_IO_DEBUG_UP_134               regMC_IO_DEBUG_UP_134;
typedef union MC_IO_DEBUG_UP_135               regMC_IO_DEBUG_UP_135;
typedef union MC_IO_DEBUG_UP_136               regMC_IO_DEBUG_UP_136;
typedef union MC_IO_DEBUG_UP_137               regMC_IO_DEBUG_UP_137;
typedef union MC_IO_DEBUG_UP_138               regMC_IO_DEBUG_UP_138;
typedef union MC_IO_DEBUG_UP_139               regMC_IO_DEBUG_UP_139;
typedef union MC_IO_DEBUG_UP_14                regMC_IO_DEBUG_UP_14;
typedef union MC_IO_DEBUG_UP_140               regMC_IO_DEBUG_UP_140;
typedef union MC_IO_DEBUG_UP_141               regMC_IO_DEBUG_UP_141;
typedef union MC_IO_DEBUG_UP_142               regMC_IO_DEBUG_UP_142;
typedef union MC_IO_DEBUG_UP_143               regMC_IO_DEBUG_UP_143;
typedef union MC_IO_DEBUG_UP_144               regMC_IO_DEBUG_UP_144;
typedef union MC_IO_DEBUG_UP_145               regMC_IO_DEBUG_UP_145;
typedef union MC_IO_DEBUG_UP_146               regMC_IO_DEBUG_UP_146;
typedef union MC_IO_DEBUG_UP_147               regMC_IO_DEBUG_UP_147;
typedef union MC_IO_DEBUG_UP_148               regMC_IO_DEBUG_UP_148;
typedef union MC_IO_DEBUG_UP_149               regMC_IO_DEBUG_UP_149;
typedef union MC_IO_DEBUG_UP_15                regMC_IO_DEBUG_UP_15;
typedef union MC_IO_DEBUG_UP_150               regMC_IO_DEBUG_UP_150;
typedef union MC_IO_DEBUG_UP_151               regMC_IO_DEBUG_UP_151;
typedef union MC_IO_DEBUG_UP_152               regMC_IO_DEBUG_UP_152;
typedef union MC_IO_DEBUG_UP_153               regMC_IO_DEBUG_UP_153;
typedef union MC_IO_DEBUG_UP_154               regMC_IO_DEBUG_UP_154;
typedef union MC_IO_DEBUG_UP_155               regMC_IO_DEBUG_UP_155;
typedef union MC_IO_DEBUG_UP_156               regMC_IO_DEBUG_UP_156;
typedef union MC_IO_DEBUG_UP_157               regMC_IO_DEBUG_UP_157;
typedef union MC_IO_DEBUG_UP_158               regMC_IO_DEBUG_UP_158;
typedef union MC_IO_DEBUG_UP_159               regMC_IO_DEBUG_UP_159;
typedef union MC_IO_DEBUG_UP_16                regMC_IO_DEBUG_UP_16;
typedef union MC_IO_DEBUG_UP_17                regMC_IO_DEBUG_UP_17;
typedef union MC_IO_DEBUG_UP_18                regMC_IO_DEBUG_UP_18;
typedef union MC_IO_DEBUG_UP_19                regMC_IO_DEBUG_UP_19;
typedef union MC_IO_DEBUG_UP_2                 regMC_IO_DEBUG_UP_2;
typedef union MC_IO_DEBUG_UP_20                regMC_IO_DEBUG_UP_20;
typedef union MC_IO_DEBUG_UP_21                regMC_IO_DEBUG_UP_21;
typedef union MC_IO_DEBUG_UP_22                regMC_IO_DEBUG_UP_22;
typedef union MC_IO_DEBUG_UP_23                regMC_IO_DEBUG_UP_23;
typedef union MC_IO_DEBUG_UP_24                regMC_IO_DEBUG_UP_24;
typedef union MC_IO_DEBUG_UP_25                regMC_IO_DEBUG_UP_25;
typedef union MC_IO_DEBUG_UP_26                regMC_IO_DEBUG_UP_26;
typedef union MC_IO_DEBUG_UP_27                regMC_IO_DEBUG_UP_27;
typedef union MC_IO_DEBUG_UP_28                regMC_IO_DEBUG_UP_28;
typedef union MC_IO_DEBUG_UP_29                regMC_IO_DEBUG_UP_29;
typedef union MC_IO_DEBUG_UP_3                 regMC_IO_DEBUG_UP_3;
typedef union MC_IO_DEBUG_UP_30                regMC_IO_DEBUG_UP_30;
typedef union MC_IO_DEBUG_UP_31                regMC_IO_DEBUG_UP_31;
typedef union MC_IO_DEBUG_UP_32                regMC_IO_DEBUG_UP_32;
typedef union MC_IO_DEBUG_UP_33                regMC_IO_DEBUG_UP_33;
typedef union MC_IO_DEBUG_UP_34                regMC_IO_DEBUG_UP_34;
typedef union MC_IO_DEBUG_UP_35                regMC_IO_DEBUG_UP_35;
typedef union MC_IO_DEBUG_UP_36                regMC_IO_DEBUG_UP_36;
typedef union MC_IO_DEBUG_UP_37                regMC_IO_DEBUG_UP_37;
typedef union MC_IO_DEBUG_UP_38                regMC_IO_DEBUG_UP_38;
typedef union MC_IO_DEBUG_UP_39                regMC_IO_DEBUG_UP_39;
typedef union MC_IO_DEBUG_UP_4                 regMC_IO_DEBUG_UP_4;
typedef union MC_IO_DEBUG_UP_40                regMC_IO_DEBUG_UP_40;
typedef union MC_IO_DEBUG_UP_41                regMC_IO_DEBUG_UP_41;
typedef union MC_IO_DEBUG_UP_42                regMC_IO_DEBUG_UP_42;
typedef union MC_IO_DEBUG_UP_43                regMC_IO_DEBUG_UP_43;
typedef union MC_IO_DEBUG_UP_44                regMC_IO_DEBUG_UP_44;
typedef union MC_IO_DEBUG_UP_45                regMC_IO_DEBUG_UP_45;
typedef union MC_IO_DEBUG_UP_46                regMC_IO_DEBUG_UP_46;
typedef union MC_IO_DEBUG_UP_47                regMC_IO_DEBUG_UP_47;
typedef union MC_IO_DEBUG_UP_48                regMC_IO_DEBUG_UP_48;
typedef union MC_IO_DEBUG_UP_49                regMC_IO_DEBUG_UP_49;
typedef union MC_IO_DEBUG_UP_5                 regMC_IO_DEBUG_UP_5;
typedef union MC_IO_DEBUG_UP_50                regMC_IO_DEBUG_UP_50;
typedef union MC_IO_DEBUG_UP_51                regMC_IO_DEBUG_UP_51;
typedef union MC_IO_DEBUG_UP_52                regMC_IO_DEBUG_UP_52;
typedef union MC_IO_DEBUG_UP_53                regMC_IO_DEBUG_UP_53;
typedef union MC_IO_DEBUG_UP_54                regMC_IO_DEBUG_UP_54;
typedef union MC_IO_DEBUG_UP_55                regMC_IO_DEBUG_UP_55;
typedef union MC_IO_DEBUG_UP_56                regMC_IO_DEBUG_UP_56;
typedef union MC_IO_DEBUG_UP_57                regMC_IO_DEBUG_UP_57;
typedef union MC_IO_DEBUG_UP_58                regMC_IO_DEBUG_UP_58;
typedef union MC_IO_DEBUG_UP_59                regMC_IO_DEBUG_UP_59;
typedef union MC_IO_DEBUG_UP_6                 regMC_IO_DEBUG_UP_6;
typedef union MC_IO_DEBUG_UP_60                regMC_IO_DEBUG_UP_60;
typedef union MC_IO_DEBUG_UP_61                regMC_IO_DEBUG_UP_61;
typedef union MC_IO_DEBUG_UP_62                regMC_IO_DEBUG_UP_62;
typedef union MC_IO_DEBUG_UP_63                regMC_IO_DEBUG_UP_63;
typedef union MC_IO_DEBUG_UP_64                regMC_IO_DEBUG_UP_64;
typedef union MC_IO_DEBUG_UP_65                regMC_IO_DEBUG_UP_65;
typedef union MC_IO_DEBUG_UP_66                regMC_IO_DEBUG_UP_66;
typedef union MC_IO_DEBUG_UP_67                regMC_IO_DEBUG_UP_67;
typedef union MC_IO_DEBUG_UP_68                regMC_IO_DEBUG_UP_68;
typedef union MC_IO_DEBUG_UP_69                regMC_IO_DEBUG_UP_69;
typedef union MC_IO_DEBUG_UP_7                 regMC_IO_DEBUG_UP_7;
typedef union MC_IO_DEBUG_UP_70                regMC_IO_DEBUG_UP_70;
typedef union MC_IO_DEBUG_UP_71                regMC_IO_DEBUG_UP_71;
typedef union MC_IO_DEBUG_UP_72                regMC_IO_DEBUG_UP_72;
typedef union MC_IO_DEBUG_UP_73                regMC_IO_DEBUG_UP_73;
typedef union MC_IO_DEBUG_UP_74                regMC_IO_DEBUG_UP_74;
typedef union MC_IO_DEBUG_UP_75                regMC_IO_DEBUG_UP_75;
typedef union MC_IO_DEBUG_UP_76                regMC_IO_DEBUG_UP_76;
typedef union MC_IO_DEBUG_UP_77                regMC_IO_DEBUG_UP_77;
typedef union MC_IO_DEBUG_UP_78                regMC_IO_DEBUG_UP_78;
typedef union MC_IO_DEBUG_UP_79                regMC_IO_DEBUG_UP_79;
typedef union MC_IO_DEBUG_UP_8                 regMC_IO_DEBUG_UP_8;
typedef union MC_IO_DEBUG_UP_80                regMC_IO_DEBUG_UP_80;
typedef union MC_IO_DEBUG_UP_81                regMC_IO_DEBUG_UP_81;
typedef union MC_IO_DEBUG_UP_82                regMC_IO_DEBUG_UP_82;
typedef union MC_IO_DEBUG_UP_83                regMC_IO_DEBUG_UP_83;
typedef union MC_IO_DEBUG_UP_84                regMC_IO_DEBUG_UP_84;
typedef union MC_IO_DEBUG_UP_85                regMC_IO_DEBUG_UP_85;
typedef union MC_IO_DEBUG_UP_86                regMC_IO_DEBUG_UP_86;
typedef union MC_IO_DEBUG_UP_87                regMC_IO_DEBUG_UP_87;
typedef union MC_IO_DEBUG_UP_88                regMC_IO_DEBUG_UP_88;
typedef union MC_IO_DEBUG_UP_89                regMC_IO_DEBUG_UP_89;
typedef union MC_IO_DEBUG_UP_9                 regMC_IO_DEBUG_UP_9;
typedef union MC_IO_DEBUG_UP_90                regMC_IO_DEBUG_UP_90;
typedef union MC_IO_DEBUG_UP_91                regMC_IO_DEBUG_UP_91;
typedef union MC_IO_DEBUG_UP_92                regMC_IO_DEBUG_UP_92;
typedef union MC_IO_DEBUG_UP_93                regMC_IO_DEBUG_UP_93;
typedef union MC_IO_DEBUG_UP_94                regMC_IO_DEBUG_UP_94;
typedef union MC_IO_DEBUG_UP_95                regMC_IO_DEBUG_UP_95;
typedef union MC_IO_DEBUG_UP_96                regMC_IO_DEBUG_UP_96;
typedef union MC_IO_DEBUG_UP_97                regMC_IO_DEBUG_UP_97;
typedef union MC_IO_DEBUG_UP_98                regMC_IO_DEBUG_UP_98;
typedef union MC_IO_DEBUG_UP_99                regMC_IO_DEBUG_UP_99;
typedef union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__SI__CI regMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__SI__CI regMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_CLKSEL_D0__SI__CI regMC_IO_DEBUG_WCDR_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_CLKSEL_D1__SI__CI regMC_IO_DEBUG_WCDR_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_MISC_D0__SI__CI regMC_IO_DEBUG_WCDR_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_MISC_D1__SI__CI regMC_IO_DEBUG_WCDR_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_OFSCAL_D0__SI__CI regMC_IO_DEBUG_WCDR_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_OFSCAL_D1__SI__CI regMC_IO_DEBUG_WCDR_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RXPHASE_D0__SI__CI regMC_IO_DEBUG_WCDR_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RXPHASE_D1__SI__CI regMC_IO_DEBUG_WCDR_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_DYN_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_DYN_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_EQ_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_EQ_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_PM_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_EQ_PM_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_WCDR_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXPHASE_D0__SI__CI regMC_IO_DEBUG_WCDR_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXPHASE_D1__SI__CI regMC_IO_DEBUG_WCDR_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXSLF_D0__SI__CI regMC_IO_DEBUG_WCDR_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_WCDR_TXSLF_D1__SI__CI regMC_IO_DEBUG_WCDR_TXSLF_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_CLKSEL_D0__SI__CI regMC_IO_DEBUG_WCK_CLKSEL_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_CLKSEL_D1__SI__CI regMC_IO_DEBUG_WCK_CLKSEL_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_MISC_D0__SI__CI  regMC_IO_DEBUG_WCK_MISC_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_MISC_D1__SI__CI  regMC_IO_DEBUG_WCK_MISC_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_OFSCAL_D0__SI__CI regMC_IO_DEBUG_WCK_OFSCAL_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_OFSCAL_D1__SI__CI regMC_IO_DEBUG_WCK_OFSCAL_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_RXPHASE_D0__SI__CI regMC_IO_DEBUG_WCK_RXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_RXPHASE_D1__SI__CI regMC_IO_DEBUG_WCK_RXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_RX_EQ_D0__SI__CI regMC_IO_DEBUG_WCK_RX_EQ_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_RX_EQ_D1__SI__CI regMC_IO_DEBUG_WCK_RX_EQ_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__SI__CI regMC_IO_DEBUG_WCK_RX_VREF_CAL_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__SI__CI regMC_IO_DEBUG_WCK_RX_VREF_CAL_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXBST_PD_D0__SI__CI regMC_IO_DEBUG_WCK_TXBST_PD_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXBST_PD_D1__SI__CI regMC_IO_DEBUG_WCK_TXBST_PD_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXBST_PU_D0__SI__CI regMC_IO_DEBUG_WCK_TXBST_PU_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXBST_PU_D1__SI__CI regMC_IO_DEBUG_WCK_TXBST_PU_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXPHASE_D0__SI__CI regMC_IO_DEBUG_WCK_TXPHASE_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXPHASE_D1__SI__CI regMC_IO_DEBUG_WCK_TXPHASE_D1__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXSLF_D0__SI__CI regMC_IO_DEBUG_WCK_TXSLF_D0__SI__CI;
typedef union MC_IO_DEBUG_WCK_TXSLF_D1__SI__CI regMC_IO_DEBUG_WCK_TXSLF_D1__SI__CI;
typedef union MC_IO_DPHY_STR_CNTL_D0__SI__CI   regMC_IO_DPHY_STR_CNTL_D0__SI__CI;
typedef union MC_IO_DPHY_STR_CNTL_D1__SI__CI   regMC_IO_DPHY_STR_CNTL_D1__SI__CI;
typedef union MC_IO_PAD_CNTL__SI__CI           regMC_IO_PAD_CNTL__SI__CI;
typedef union MC_IO_PAD_CNTL_D0__SI__CI        regMC_IO_PAD_CNTL_D0__SI__CI;
typedef union MC_IO_PAD_CNTL_D1__SI__CI        regMC_IO_PAD_CNTL_D1__SI__CI;
typedef union MC_IO_RXCNTL1_DPHY0_D0__CI       regMC_IO_RXCNTL1_DPHY0_D0__CI;
typedef union MC_IO_RXCNTL1_DPHY0_D0__SI       regMC_IO_RXCNTL1_DPHY0_D0__SI;
typedef union MC_IO_RXCNTL1_DPHY0_D1__CI       regMC_IO_RXCNTL1_DPHY0_D1__CI;
typedef union MC_IO_RXCNTL1_DPHY0_D1__SI       regMC_IO_RXCNTL1_DPHY0_D1__SI;
typedef union MC_IO_RXCNTL1_DPHY1_D0__CI       regMC_IO_RXCNTL1_DPHY1_D0__CI;
typedef union MC_IO_RXCNTL1_DPHY1_D0__SI       regMC_IO_RXCNTL1_DPHY1_D0__SI;
typedef union MC_IO_RXCNTL1_DPHY1_D1__CI       regMC_IO_RXCNTL1_DPHY1_D1__CI;
typedef union MC_IO_RXCNTL1_DPHY1_D1__SI       regMC_IO_RXCNTL1_DPHY1_D1__SI;
typedef union MC_IO_RXCNTL_DPHY0_D0__SI__CI    regMC_IO_RXCNTL_DPHY0_D0__SI__CI;
typedef union MC_IO_RXCNTL_DPHY0_D1__SI__CI    regMC_IO_RXCNTL_DPHY0_D1__SI__CI;
typedef union MC_IO_RXCNTL_DPHY1_D0__SI__CI    regMC_IO_RXCNTL_DPHY1_D0__SI__CI;
typedef union MC_IO_RXCNTL_DPHY1_D1__SI__CI    regMC_IO_RXCNTL_DPHY1_D1__SI__CI;
typedef union MC_IO_TXCNTL_APHY_D0__SI__CI     regMC_IO_TXCNTL_APHY_D0__SI__CI;
typedef union MC_IO_TXCNTL_APHY_D1__SI__CI     regMC_IO_TXCNTL_APHY_D1__SI__CI;
typedef union MC_IO_TXCNTL_DPHY0_D0__SI__CI    regMC_IO_TXCNTL_DPHY0_D0__SI__CI;
typedef union MC_IO_TXCNTL_DPHY0_D1__SI__CI    regMC_IO_TXCNTL_DPHY0_D1__SI__CI;
typedef union MC_IO_TXCNTL_DPHY1_D0__SI__CI    regMC_IO_TXCNTL_DPHY1_D0__SI__CI;
typedef union MC_IO_TXCNTL_DPHY1_D1__SI__CI    regMC_IO_TXCNTL_DPHY1_D1__SI__CI;
typedef union MC_MCBVM_PERFCOUNTER0_CFG__CI__VI regMC_MCBVM_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_MCBVM_PERFCOUNTER1_CFG__CI__VI regMC_MCBVM_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_MCBVM_PERFCOUNTER2_CFG__CI__VI regMC_MCBVM_PERFCOUNTER2_CFG__CI__VI;
typedef union MC_MCBVM_PERFCOUNTER3_CFG__CI__VI regMC_MCBVM_PERFCOUNTER3_CFG__CI__VI;
typedef union MC_MCBVM_PERFCOUNTER_HI__CI__VI  regMC_MCBVM_PERFCOUNTER_HI__CI__VI;
typedef union MC_MCBVM_PERFCOUNTER_LO__CI__VI  regMC_MCBVM_PERFCOUNTER_LO__CI__VI;
typedef union MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_MCBVM_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER0_CFG__CI__VI regMC_MCDVM_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER1_CFG__CI__VI regMC_MCDVM_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER2_CFG__CI__VI regMC_MCDVM_PERFCOUNTER2_CFG__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER3_CFG__CI__VI regMC_MCDVM_PERFCOUNTER3_CFG__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER_HI__CI__VI  regMC_MCDVM_PERFCOUNTER_HI__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER_LO__CI__VI  regMC_MCDVM_PERFCOUNTER_LO__CI__VI;
typedef union MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_MCDVM_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_MEM_POWER_LS                  regMC_MEM_POWER_LS;
typedef union MC_NPL_STATUS__SI__CI            regMC_NPL_STATUS__SI__CI;
typedef union MC_PHY_TIMING_2__SI__CI          regMC_PHY_TIMING_2__SI__CI;
typedef union MC_PHY_TIMING_D0__SI__CI         regMC_PHY_TIMING_D0__SI__CI;
typedef union MC_PHY_TIMING_D1__SI__CI         regMC_PHY_TIMING_D1__SI__CI;
typedef union MC_PMG_AUTO_CFG__SI__CI          regMC_PMG_AUTO_CFG__SI__CI;
typedef union MC_PMG_AUTO_CMD__SI__CI          regMC_PMG_AUTO_CMD__SI__CI;
typedef union MC_PMG_CFG__SI__CI               regMC_PMG_CFG__SI__CI;
typedef union MC_PMG_CFG__VI                   regMC_PMG_CFG__VI;
typedef union MC_PMG_CMD_EMRS__SI__CI          regMC_PMG_CMD_EMRS__SI__CI;
typedef union MC_PMG_CMD_EMRS__VI              regMC_PMG_CMD_EMRS__VI;
typedef union MC_PMG_CMD_MRS__SI__CI           regMC_PMG_CMD_MRS__SI__CI;
typedef union MC_PMG_CMD_MRS__VI               regMC_PMG_CMD_MRS__VI;
typedef union MC_PMG_CMD_MRS1__SI__CI          regMC_PMG_CMD_MRS1__SI__CI;
typedef union MC_PMG_CMD_MRS1__VI              regMC_PMG_CMD_MRS1__VI;
typedef union MC_PMG_CMD_MRS2__SI__CI          regMC_PMG_CMD_MRS2__SI__CI;
typedef union MC_PMG_CMD_MRS2__VI              regMC_PMG_CMD_MRS2__VI;
typedef union MC_RD_CB                         regMC_RD_CB;
typedef union MC_RD_DB                         regMC_RD_DB;
typedef union MC_RD_GRP_EXT                    regMC_RD_GRP_EXT;
typedef union MC_RD_GRP_GFX__CI                regMC_RD_GRP_GFX__CI;
typedef union MC_RD_GRP_GFX__VI                regMC_RD_GRP_GFX__VI;
typedef union MC_RD_GRP_GFX__SI                regMC_RD_GRP_GFX__SI;
typedef union MC_RD_GRP_LCL                    regMC_RD_GRP_LCL;
typedef union MC_RD_GRP_OTH__CI                regMC_RD_GRP_OTH__CI;
typedef union MC_RD_GRP_OTH__VI                regMC_RD_GRP_OTH__VI;
typedef union MC_RD_GRP_OTH__SI                regMC_RD_GRP_OTH__SI;
typedef union MC_RD_GRP_SYS__CI__VI            regMC_RD_GRP_SYS__CI__VI;
typedef union MC_RD_GRP_SYS__SI                regMC_RD_GRP_SYS__SI;
typedef union MC_RD_HUB                        regMC_RD_HUB;
typedef union MC_RD_TC0                        regMC_RD_TC0;
typedef union MC_RD_TC1                        regMC_RD_TC1;
typedef union MC_RPB_ARB_CNTL                  regMC_RPB_ARB_CNTL;
typedef union MC_RPB_BIF_CNTL                  regMC_RPB_BIF_CNTL;
typedef union MC_RPB_CID_QUEUE_EX              regMC_RPB_CID_QUEUE_EX;
typedef union MC_RPB_CID_QUEUE_EX_DATA         regMC_RPB_CID_QUEUE_EX_DATA;
typedef union MC_RPB_CID_QUEUE_RD              regMC_RPB_CID_QUEUE_RD;
typedef union MC_RPB_CID_QUEUE_WR              regMC_RPB_CID_QUEUE_WR;
typedef union MC_RPB_CONF                      regMC_RPB_CONF;
typedef union MC_RPB_DBG1                      regMC_RPB_DBG1;
typedef union MC_RPB_EFF_CNTL                  regMC_RPB_EFF_CNTL;
typedef union MC_RPB_IF_CONF                   regMC_RPB_IF_CONF;
typedef union MC_RPB_PERFCOUNTER0_CFG__CI__VI  regMC_RPB_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_RPB_PERFCOUNTER1_CFG__CI__VI  regMC_RPB_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_RPB_PERFCOUNTER2_CFG__CI__VI  regMC_RPB_PERFCOUNTER2_CFG__CI__VI;
typedef union MC_RPB_PERFCOUNTER3_CFG__CI__VI  regMC_RPB_PERFCOUNTER3_CFG__CI__VI;
typedef union MC_RPB_PERFCOUNTER_HI__CI__VI    regMC_RPB_PERFCOUNTER_HI__CI__VI;
typedef union MC_RPB_PERFCOUNTER_LO__CI__VI    regMC_RPB_PERFCOUNTER_LO__CI__VI;
typedef union MC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_RPB_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_RPB_PERF_COUNTER_CNTL         regMC_RPB_PERF_COUNTER_CNTL;
typedef union MC_RPB_PERF_COUNTER_STATUS       regMC_RPB_PERF_COUNTER_STATUS;
typedef union MC_RPB_RD_SWITCH_CNTL            regMC_RPB_RD_SWITCH_CNTL;
typedef union MC_RPB_WR_COMBINE_CNTL           regMC_RPB_WR_COMBINE_CNTL;
typedef union MC_RPB_WR_SWITCH_CNTL            regMC_RPB_WR_SWITCH_CNTL;
typedef union MC_SEQ_BIT_REMAP_B0_D0__SI__CI   regMC_SEQ_BIT_REMAP_B0_D0__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B0_D1__SI__CI   regMC_SEQ_BIT_REMAP_B0_D1__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B1_D0__SI__CI   regMC_SEQ_BIT_REMAP_B1_D0__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B1_D1__SI__CI   regMC_SEQ_BIT_REMAP_B1_D1__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B2_D0__SI__CI   regMC_SEQ_BIT_REMAP_B2_D0__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B2_D1__SI__CI   regMC_SEQ_BIT_REMAP_B2_D1__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B3_D0__SI__CI   regMC_SEQ_BIT_REMAP_B3_D0__SI__CI;
typedef union MC_SEQ_BIT_REMAP_B3_D1__SI__CI   regMC_SEQ_BIT_REMAP_B3_D1__SI__CI;
typedef union MC_SEQ_BYTE_REMAP_D0__SI__CI     regMC_SEQ_BYTE_REMAP_D0__SI__CI;
typedef union MC_SEQ_BYTE_REMAP_D1__SI__CI     regMC_SEQ_BYTE_REMAP_D1__SI__CI;
typedef union MC_SEQ_CAS_TIMING__SI__CI        regMC_SEQ_CAS_TIMING__SI__CI;
typedef union MC_SEQ_CAS_TIMING__VI            regMC_SEQ_CAS_TIMING__VI;
typedef union MC_SEQ_CAS_TIMING_LP__SI__CI     regMC_SEQ_CAS_TIMING_LP__SI__CI;
typedef union MC_SEQ_CAS_TIMING_LP__VI         regMC_SEQ_CAS_TIMING_LP__VI;
typedef union MC_SEQ_CG                        regMC_SEQ_CG;
typedef union MC_SEQ_CMD__SI__CI               regMC_SEQ_CMD__SI__CI;
typedef union MC_SEQ_CMD__VI                   regMC_SEQ_CMD__VI;
typedef union MC_SEQ_CNTL__SI__CI              regMC_SEQ_CNTL__SI__CI;
typedef union MC_SEQ_CNTL__VI                  regMC_SEQ_CNTL__VI;
typedef union MC_SEQ_CNTL_2__CI                regMC_SEQ_CNTL_2__CI;
typedef union MC_SEQ_CNTL_2__VI                regMC_SEQ_CNTL_2__VI;
typedef union MC_SEQ_CNTL_2__SI                regMC_SEQ_CNTL_2__SI;
typedef union MC_SEQ_CNTL_3__CI                regMC_SEQ_CNTL_3__CI;
typedef union MC_SEQ_CNTL_3__VI                regMC_SEQ_CNTL_3__VI;
typedef union MC_SEQ_DLL_STBY_LP__CI           regMC_SEQ_DLL_STBY_LP__CI;
typedef union MC_SEQ_DLL_STBY__CI              regMC_SEQ_DLL_STBY__CI;
typedef union MC_SEQ_DRAM__SI__CI              regMC_SEQ_DRAM__SI__CI;
typedef union MC_SEQ_DRAM__VI                  regMC_SEQ_DRAM__VI;
typedef union MC_SEQ_DRAM_2__SI__CI            regMC_SEQ_DRAM_2__SI__CI;
typedef union MC_SEQ_DRAM_2__VI                regMC_SEQ_DRAM_2__VI;
typedef union MC_SEQ_DRAM_ERROR_INSERTION__SI__CI regMC_SEQ_DRAM_ERROR_INSERTION__SI__CI;
typedef union MC_SEQ_FIFO_CTL__SI__CI          regMC_SEQ_FIFO_CTL__SI__CI;
typedef union MC_SEQ_FIFO_CTL__VI              regMC_SEQ_FIFO_CTL__VI;
typedef union MC_SEQ_G5PDX_CMD0_LP__CI         regMC_SEQ_G5PDX_CMD0_LP__CI;
typedef union MC_SEQ_G5PDX_CMD0__CI            regMC_SEQ_G5PDX_CMD0__CI;
typedef union MC_SEQ_G5PDX_CMD1_LP__CI         regMC_SEQ_G5PDX_CMD1_LP__CI;
typedef union MC_SEQ_G5PDX_CMD1__CI            regMC_SEQ_G5PDX_CMD1__CI;
typedef union MC_SEQ_G5PDX_CTRL_LP__CI         regMC_SEQ_G5PDX_CTRL_LP__CI;
typedef union MC_SEQ_G5PDX_CTRL__CI            regMC_SEQ_G5PDX_CTRL__CI;
typedef union MC_SEQ_IO_DEBUG_DATA             regMC_SEQ_IO_DEBUG_DATA;
typedef union MC_SEQ_IO_DEBUG_INDEX            regMC_SEQ_IO_DEBUG_INDEX;
typedef union MC_SEQ_IO_RDBI__SI__CI           regMC_SEQ_IO_RDBI__SI__CI;
typedef union MC_SEQ_IO_REDC__SI__CI           regMC_SEQ_IO_REDC__SI__CI;
typedef union MC_SEQ_IO_RESERVE_D0__SI__CI     regMC_SEQ_IO_RESERVE_D0__SI__CI;
typedef union MC_SEQ_IO_RESERVE_D1__SI__CI     regMC_SEQ_IO_RESERVE_D1__SI__CI;
typedef union MC_SEQ_IO_RWORD0__SI__CI         regMC_SEQ_IO_RWORD0__SI__CI;
typedef union MC_SEQ_IO_RWORD1__SI__CI         regMC_SEQ_IO_RWORD1__SI__CI;
typedef union MC_SEQ_IO_RWORD2__SI__CI         regMC_SEQ_IO_RWORD2__SI__CI;
typedef union MC_SEQ_IO_RWORD3__SI__CI         regMC_SEQ_IO_RWORD3__SI__CI;
typedef union MC_SEQ_IO_RWORD4__SI__CI         regMC_SEQ_IO_RWORD4__SI__CI;
typedef union MC_SEQ_IO_RWORD5__SI__CI         regMC_SEQ_IO_RWORD5__SI__CI;
typedef union MC_SEQ_IO_RWORD6__SI__CI         regMC_SEQ_IO_RWORD6__SI__CI;
typedef union MC_SEQ_IO_RWORD7__SI__CI         regMC_SEQ_IO_RWORD7__SI__CI;
typedef union MC_SEQ_MISC0                     regMC_SEQ_MISC0;
typedef union MC_SEQ_MISC1                     regMC_SEQ_MISC1;
typedef union MC_SEQ_MISC3                     regMC_SEQ_MISC3;
typedef union MC_SEQ_MISC4                     regMC_SEQ_MISC4;
typedef union MC_SEQ_MISC5                     regMC_SEQ_MISC5;
typedef union MC_SEQ_MISC6                     regMC_SEQ_MISC6;
typedef union MC_SEQ_MISC7                     regMC_SEQ_MISC7;
typedef union MC_SEQ_MISC8                     regMC_SEQ_MISC8;
typedef union MC_SEQ_MISC9                     regMC_SEQ_MISC9;
typedef union MC_SEQ_MISC_TIMING__SI__CI       regMC_SEQ_MISC_TIMING__SI__CI;
typedef union MC_SEQ_MISC_TIMING__VI           regMC_SEQ_MISC_TIMING__VI;
typedef union MC_SEQ_MISC_TIMING2__SI__CI      regMC_SEQ_MISC_TIMING2__SI__CI;
typedef union MC_SEQ_MISC_TIMING2__VI          regMC_SEQ_MISC_TIMING2__VI;
typedef union MC_SEQ_MISC_TIMING2_LP__SI__CI   regMC_SEQ_MISC_TIMING2_LP__SI__CI;
typedef union MC_SEQ_MISC_TIMING2_LP__VI       regMC_SEQ_MISC_TIMING2_LP__VI;
typedef union MC_SEQ_MISC_TIMING_LP__SI__CI    regMC_SEQ_MISC_TIMING_LP__SI__CI;
typedef union MC_SEQ_MISC_TIMING_LP__VI        regMC_SEQ_MISC_TIMING_LP__VI;
typedef union MC_SEQ_MPLL_OVERRIDE__SI__CI     regMC_SEQ_MPLL_OVERRIDE__SI__CI;
typedef union MC_SEQ_PERF_CNTL__SI__CI         regMC_SEQ_PERF_CNTL__SI__CI;
typedef union MC_SEQ_PERF_CNTL_1__SI__CI       regMC_SEQ_PERF_CNTL_1__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_A_I0__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_A_I1__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_B_I0__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_B_I1__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_C_I0__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_C_I1__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI regMC_SEQ_PERF_SEQ_CNT_D_I0__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI regMC_SEQ_PERF_SEQ_CNT_D_I1__SI__CI;
typedef union MC_SEQ_PERF_SEQ_CTL__SI__CI      regMC_SEQ_PERF_SEQ_CTL__SI__CI;
typedef union MC_SEQ_PHYREG_BCAST__CI          regMC_SEQ_PHYREG_BCAST__CI;
typedef union MC_SEQ_PMG_CMD_EMRS_LP__SI__CI   regMC_SEQ_PMG_CMD_EMRS_LP__SI__CI;
typedef union MC_SEQ_PMG_CMD_MRS1_LP__SI__CI   regMC_SEQ_PMG_CMD_MRS1_LP__SI__CI;
typedef union MC_SEQ_PMG_CMD_MRS2_LP__SI__CI   regMC_SEQ_PMG_CMD_MRS2_LP__SI__CI;
typedef union MC_SEQ_PMG_CMD_MRS_LP__SI__CI    regMC_SEQ_PMG_CMD_MRS_LP__SI__CI;
typedef union MC_SEQ_PMG_DVS_CMD_LP__CI        regMC_SEQ_PMG_DVS_CMD_LP__CI;
typedef union MC_SEQ_PMG_DVS_CMD__CI           regMC_SEQ_PMG_DVS_CMD__CI;
typedef union MC_SEQ_PMG_DVS_CTL_LP__CI        regMC_SEQ_PMG_DVS_CTL_LP__CI;
typedef union MC_SEQ_PMG_DVS_CTL__CI           regMC_SEQ_PMG_DVS_CTL__CI;
typedef union MC_SEQ_PMG_PG_HWCNTL__SI__CI     regMC_SEQ_PMG_PG_HWCNTL__SI__CI;
typedef union MC_SEQ_PMG_PG_SWCNTL_0__SI__CI   regMC_SEQ_PMG_PG_SWCNTL_0__SI__CI;
typedef union MC_SEQ_PMG_PG_SWCNTL_1__SI__CI   regMC_SEQ_PMG_PG_SWCNTL_1__SI__CI;
typedef union MC_SEQ_PMG_TIMING__SI__CI        regMC_SEQ_PMG_TIMING__SI__CI;
typedef union MC_SEQ_PMG_TIMING__VI            regMC_SEQ_PMG_TIMING__VI;
typedef union MC_SEQ_PMG_TIMING_LP__SI__CI     regMC_SEQ_PMG_TIMING_LP__SI__CI;
typedef union MC_SEQ_PMG_TIMING_LP__VI         regMC_SEQ_PMG_TIMING_LP__VI;
typedef union MC_SEQ_RAS_TIMING                regMC_SEQ_RAS_TIMING;
typedef union MC_SEQ_RAS_TIMING_LP             regMC_SEQ_RAS_TIMING_LP;
typedef union MC_SEQ_RD_CTL_D0__SI__CI         regMC_SEQ_RD_CTL_D0__SI__CI;
typedef union MC_SEQ_RD_CTL_D0__VI             regMC_SEQ_RD_CTL_D0__VI;
typedef union MC_SEQ_RD_CTL_D0_LP__SI__CI      regMC_SEQ_RD_CTL_D0_LP__SI__CI;
typedef union MC_SEQ_RD_CTL_D0_LP__VI          regMC_SEQ_RD_CTL_D0_LP__VI;
typedef union MC_SEQ_RD_CTL_D1__SI__CI         regMC_SEQ_RD_CTL_D1__SI__CI;
typedef union MC_SEQ_RD_CTL_D1__VI             regMC_SEQ_RD_CTL_D1__VI;
typedef union MC_SEQ_RD_CTL_D1_LP__SI__CI      regMC_SEQ_RD_CTL_D1_LP__SI__CI;
typedef union MC_SEQ_RD_CTL_D1_LP__VI          regMC_SEQ_RD_CTL_D1_LP__VI;
typedef union MC_SEQ_RESERVE_0_S               regMC_SEQ_RESERVE_0_S;
typedef union MC_SEQ_RESERVE_1_S               regMC_SEQ_RESERVE_1_S;
typedef union MC_SEQ_RESERVE_M                 regMC_SEQ_RESERVE_M;
typedef union MC_SEQ_RXFRAMING_BYTE0_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE0_D0__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE0_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE0_D1__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE1_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE1_D0__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE1_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE1_D1__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE2_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE2_D0__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE2_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE2_D1__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE3_D0__SI__CI regMC_SEQ_RXFRAMING_BYTE3_D0__SI__CI;
typedef union MC_SEQ_RXFRAMING_BYTE3_D1__SI__CI regMC_SEQ_RXFRAMING_BYTE3_D1__SI__CI;
typedef union MC_SEQ_RXFRAMING_DBI_D0__SI__CI  regMC_SEQ_RXFRAMING_DBI_D0__SI__CI;
typedef union MC_SEQ_RXFRAMING_DBI_D1__SI__CI  regMC_SEQ_RXFRAMING_DBI_D1__SI__CI;
typedef union MC_SEQ_RXFRAMING_EDC_D0__SI__CI  regMC_SEQ_RXFRAMING_EDC_D0__SI__CI;
typedef union MC_SEQ_RXFRAMING_EDC_D1__SI__CI  regMC_SEQ_RXFRAMING_EDC_D1__SI__CI;
typedef union MC_SEQ_SREG_READ__CI__VI         regMC_SEQ_SREG_READ__CI__VI;
typedef union MC_SEQ_SREG_STATUS__CI__VI       regMC_SEQ_SREG_STATUS__CI__VI;
typedef union MC_SEQ_STATUS_M__SI__CI          regMC_SEQ_STATUS_M__SI__CI;
typedef union MC_SEQ_STATUS_M__VI              regMC_SEQ_STATUS_M__VI;
typedef union MC_SEQ_STATUS_S                  regMC_SEQ_STATUS_S;
typedef union MC_SEQ_SUP_CNTL__SI__CI          regMC_SEQ_SUP_CNTL__SI__CI;
typedef union MC_SEQ_SUP_CNTL__VI              regMC_SEQ_SUP_CNTL__VI;
typedef union MC_SEQ_SUP_DEC_STAT              regMC_SEQ_SUP_DEC_STAT;
typedef union MC_SEQ_SUP_GP0_STAT              regMC_SEQ_SUP_GP0_STAT;
typedef union MC_SEQ_SUP_GP1_STAT              regMC_SEQ_SUP_GP1_STAT;
typedef union MC_SEQ_SUP_GP2_STAT              regMC_SEQ_SUP_GP2_STAT;
typedef union MC_SEQ_SUP_GP3_STAT              regMC_SEQ_SUP_GP3_STAT;
typedef union MC_SEQ_SUP_IR_STAT               regMC_SEQ_SUP_IR_STAT;
typedef union MC_SEQ_SUP_PGM                   regMC_SEQ_SUP_PGM;
typedef union MC_SEQ_SUP_PGM_STAT              regMC_SEQ_SUP_PGM_STAT;
typedef union MC_SEQ_SUP_R_PGM                 regMC_SEQ_SUP_R_PGM;
typedef union MC_SEQ_TCG_CNTL__SI__CI          regMC_SEQ_TCG_CNTL__SI__CI;
typedef union MC_SEQ_TIMER_RD                  regMC_SEQ_TIMER_RD;
typedef union MC_SEQ_TIMER_WR                  regMC_SEQ_TIMER_WR;
typedef union MC_SEQ_TRAIN_CAPTURE__SI__CI     regMC_SEQ_TRAIN_CAPTURE__SI__CI;
typedef union MC_SEQ_TRAIN_CAPTURE__VI         regMC_SEQ_TRAIN_CAPTURE__VI;
typedef union MC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI regMC_SEQ_TRAIN_EDC_THRESHOLD__SI__CI;
typedef union MC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI regMC_SEQ_TRAIN_EDC_THRESHOLD2__SI__CI;
typedef union MC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI regMC_SEQ_TRAIN_EDC_THRESHOLD3__SI__CI;
typedef union MC_SEQ_TRAIN_TIMING__SI__CI      regMC_SEQ_TRAIN_TIMING__SI__CI;
typedef union MC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI regMC_SEQ_TRAIN_WAKEUP_CLEAR__SI__CI;
typedef union MC_SEQ_TRAIN_WAKEUP_CLEAR__VI    regMC_SEQ_TRAIN_WAKEUP_CLEAR__VI;
typedef union MC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI regMC_SEQ_TRAIN_WAKEUP_CNTL__SI__CI;
typedef union MC_SEQ_TRAIN_WAKEUP_CNTL__VI     regMC_SEQ_TRAIN_WAKEUP_CNTL__VI;
typedef union MC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI regMC_SEQ_TRAIN_WAKEUP_EDGE__SI__CI;
typedef union MC_SEQ_TRAIN_WAKEUP_EDGE__VI     regMC_SEQ_TRAIN_WAKEUP_EDGE__VI;
typedef union MC_SEQ_TRAIN_WAKEUP_MASK__SI__CI regMC_SEQ_TRAIN_WAKEUP_MASK__SI__CI;
typedef union MC_SEQ_TRAIN_WAKEUP_MASK__VI     regMC_SEQ_TRAIN_WAKEUP_MASK__VI;
typedef union MC_SEQ_TSM_BCNT__SI__CI          regMC_SEQ_TSM_BCNT__SI__CI;
typedef union MC_SEQ_TSM_CTRL__SI__CI          regMC_SEQ_TSM_CTRL__SI__CI;
typedef union MC_SEQ_TSM_DBI__SI__CI           regMC_SEQ_TSM_DBI__SI__CI;
typedef union MC_SEQ_TSM_DEBUG_DATA__SI__CI    regMC_SEQ_TSM_DEBUG_DATA__SI__CI;
typedef union MC_SEQ_TSM_DEBUG_INDEX__SI__CI   regMC_SEQ_TSM_DEBUG_INDEX__SI__CI;
typedef union MC_SEQ_TSM_EDC__SI__CI           regMC_SEQ_TSM_EDC__SI__CI;
typedef union MC_SEQ_TSM_FLAG__SI__CI          regMC_SEQ_TSM_FLAG__SI__CI;
typedef union MC_SEQ_TSM_GCNT__SI__CI          regMC_SEQ_TSM_GCNT__SI__CI;
typedef union MC_SEQ_TSM_MISC__SI__CI          regMC_SEQ_TSM_MISC__SI__CI;
typedef union MC_SEQ_TSM_NCNT__SI__CI          regMC_SEQ_TSM_NCNT__SI__CI;
typedef union MC_SEQ_TSM_OCNT__SI__CI          regMC_SEQ_TSM_OCNT__SI__CI;
typedef union MC_SEQ_TSM_UPDATE__SI__CI        regMC_SEQ_TSM_UPDATE__SI__CI;
typedef union MC_SEQ_TSM_WCDR__SI__CI          regMC_SEQ_TSM_WCDR__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE0_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE0_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE0_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE0_D1__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE1_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE1_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE1_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE1_D1__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE2_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE2_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE2_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE2_D1__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE3_D0__SI__CI regMC_SEQ_TXFRAMING_BYTE3_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_BYTE3_D1__SI__CI regMC_SEQ_TXFRAMING_BYTE3_D1__SI__CI;
typedef union MC_SEQ_TXFRAMING_DBI_D0__SI__CI  regMC_SEQ_TXFRAMING_DBI_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_DBI_D1__SI__CI  regMC_SEQ_TXFRAMING_DBI_D1__SI__CI;
typedef union MC_SEQ_TXFRAMING_EDC_D0__SI__CI  regMC_SEQ_TXFRAMING_EDC_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_EDC_D1__SI__CI  regMC_SEQ_TXFRAMING_EDC_D1__SI__CI;
typedef union MC_SEQ_TXFRAMING_FCK_D0__SI__CI  regMC_SEQ_TXFRAMING_FCK_D0__SI__CI;
typedef union MC_SEQ_TXFRAMING_FCK_D1__SI__CI  regMC_SEQ_TXFRAMING_FCK_D1__SI__CI;
typedef union MC_SEQ_VENDOR_ID_I0__SI__CI      regMC_SEQ_VENDOR_ID_I0__SI__CI;
typedef union MC_SEQ_VENDOR_ID_I1__SI__CI      regMC_SEQ_VENDOR_ID_I1__SI__CI;
typedef union MC_SEQ_WCDR_CTRL__SI__CI         regMC_SEQ_WCDR_CTRL__SI__CI;
typedef union MC_SEQ_WR_CTL_2__SI__CI          regMC_SEQ_WR_CTL_2__SI__CI;
typedef union MC_SEQ_WR_CTL_2_LP__SI__CI       regMC_SEQ_WR_CTL_2_LP__SI__CI;
typedef union MC_SEQ_WR_CTL_D0__SI__CI         regMC_SEQ_WR_CTL_D0__SI__CI;
typedef union MC_SEQ_WR_CTL_D0__VI             regMC_SEQ_WR_CTL_D0__VI;
typedef union MC_SEQ_WR_CTL_D0_LP__SI__CI      regMC_SEQ_WR_CTL_D0_LP__SI__CI;
typedef union MC_SEQ_WR_CTL_D0_LP__VI          regMC_SEQ_WR_CTL_D0_LP__VI;
typedef union MC_SEQ_WR_CTL_D1__SI__CI         regMC_SEQ_WR_CTL_D1__SI__CI;
typedef union MC_SEQ_WR_CTL_D1__VI             regMC_SEQ_WR_CTL_D1__VI;
typedef union MC_SEQ_WR_CTL_D1_LP__SI__CI      regMC_SEQ_WR_CTL_D1_LP__SI__CI;
typedef union MC_SEQ_WR_CTL_D1_LP__VI          regMC_SEQ_WR_CTL_D1_LP__VI;
typedef union MC_SHARED_BLACKOUT_CNTL__SI__CI  regMC_SHARED_BLACKOUT_CNTL__SI__CI;
typedef union MC_SHARED_BLACKOUT_CNTL__VI      regMC_SHARED_BLACKOUT_CNTL__VI;
typedef union MC_SHARED_CHMAP                  regMC_SHARED_CHMAP;
typedef union MC_SHARED_CHREMAP__SI__CI        regMC_SHARED_CHREMAP__SI__CI;
typedef union MC_SHARED_CHREMAP__VI            regMC_SHARED_CHREMAP__VI;
typedef union MC_TRAIN_EDCCDR_R_D0__SI__CI     regMC_TRAIN_EDCCDR_R_D0__SI__CI;
typedef union MC_TRAIN_EDCCDR_R_D1__SI__CI     regMC_TRAIN_EDCCDR_R_D1__SI__CI;
typedef union MC_TRAIN_EDC_STATUS_D0__SI__CI   regMC_TRAIN_EDC_STATUS_D0__SI__CI;
typedef union MC_TRAIN_EDC_STATUS_D1__SI__CI   regMC_TRAIN_EDC_STATUS_D1__SI__CI;
typedef union MC_TRAIN_PRBSERR_0_D0__SI__CI    regMC_TRAIN_PRBSERR_0_D0__SI__CI;
typedef union MC_TRAIN_PRBSERR_0_D1__SI__CI    regMC_TRAIN_PRBSERR_0_D1__SI__CI;
typedef union MC_TRAIN_PRBSERR_1_D0__SI__CI    regMC_TRAIN_PRBSERR_1_D0__SI__CI;
typedef union MC_TRAIN_PRBSERR_1_D1__SI__CI    regMC_TRAIN_PRBSERR_1_D1__SI__CI;
typedef union MC_TRAIN_PRBSERR_2_D0__SI__CI    regMC_TRAIN_PRBSERR_2_D0__SI__CI;
typedef union MC_TRAIN_PRBSERR_2_D1__SI__CI    regMC_TRAIN_PRBSERR_2_D1__SI__CI;
typedef union MC_TSM_DEBUG_BCNT0__SI__CI       regMC_TSM_DEBUG_BCNT0__SI__CI;
typedef union MC_TSM_DEBUG_BCNT1__SI__CI       regMC_TSM_DEBUG_BCNT1__SI__CI;
typedef union MC_TSM_DEBUG_BCNT10__SI__CI      regMC_TSM_DEBUG_BCNT10__SI__CI;
typedef union MC_TSM_DEBUG_BCNT2__SI__CI       regMC_TSM_DEBUG_BCNT2__SI__CI;
typedef union MC_TSM_DEBUG_BCNT3__SI__CI       regMC_TSM_DEBUG_BCNT3__SI__CI;
typedef union MC_TSM_DEBUG_BCNT4__SI__CI       regMC_TSM_DEBUG_BCNT4__SI__CI;
typedef union MC_TSM_DEBUG_BCNT5__SI__CI       regMC_TSM_DEBUG_BCNT5__SI__CI;
typedef union MC_TSM_DEBUG_BCNT6__SI__CI       regMC_TSM_DEBUG_BCNT6__SI__CI;
typedef union MC_TSM_DEBUG_BCNT7__SI__CI       regMC_TSM_DEBUG_BCNT7__SI__CI;
typedef union MC_TSM_DEBUG_BCNT8__SI__CI       regMC_TSM_DEBUG_BCNT8__SI__CI;
typedef union MC_TSM_DEBUG_BCNT9__SI__CI       regMC_TSM_DEBUG_BCNT9__SI__CI;
typedef union MC_TSM_DEBUG_BKPT__SI__CI        regMC_TSM_DEBUG_BKPT__SI__CI;
typedef union MC_TSM_DEBUG_FLAG__SI__CI        regMC_TSM_DEBUG_FLAG__SI__CI;
typedef union MC_TSM_DEBUG_GCNT__SI__CI        regMC_TSM_DEBUG_GCNT__SI__CI;
typedef union MC_TSM_DEBUG_MISC__SI__CI        regMC_TSM_DEBUG_MISC__SI__CI;
typedef union MC_TSM_DEBUG_ST01__SI__CI        regMC_TSM_DEBUG_ST01__SI__CI;
typedef union MC_TSM_DEBUG_ST23__SI__CI        regMC_TSM_DEBUG_ST23__SI__CI;
typedef union MC_TSM_DEBUG_ST45__SI__CI        regMC_TSM_DEBUG_ST45__SI__CI;
typedef union MC_VM_AGP_BASE                   regMC_VM_AGP_BASE;
typedef union MC_VM_AGP_BOT                    regMC_VM_AGP_BOT;
typedef union MC_VM_AGP_TOP                    regMC_VM_AGP_TOP;
typedef union MC_VM_DC_WRITE_CNTL              regMC_VM_DC_WRITE_CNTL;
typedef union MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR regMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR;
typedef union MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR regMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR;
typedef union MC_VM_FB_LOCATION                regMC_VM_FB_LOCATION;
typedef union MC_VM_FB_OFFSET                  regMC_VM_FB_OFFSET;
typedef union MC_VM_L2_PERFCOUNTER0_CFG__CI__VI regMC_VM_L2_PERFCOUNTER0_CFG__CI__VI;
typedef union MC_VM_L2_PERFCOUNTER1_CFG__CI__VI regMC_VM_L2_PERFCOUNTER1_CFG__CI__VI;
typedef union MC_VM_L2_PERFCOUNTER_HI__CI__VI  regMC_VM_L2_PERFCOUNTER_HI__CI__VI;
typedef union MC_VM_L2_PERFCOUNTER_LO__CI__VI  regMC_VM_L2_PERFCOUNTER_LO__CI__VI;
typedef union MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI regMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CI__VI;
typedef union MC_VM_MB_L1_TLB0_DEBUG           regMC_VM_MB_L1_TLB0_DEBUG;
typedef union MC_VM_MB_L1_TLB0_STATUS          regMC_VM_MB_L1_TLB0_STATUS;
typedef union MC_VM_MB_L1_TLB1_STATUS          regMC_VM_MB_L1_TLB1_STATUS;
typedef union MC_VM_MB_L1_TLB2_DEBUG           regMC_VM_MB_L1_TLB2_DEBUG;
typedef union MC_VM_MB_L1_TLB2_STATUS          regMC_VM_MB_L1_TLB2_STATUS;
typedef union MC_VM_MB_L1_TLB3_DEBUG           regMC_VM_MB_L1_TLB3_DEBUG;
typedef union MC_VM_MB_L1_TLB3_STATUS          regMC_VM_MB_L1_TLB3_STATUS;
typedef union MC_VM_MB_L2ARBITER_L2_CREDITS    regMC_VM_MB_L2ARBITER_L2_CREDITS;
typedef union MC_VM_MD_L1_TLB0_DEBUG           regMC_VM_MD_L1_TLB0_DEBUG;
typedef union MC_VM_MD_L1_TLB0_STATUS          regMC_VM_MD_L1_TLB0_STATUS;
typedef union MC_VM_MD_L1_TLB1_DEBUG           regMC_VM_MD_L1_TLB1_DEBUG;
typedef union MC_VM_MD_L1_TLB1_STATUS          regMC_VM_MD_L1_TLB1_STATUS;
typedef union MC_VM_MD_L1_TLB2_DEBUG           regMC_VM_MD_L1_TLB2_DEBUG;
typedef union MC_VM_MD_L1_TLB2_STATUS          regMC_VM_MD_L1_TLB2_STATUS;
typedef union MC_VM_MD_L1_TLB3_DEBUG           regMC_VM_MD_L1_TLB3_DEBUG;
typedef union MC_VM_MD_L1_TLB3_STATUS          regMC_VM_MD_L1_TLB3_STATUS;
typedef union MC_VM_MD_L2ARBITER_L2_CREDITS    regMC_VM_MD_L2ARBITER_L2_CREDITS;
typedef union MC_VM_MX_L1_TLB_CNTL             regMC_VM_MX_L1_TLB_CNTL;
typedef union MC_VM_STEERING__CI__VI           regMC_VM_STEERING__CI__VI;
typedef union MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR;
typedef union MC_VM_SYSTEM_APERTURE_HIGH_ADDR  regMC_VM_SYSTEM_APERTURE_HIGH_ADDR;
typedef union MC_VM_SYSTEM_APERTURE_LOW_ADDR   regMC_VM_SYSTEM_APERTURE_LOW_ADDR;
typedef union MC_WR_CB                         regMC_WR_CB;
typedef union MC_WR_DB                         regMC_WR_DB;
typedef union MC_WR_GRP_EXT                    regMC_WR_GRP_EXT;
typedef union MC_WR_GRP_GFX__CI                regMC_WR_GRP_GFX__CI;
typedef union MC_WR_GRP_GFX__VI                regMC_WR_GRP_GFX__VI;
typedef union MC_WR_GRP_GFX__SI                regMC_WR_GRP_GFX__SI;
typedef union MC_WR_GRP_LCL                    regMC_WR_GRP_LCL;
typedef union MC_WR_GRP_OTH__CI__VI            regMC_WR_GRP_OTH__CI__VI;
typedef union MC_WR_GRP_OTH__SI                regMC_WR_GRP_OTH__SI;
typedef union MC_WR_GRP_SYS__CI                regMC_WR_GRP_SYS__CI;
typedef union MC_WR_GRP_SYS__VI                regMC_WR_GRP_SYS__VI;
typedef union MC_WR_GRP_SYS__SI                regMC_WR_GRP_SYS__SI;
typedef union MC_WR_HUB                        regMC_WR_HUB;
typedef union MC_WR_TC0                        regMC_WR_TC0;
typedef union MC_WR_TC1                        regMC_WR_TC1;
typedef union MC_XBAR_ADDR_DEC                 regMC_XBAR_ADDR_DEC;
typedef union MC_XBAR_ARB                      regMC_XBAR_ARB;
typedef union MC_XBAR_ARB_MAX_BURST            regMC_XBAR_ARB_MAX_BURST;
typedef union MC_XBAR_CHTRIREMAP               regMC_XBAR_CHTRIREMAP;
typedef union MC_XBAR_PERF_MON_CNTL0__SI__CI   regMC_XBAR_PERF_MON_CNTL0__SI__CI;
typedef union MC_XBAR_PERF_MON_CNTL1__SI__CI   regMC_XBAR_PERF_MON_CNTL1__SI__CI;
typedef union MC_XBAR_PERF_MON_CNTL2__SI__CI   regMC_XBAR_PERF_MON_CNTL2__SI__CI;
typedef union MC_XBAR_PERF_MON_MAX_THSH__SI__CI regMC_XBAR_PERF_MON_MAX_THSH__SI__CI;
typedef union MC_XBAR_PERF_MON_RSLT0__SI__CI   regMC_XBAR_PERF_MON_RSLT0__SI__CI;
typedef union MC_XBAR_PERF_MON_RSLT1__SI__CI   regMC_XBAR_PERF_MON_RSLT1__SI__CI;
typedef union MC_XBAR_PERF_MON_RSLT2__SI__CI   regMC_XBAR_PERF_MON_RSLT2__SI__CI;
typedef union MC_XBAR_PERF_MON_RSLT3__SI__CI   regMC_XBAR_PERF_MON_RSLT3__SI__CI;
typedef union MC_XBAR_RDREQ_CREDIT             regMC_XBAR_RDREQ_CREDIT;
typedef union MC_XBAR_RDREQ_PRI_CREDIT         regMC_XBAR_RDREQ_PRI_CREDIT;
typedef union MC_XBAR_RDRET_CREDIT1            regMC_XBAR_RDRET_CREDIT1;
typedef union MC_XBAR_RDRET_CREDIT2            regMC_XBAR_RDRET_CREDIT2;
typedef union MC_XBAR_RDRET_PRI_CREDIT1        regMC_XBAR_RDRET_PRI_CREDIT1;
typedef union MC_XBAR_RDRET_PRI_CREDIT2        regMC_XBAR_RDRET_PRI_CREDIT2;
typedef union MC_XBAR_REMOTE                   regMC_XBAR_REMOTE;
typedef union MC_XBAR_SPARE0                   regMC_XBAR_SPARE0;
typedef union MC_XBAR_SPARE1                   regMC_XBAR_SPARE1;
typedef union MC_XBAR_TWOCHAN                  regMC_XBAR_TWOCHAN;
typedef union MC_XBAR_WRREQ_CREDIT             regMC_XBAR_WRREQ_CREDIT;
typedef union MC_XBAR_WRRET_CREDIT1            regMC_XBAR_WRRET_CREDIT1;
typedef union MC_XBAR_WRRET_CREDIT2            regMC_XBAR_WRRET_CREDIT2;
typedef union MC_XPB_CLG_CFG0                  regMC_XPB_CLG_CFG0;
typedef union MC_XPB_CLG_CFG1                  regMC_XPB_CLG_CFG1;
typedef union MC_XPB_CLG_CFG10                 regMC_XPB_CLG_CFG10;
typedef union MC_XPB_CLG_CFG11                 regMC_XPB_CLG_CFG11;
typedef union MC_XPB_CLG_CFG12                 regMC_XPB_CLG_CFG12;
typedef union MC_XPB_CLG_CFG13                 regMC_XPB_CLG_CFG13;
typedef union MC_XPB_CLG_CFG14                 regMC_XPB_CLG_CFG14;
typedef union MC_XPB_CLG_CFG15                 regMC_XPB_CLG_CFG15;
typedef union MC_XPB_CLG_CFG16                 regMC_XPB_CLG_CFG16;
typedef union MC_XPB_CLG_CFG17                 regMC_XPB_CLG_CFG17;
typedef union MC_XPB_CLG_CFG18                 regMC_XPB_CLG_CFG18;
typedef union MC_XPB_CLG_CFG19                 regMC_XPB_CLG_CFG19;
typedef union MC_XPB_CLG_CFG2                  regMC_XPB_CLG_CFG2;
typedef union MC_XPB_CLG_CFG20                 regMC_XPB_CLG_CFG20;
typedef union MC_XPB_CLG_CFG21                 regMC_XPB_CLG_CFG21;
typedef union MC_XPB_CLG_CFG22                 regMC_XPB_CLG_CFG22;
typedef union MC_XPB_CLG_CFG23                 regMC_XPB_CLG_CFG23;
typedef union MC_XPB_CLG_CFG24                 regMC_XPB_CLG_CFG24;
typedef union MC_XPB_CLG_CFG25                 regMC_XPB_CLG_CFG25;
typedef union MC_XPB_CLG_CFG26                 regMC_XPB_CLG_CFG26;
typedef union MC_XPB_CLG_CFG27                 regMC_XPB_CLG_CFG27;
typedef union MC_XPB_CLG_CFG28                 regMC_XPB_CLG_CFG28;
typedef union MC_XPB_CLG_CFG29                 regMC_XPB_CLG_CFG29;
typedef union MC_XPB_CLG_CFG3                  regMC_XPB_CLG_CFG3;
typedef union MC_XPB_CLG_CFG30                 regMC_XPB_CLG_CFG30;
typedef union MC_XPB_CLG_CFG31                 regMC_XPB_CLG_CFG31;
typedef union MC_XPB_CLG_CFG32                 regMC_XPB_CLG_CFG32;
typedef union MC_XPB_CLG_CFG33                 regMC_XPB_CLG_CFG33;
typedef union MC_XPB_CLG_CFG34                 regMC_XPB_CLG_CFG34;
typedef union MC_XPB_CLG_CFG35                 regMC_XPB_CLG_CFG35;
typedef union MC_XPB_CLG_CFG36                 regMC_XPB_CLG_CFG36;
typedef union MC_XPB_CLG_CFG4                  regMC_XPB_CLG_CFG4;
typedef union MC_XPB_CLG_CFG5                  regMC_XPB_CLG_CFG5;
typedef union MC_XPB_CLG_CFG6                  regMC_XPB_CLG_CFG6;
typedef union MC_XPB_CLG_CFG7                  regMC_XPB_CLG_CFG7;
typedef union MC_XPB_CLG_CFG8                  regMC_XPB_CLG_CFG8;
typedef union MC_XPB_CLG_CFG9                  regMC_XPB_CLG_CFG9;
typedef union MC_XPB_CLG_EXTRA                 regMC_XPB_CLG_EXTRA;
typedef union MC_XPB_CLG_EXTRA_RD              regMC_XPB_CLG_EXTRA_RD;
typedef union MC_XPB_CLK_GAT                   regMC_XPB_CLK_GAT;
typedef union MC_XPB_INTF_CFG                  regMC_XPB_INTF_CFG;
typedef union MC_XPB_INTF_CFG2                 regMC_XPB_INTF_CFG2;
typedef union MC_XPB_INTF_STS                  regMC_XPB_INTF_STS;
typedef union MC_XPB_LB_ADDR                   regMC_XPB_LB_ADDR;
typedef union MC_XPB_MAP_INVERT_FLUSH_NUM_LSB  regMC_XPB_MAP_INVERT_FLUSH_NUM_LSB;
typedef union MC_XPB_MISC_CFG                  regMC_XPB_MISC_CFG;
typedef union MC_XPB_P2P_BAR0                  regMC_XPB_P2P_BAR0;
typedef union MC_XPB_P2P_BAR1                  regMC_XPB_P2P_BAR1;
typedef union MC_XPB_P2P_BAR2                  regMC_XPB_P2P_BAR2;
typedef union MC_XPB_P2P_BAR3                  regMC_XPB_P2P_BAR3;
typedef union MC_XPB_P2P_BAR4                  regMC_XPB_P2P_BAR4;
typedef union MC_XPB_P2P_BAR5                  regMC_XPB_P2P_BAR5;
typedef union MC_XPB_P2P_BAR6                  regMC_XPB_P2P_BAR6;
typedef union MC_XPB_P2P_BAR7                  regMC_XPB_P2P_BAR7;
typedef union MC_XPB_P2P_BAR_CFG               regMC_XPB_P2P_BAR_CFG;
typedef union MC_XPB_P2P_BAR_DEBUG             regMC_XPB_P2P_BAR_DEBUG;
typedef union MC_XPB_P2P_BAR_DELTA_ABOVE       regMC_XPB_P2P_BAR_DELTA_ABOVE;
typedef union MC_XPB_P2P_BAR_DELTA_BELOW       regMC_XPB_P2P_BAR_DELTA_BELOW;
typedef union MC_XPB_P2P_BAR_SETUP             regMC_XPB_P2P_BAR_SETUP;
typedef union MC_XPB_PEER_SYS_BAR0             regMC_XPB_PEER_SYS_BAR0;
typedef union MC_XPB_PEER_SYS_BAR1             regMC_XPB_PEER_SYS_BAR1;
typedef union MC_XPB_PEER_SYS_BAR2             regMC_XPB_PEER_SYS_BAR2;
typedef union MC_XPB_PEER_SYS_BAR3             regMC_XPB_PEER_SYS_BAR3;
typedef union MC_XPB_PEER_SYS_BAR4             regMC_XPB_PEER_SYS_BAR4;
typedef union MC_XPB_PEER_SYS_BAR5             regMC_XPB_PEER_SYS_BAR5;
typedef union MC_XPB_PEER_SYS_BAR6             regMC_XPB_PEER_SYS_BAR6;
typedef union MC_XPB_PEER_SYS_BAR7             regMC_XPB_PEER_SYS_BAR7;
typedef union MC_XPB_PEER_SYS_BAR8             regMC_XPB_PEER_SYS_BAR8;
typedef union MC_XPB_PEER_SYS_BAR9             regMC_XPB_PEER_SYS_BAR9;
typedef union MC_XPB_PERF_KNOBS                regMC_XPB_PERF_KNOBS;
typedef union MC_XPB_PIPE_STS                  regMC_XPB_PIPE_STS;
typedef union MC_XPB_RTR_DEST_MAP0             regMC_XPB_RTR_DEST_MAP0;
typedef union MC_XPB_RTR_DEST_MAP1             regMC_XPB_RTR_DEST_MAP1;
typedef union MC_XPB_RTR_DEST_MAP2             regMC_XPB_RTR_DEST_MAP2;
typedef union MC_XPB_RTR_DEST_MAP3             regMC_XPB_RTR_DEST_MAP3;
typedef union MC_XPB_RTR_DEST_MAP4             regMC_XPB_RTR_DEST_MAP4;
typedef union MC_XPB_RTR_DEST_MAP5             regMC_XPB_RTR_DEST_MAP5;
typedef union MC_XPB_RTR_DEST_MAP6             regMC_XPB_RTR_DEST_MAP6;
typedef union MC_XPB_RTR_DEST_MAP7             regMC_XPB_RTR_DEST_MAP7;
typedef union MC_XPB_RTR_DEST_MAP8             regMC_XPB_RTR_DEST_MAP8;
typedef union MC_XPB_RTR_DEST_MAP9             regMC_XPB_RTR_DEST_MAP9;
typedef union MC_XPB_RTR_SRC_APRTR0            regMC_XPB_RTR_SRC_APRTR0;
typedef union MC_XPB_RTR_SRC_APRTR1            regMC_XPB_RTR_SRC_APRTR1;
typedef union MC_XPB_RTR_SRC_APRTR2            regMC_XPB_RTR_SRC_APRTR2;
typedef union MC_XPB_RTR_SRC_APRTR3            regMC_XPB_RTR_SRC_APRTR3;
typedef union MC_XPB_RTR_SRC_APRTR4            regMC_XPB_RTR_SRC_APRTR4;
typedef union MC_XPB_RTR_SRC_APRTR5            regMC_XPB_RTR_SRC_APRTR5;
typedef union MC_XPB_RTR_SRC_APRTR6            regMC_XPB_RTR_SRC_APRTR6;
typedef union MC_XPB_RTR_SRC_APRTR7            regMC_XPB_RTR_SRC_APRTR7;
typedef union MC_XPB_RTR_SRC_APRTR8            regMC_XPB_RTR_SRC_APRTR8;
typedef union MC_XPB_RTR_SRC_APRTR9            regMC_XPB_RTR_SRC_APRTR9;
typedef union MC_XPB_STICKY                    regMC_XPB_STICKY;
typedef union MC_XPB_STICKY_W1C                regMC_XPB_STICKY_W1C;
typedef union MC_XPB_SUB_CTRL                  regMC_XPB_SUB_CTRL;
typedef union MC_XPB_UNC_THRESH_HST            regMC_XPB_UNC_THRESH_HST;
typedef union MC_XPB_UNC_THRESH_SID            regMC_XPB_UNC_THRESH_SID;
typedef union MC_XPB_WCB_CFG                   regMC_XPB_WCB_CFG;
typedef union MC_XPB_WCB_STS                   regMC_XPB_WCB_STS;
typedef union MC_XPB_XDMA_PEER_SYS_BAR0        regMC_XPB_XDMA_PEER_SYS_BAR0;
typedef union MC_XPB_XDMA_PEER_SYS_BAR1        regMC_XPB_XDMA_PEER_SYS_BAR1;
typedef union MC_XPB_XDMA_PEER_SYS_BAR2        regMC_XPB_XDMA_PEER_SYS_BAR2;
typedef union MC_XPB_XDMA_PEER_SYS_BAR3        regMC_XPB_XDMA_PEER_SYS_BAR3;
typedef union MC_XPB_XDMA_RTR_DEST_MAP0        regMC_XPB_XDMA_RTR_DEST_MAP0;
typedef union MC_XPB_XDMA_RTR_DEST_MAP1        regMC_XPB_XDMA_RTR_DEST_MAP1;
typedef union MC_XPB_XDMA_RTR_DEST_MAP2        regMC_XPB_XDMA_RTR_DEST_MAP2;
typedef union MC_XPB_XDMA_RTR_DEST_MAP3        regMC_XPB_XDMA_RTR_DEST_MAP3;
typedef union MC_XPB_XDMA_RTR_SRC_APRTR0       regMC_XPB_XDMA_RTR_SRC_APRTR0;
typedef union MC_XPB_XDMA_RTR_SRC_APRTR1       regMC_XPB_XDMA_RTR_SRC_APRTR1;
typedef union MC_XPB_XDMA_RTR_SRC_APRTR2       regMC_XPB_XDMA_RTR_SRC_APRTR2;
typedef union MC_XPB_XDMA_RTR_SRC_APRTR3       regMC_XPB_XDMA_RTR_SRC_APRTR3;
typedef union MEM_TYPE_CNTL__CI__VI            regMEM_TYPE_CNTL__CI__VI;
typedef union MICROSECOND_TIME_BASE_DIV__SI__VI regMICROSECOND_TIME_BASE_DIV__SI__VI;
typedef union MINOR_VERSION__SI__VI            regMINOR_VERSION__SI__VI;
typedef union MIN_GRANT                        regMIN_GRANT;
typedef union MISC_CLK_CTRL__CI__VI            regMISC_CLK_CTRL__CI__VI;
typedef union MM_CFGREGS_CNTL                  regMM_CFGREGS_CNTL;
typedef union MM_DATA                          regMM_DATA;
typedef union MM_INDEX                         regMM_INDEX;
typedef union MM_INDEX_HI__CI__VI              regMM_INDEX_HI__CI__VI;
typedef union MPLL_AD_FUNC_CNTL__SI__CI        regMPLL_AD_FUNC_CNTL__SI__CI;
typedef union MPLL_AD_STATUS__SI__CI           regMPLL_AD_STATUS__SI__CI;
typedef union MPLL_BYPASSCLK_SEL               regMPLL_BYPASSCLK_SEL;
typedef union MPLL_CNTL_MODE__SI__CI           regMPLL_CNTL_MODE__SI__CI;
typedef union MPLL_CONTROL__SI__CI             regMPLL_CONTROL__SI__CI;
typedef union MPLL_DQ_0_0_STATUS__SI__CI       regMPLL_DQ_0_0_STATUS__SI__CI;
typedef union MPLL_DQ_0_1_STATUS__SI__CI       regMPLL_DQ_0_1_STATUS__SI__CI;
typedef union MPLL_DQ_1_0_STATUS__SI__CI       regMPLL_DQ_1_0_STATUS__SI__CI;
typedef union MPLL_DQ_1_1_STATUS__SI__CI       regMPLL_DQ_1_1_STATUS__SI__CI;
typedef union MPLL_DQ_FUNC_CNTL__SI__CI        regMPLL_DQ_FUNC_CNTL__SI__CI;
typedef union MPLL_FUNC_CNTL__SI__CI           regMPLL_FUNC_CNTL__SI__CI;
typedef union MPLL_FUNC_CNTL_1__SI__CI         regMPLL_FUNC_CNTL_1__SI__CI;
typedef union MPLL_FUNC_CNTL_2__CI             regMPLL_FUNC_CNTL_2__CI;
typedef union MPLL_FUNC_CNTL_2__SI             regMPLL_FUNC_CNTL_2__SI;
typedef union MPLL_SEQ_UCODE_1__SI__CI         regMPLL_SEQ_UCODE_1__SI__CI;
typedef union MPLL_SEQ_UCODE_2__SI__CI         regMPLL_SEQ_UCODE_2__SI__CI;
typedef union MPLL_SS1__SI__CI                 regMPLL_SS1__SI__CI;
typedef union MPLL_SS2__SI__CI                 regMPLL_SS2__SI__CI;
typedef union MPLL_TIME__SI__CI                regMPLL_TIME__SI__CI;
typedef union MSI_CAP_LIST                     regMSI_CAP_LIST;
typedef union MSI_MSG_ADDR_HI                  regMSI_MSG_ADDR_HI;
typedef union MSI_MSG_ADDR_LO                  regMSI_MSG_ADDR_LO;
typedef union MSI_MSG_CNTL                     regMSI_MSG_CNTL;
typedef union MSI_MSG_DATA                     regMSI_MSG_DATA;
typedef union MSI_MSG_DATA_64                  regMSI_MSG_DATA_64;
typedef union MVP_AFR_FLIP_FIFO_CNTL__SI__VI   regMVP_AFR_FLIP_FIFO_CNTL__SI__VI;
typedef union MVP_AFR_FLIP_MODE__SI__VI        regMVP_AFR_FLIP_MODE__SI__VI;
typedef union MVP_BLACK_KEYER__SI__VI          regMVP_BLACK_KEYER__SI__VI;
typedef union MVP_CONTROL1__SI__VI             regMVP_CONTROL1__SI__VI;
typedef union MVP_CONTROL2__SI__VI             regMVP_CONTROL2__SI__VI;
typedef union MVP_CONTROL3__SI__VI             regMVP_CONTROL3__SI__VI;
typedef union MVP_CRC_CNTL__SI__VI             regMVP_CRC_CNTL__SI__VI;
typedef union MVP_CRC_RESULT_BLUE_GREEN__SI__VI regMVP_CRC_RESULT_BLUE_GREEN__SI__VI;
typedef union MVP_CRC_RESULT_RED__SI__VI       regMVP_CRC_RESULT_RED__SI__VI;
typedef union MVP_DEBUG_05__SI__VI             regMVP_DEBUG_05__SI__VI;
typedef union MVP_DEBUG_09__SI__VI             regMVP_DEBUG_09__SI__VI;
typedef union MVP_DEBUG_12__SI__VI             regMVP_DEBUG_12__SI__VI;
typedef union MVP_DEBUG_13__SI__VI             regMVP_DEBUG_13__SI__VI;
typedef union MVP_DEBUG_14__SI__VI             regMVP_DEBUG_14__SI__VI;
typedef union MVP_DEBUG_15__SI__VI             regMVP_DEBUG_15__SI__VI;
typedef union MVP_DEBUG_16__SI__VI             regMVP_DEBUG_16__SI__VI;
typedef union MVP_DEBUG_17__SI__VI             regMVP_DEBUG_17__SI__VI;
typedef union MVP_FIFO_CONTROL__SI__VI         regMVP_FIFO_CONTROL__SI__VI;
typedef union MVP_FIFO_STATUS__SI__VI          regMVP_FIFO_STATUS__SI__VI;
typedef union MVP_FLIP_LINE_NUM_INSERT__SI__VI regMVP_FLIP_LINE_NUM_INSERT__SI__VI;
typedef union MVP_INBAND_CNTL_CAP__SI__VI      regMVP_INBAND_CNTL_CAP__SI__VI;
typedef union MVP_RECEIVE_CNT_CNTL1__SI__VI    regMVP_RECEIVE_CNT_CNTL1__SI__VI;
typedef union MVP_RECEIVE_CNT_CNTL2__SI__VI    regMVP_RECEIVE_CNT_CNTL2__SI__VI;
typedef union MVP_SLAVE_STATUS__SI__VI         regMVP_SLAVE_STATUS__SI__VI;
typedef union MVP_TEST_DEBUG_DATA__SI__VI      regMVP_TEST_DEBUG_DATA__SI__VI;
typedef union MVP_TEST_DEBUG_INDEX__SI__VI     regMVP_TEST_DEBUG_INDEX__SI__VI;
typedef union NEW_REFCLKB_TIMER_1__CI          regNEW_REFCLKB_TIMER_1__CI;
typedef union NEW_REFCLKB_TIMER__CI            regNEW_REFCLKB_TIMER__CI;
typedef union OUTPUT_PAYLOAD_CAPABILITY__SI__VI regOUTPUT_PAYLOAD_CAPABILITY__SI__VI;
typedef union OVLSCL_EDGE_PIXEL_CNTL__SI__VI   regOVLSCL_EDGE_PIXEL_CNTL__SI__VI;
typedef union OVL_CONTROL1__SI                 regOVL_CONTROL1__SI;
typedef union OVL_CONTROL1__VI                 regOVL_CONTROL1__VI;
typedef union OVL_CONTROL2__SI__VI             regOVL_CONTROL2__SI__VI;
typedef union OVL_DFQ_CONTROL__SI__VI          regOVL_DFQ_CONTROL__SI__VI;
typedef union OVL_DFQ_STATUS__SI__VI           regOVL_DFQ_STATUS__SI__VI;
typedef union OVL_ENABLE__SI__VI               regOVL_ENABLE__SI__VI;
typedef union OVL_END__SI__VI                  regOVL_END__SI__VI;
typedef union OVL_PITCH__SI__VI                regOVL_PITCH__SI__VI;
typedef union OVL_START__SI__VI                regOVL_START__SI__VI;
typedef union OVL_SURFACE_ADDRESS              regOVL_SURFACE_ADDRESS;
typedef union OVL_SURFACE_ADDRESS_HIGH         regOVL_SURFACE_ADDRESS_HIGH;
typedef union OVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI regOVL_SURFACE_ADDRESS_HIGH_INUSE__SI__VI;
typedef union OVL_SURFACE_ADDRESS_INUSE__SI__VI regOVL_SURFACE_ADDRESS_INUSE__SI__VI;
typedef union OVL_SURFACE_OFFSET_X__SI__VI     regOVL_SURFACE_OFFSET_X__SI__VI;
typedef union OVL_SURFACE_OFFSET_Y__SI__VI     regOVL_SURFACE_OFFSET_Y__SI__VI;
typedef union OVL_SWAP_CNTL__SI__VI            regOVL_SWAP_CNTL__SI__VI;
typedef union OVL_UPDATE__SI__VI               regOVL_UPDATE__SI__VI;
typedef union PAGE_MIRROR_CNTL                 regPAGE_MIRROR_CNTL;
typedef union PA_CL_CLIP_CNTL                  regPA_CL_CLIP_CNTL;
typedef union PA_CL_CNTL_STATUS                regPA_CL_CNTL_STATUS;
typedef union PA_CL_ENHANCE                    regPA_CL_ENHANCE;
typedef union PA_CL_GB_HORZ_CLIP_ADJ           regPA_CL_GB_HORZ_CLIP_ADJ;
typedef union PA_CL_GB_HORZ_DISC_ADJ           regPA_CL_GB_HORZ_DISC_ADJ;
typedef union PA_CL_GB_VERT_CLIP_ADJ           regPA_CL_GB_VERT_CLIP_ADJ;
typedef union PA_CL_GB_VERT_DISC_ADJ           regPA_CL_GB_VERT_DISC_ADJ;
typedef union PA_CL_NANINF_CNTL                regPA_CL_NANINF_CNTL;
typedef union PA_CL_POINT_CULL_RAD             regPA_CL_POINT_CULL_RAD;
typedef union PA_CL_POINT_SIZE                 regPA_CL_POINT_SIZE;
typedef union PA_CL_POINT_X_RAD                regPA_CL_POINT_X_RAD;
typedef union PA_CL_POINT_Y_RAD                regPA_CL_POINT_Y_RAD;
typedef union PA_CL_RESET_DEBUG__CI__VI        regPA_CL_RESET_DEBUG__CI__VI;
typedef union PA_CL_UCP_0_W                    regPA_CL_UCP_0_W;
typedef union PA_CL_UCP_0_X                    regPA_CL_UCP_0_X;
typedef union PA_CL_UCP_0_Y                    regPA_CL_UCP_0_Y;
typedef union PA_CL_UCP_0_Z                    regPA_CL_UCP_0_Z;
typedef union PA_CL_UCP_1_W                    regPA_CL_UCP_1_W;
typedef union PA_CL_UCP_1_X                    regPA_CL_UCP_1_X;
typedef union PA_CL_UCP_1_Y                    regPA_CL_UCP_1_Y;
typedef union PA_CL_UCP_1_Z                    regPA_CL_UCP_1_Z;
typedef union PA_CL_UCP_2_W                    regPA_CL_UCP_2_W;
typedef union PA_CL_UCP_2_X                    regPA_CL_UCP_2_X;
typedef union PA_CL_UCP_2_Y                    regPA_CL_UCP_2_Y;
typedef union PA_CL_UCP_2_Z                    regPA_CL_UCP_2_Z;
typedef union PA_CL_UCP_3_W                    regPA_CL_UCP_3_W;
typedef union PA_CL_UCP_3_X                    regPA_CL_UCP_3_X;
typedef union PA_CL_UCP_3_Y                    regPA_CL_UCP_3_Y;
typedef union PA_CL_UCP_3_Z                    regPA_CL_UCP_3_Z;
typedef union PA_CL_UCP_4_W                    regPA_CL_UCP_4_W;
typedef union PA_CL_UCP_4_X                    regPA_CL_UCP_4_X;
typedef union PA_CL_UCP_4_Y                    regPA_CL_UCP_4_Y;
typedef union PA_CL_UCP_4_Z                    regPA_CL_UCP_4_Z;
typedef union PA_CL_UCP_5_W                    regPA_CL_UCP_5_W;
typedef union PA_CL_UCP_5_X                    regPA_CL_UCP_5_X;
typedef union PA_CL_UCP_5_Y                    regPA_CL_UCP_5_Y;
typedef union PA_CL_UCP_5_Z                    regPA_CL_UCP_5_Z;
typedef union PA_CL_VPORT_XOFFSET              regPA_CL_VPORT_XOFFSET;
typedef union PA_CL_VPORT_XOFFSET_1            regPA_CL_VPORT_XOFFSET_1;
typedef union PA_CL_VPORT_XOFFSET_10           regPA_CL_VPORT_XOFFSET_10;
typedef union PA_CL_VPORT_XOFFSET_11           regPA_CL_VPORT_XOFFSET_11;
typedef union PA_CL_VPORT_XOFFSET_12           regPA_CL_VPORT_XOFFSET_12;
typedef union PA_CL_VPORT_XOFFSET_13           regPA_CL_VPORT_XOFFSET_13;
typedef union PA_CL_VPORT_XOFFSET_14           regPA_CL_VPORT_XOFFSET_14;
typedef union PA_CL_VPORT_XOFFSET_15           regPA_CL_VPORT_XOFFSET_15;
typedef union PA_CL_VPORT_XOFFSET_2            regPA_CL_VPORT_XOFFSET_2;
typedef union PA_CL_VPORT_XOFFSET_3            regPA_CL_VPORT_XOFFSET_3;
typedef union PA_CL_VPORT_XOFFSET_4            regPA_CL_VPORT_XOFFSET_4;
typedef union PA_CL_VPORT_XOFFSET_5            regPA_CL_VPORT_XOFFSET_5;
typedef union PA_CL_VPORT_XOFFSET_6            regPA_CL_VPORT_XOFFSET_6;
typedef union PA_CL_VPORT_XOFFSET_7            regPA_CL_VPORT_XOFFSET_7;
typedef union PA_CL_VPORT_XOFFSET_8            regPA_CL_VPORT_XOFFSET_8;
typedef union PA_CL_VPORT_XOFFSET_9            regPA_CL_VPORT_XOFFSET_9;
typedef union PA_CL_VPORT_XSCALE               regPA_CL_VPORT_XSCALE;
typedef union PA_CL_VPORT_XSCALE_1             regPA_CL_VPORT_XSCALE_1;
typedef union PA_CL_VPORT_XSCALE_10            regPA_CL_VPORT_XSCALE_10;
typedef union PA_CL_VPORT_XSCALE_11            regPA_CL_VPORT_XSCALE_11;
typedef union PA_CL_VPORT_XSCALE_12            regPA_CL_VPORT_XSCALE_12;
typedef union PA_CL_VPORT_XSCALE_13            regPA_CL_VPORT_XSCALE_13;
typedef union PA_CL_VPORT_XSCALE_14            regPA_CL_VPORT_XSCALE_14;
typedef union PA_CL_VPORT_XSCALE_15            regPA_CL_VPORT_XSCALE_15;
typedef union PA_CL_VPORT_XSCALE_2             regPA_CL_VPORT_XSCALE_2;
typedef union PA_CL_VPORT_XSCALE_3             regPA_CL_VPORT_XSCALE_3;
typedef union PA_CL_VPORT_XSCALE_4             regPA_CL_VPORT_XSCALE_4;
typedef union PA_CL_VPORT_XSCALE_5             regPA_CL_VPORT_XSCALE_5;
typedef union PA_CL_VPORT_XSCALE_6             regPA_CL_VPORT_XSCALE_6;
typedef union PA_CL_VPORT_XSCALE_7             regPA_CL_VPORT_XSCALE_7;
typedef union PA_CL_VPORT_XSCALE_8             regPA_CL_VPORT_XSCALE_8;
typedef union PA_CL_VPORT_XSCALE_9             regPA_CL_VPORT_XSCALE_9;
typedef union PA_CL_VPORT_YOFFSET              regPA_CL_VPORT_YOFFSET;
typedef union PA_CL_VPORT_YOFFSET_1            regPA_CL_VPORT_YOFFSET_1;
typedef union PA_CL_VPORT_YOFFSET_10           regPA_CL_VPORT_YOFFSET_10;
typedef union PA_CL_VPORT_YOFFSET_11           regPA_CL_VPORT_YOFFSET_11;
typedef union PA_CL_VPORT_YOFFSET_12           regPA_CL_VPORT_YOFFSET_12;
typedef union PA_CL_VPORT_YOFFSET_13           regPA_CL_VPORT_YOFFSET_13;
typedef union PA_CL_VPORT_YOFFSET_14           regPA_CL_VPORT_YOFFSET_14;
typedef union PA_CL_VPORT_YOFFSET_15           regPA_CL_VPORT_YOFFSET_15;
typedef union PA_CL_VPORT_YOFFSET_2            regPA_CL_VPORT_YOFFSET_2;
typedef union PA_CL_VPORT_YOFFSET_3            regPA_CL_VPORT_YOFFSET_3;
typedef union PA_CL_VPORT_YOFFSET_4            regPA_CL_VPORT_YOFFSET_4;
typedef union PA_CL_VPORT_YOFFSET_5            regPA_CL_VPORT_YOFFSET_5;
typedef union PA_CL_VPORT_YOFFSET_6            regPA_CL_VPORT_YOFFSET_6;
typedef union PA_CL_VPORT_YOFFSET_7            regPA_CL_VPORT_YOFFSET_7;
typedef union PA_CL_VPORT_YOFFSET_8            regPA_CL_VPORT_YOFFSET_8;
typedef union PA_CL_VPORT_YOFFSET_9            regPA_CL_VPORT_YOFFSET_9;
typedef union PA_CL_VPORT_YSCALE               regPA_CL_VPORT_YSCALE;
typedef union PA_CL_VPORT_YSCALE_1             regPA_CL_VPORT_YSCALE_1;
typedef union PA_CL_VPORT_YSCALE_10            regPA_CL_VPORT_YSCALE_10;
typedef union PA_CL_VPORT_YSCALE_11            regPA_CL_VPORT_YSCALE_11;
typedef union PA_CL_VPORT_YSCALE_12            regPA_CL_VPORT_YSCALE_12;
typedef union PA_CL_VPORT_YSCALE_13            regPA_CL_VPORT_YSCALE_13;
typedef union PA_CL_VPORT_YSCALE_14            regPA_CL_VPORT_YSCALE_14;
typedef union PA_CL_VPORT_YSCALE_15            regPA_CL_VPORT_YSCALE_15;
typedef union PA_CL_VPORT_YSCALE_2             regPA_CL_VPORT_YSCALE_2;
typedef union PA_CL_VPORT_YSCALE_3             regPA_CL_VPORT_YSCALE_3;
typedef union PA_CL_VPORT_YSCALE_4             regPA_CL_VPORT_YSCALE_4;
typedef union PA_CL_VPORT_YSCALE_5             regPA_CL_VPORT_YSCALE_5;
typedef union PA_CL_VPORT_YSCALE_6             regPA_CL_VPORT_YSCALE_6;
typedef union PA_CL_VPORT_YSCALE_7             regPA_CL_VPORT_YSCALE_7;
typedef union PA_CL_VPORT_YSCALE_8             regPA_CL_VPORT_YSCALE_8;
typedef union PA_CL_VPORT_YSCALE_9             regPA_CL_VPORT_YSCALE_9;
typedef union PA_CL_VPORT_ZOFFSET              regPA_CL_VPORT_ZOFFSET;
typedef union PA_CL_VPORT_ZOFFSET_1            regPA_CL_VPORT_ZOFFSET_1;
typedef union PA_CL_VPORT_ZOFFSET_10           regPA_CL_VPORT_ZOFFSET_10;
typedef union PA_CL_VPORT_ZOFFSET_11           regPA_CL_VPORT_ZOFFSET_11;
typedef union PA_CL_VPORT_ZOFFSET_12           regPA_CL_VPORT_ZOFFSET_12;
typedef union PA_CL_VPORT_ZOFFSET_13           regPA_CL_VPORT_ZOFFSET_13;
typedef union PA_CL_VPORT_ZOFFSET_14           regPA_CL_VPORT_ZOFFSET_14;
typedef union PA_CL_VPORT_ZOFFSET_15           regPA_CL_VPORT_ZOFFSET_15;
typedef union PA_CL_VPORT_ZOFFSET_2            regPA_CL_VPORT_ZOFFSET_2;
typedef union PA_CL_VPORT_ZOFFSET_3            regPA_CL_VPORT_ZOFFSET_3;
typedef union PA_CL_VPORT_ZOFFSET_4            regPA_CL_VPORT_ZOFFSET_4;
typedef union PA_CL_VPORT_ZOFFSET_5            regPA_CL_VPORT_ZOFFSET_5;
typedef union PA_CL_VPORT_ZOFFSET_6            regPA_CL_VPORT_ZOFFSET_6;
typedef union PA_CL_VPORT_ZOFFSET_7            regPA_CL_VPORT_ZOFFSET_7;
typedef union PA_CL_VPORT_ZOFFSET_8            regPA_CL_VPORT_ZOFFSET_8;
typedef union PA_CL_VPORT_ZOFFSET_9            regPA_CL_VPORT_ZOFFSET_9;
typedef union PA_CL_VPORT_ZSCALE               regPA_CL_VPORT_ZSCALE;
typedef union PA_CL_VPORT_ZSCALE_1             regPA_CL_VPORT_ZSCALE_1;
typedef union PA_CL_VPORT_ZSCALE_10            regPA_CL_VPORT_ZSCALE_10;
typedef union PA_CL_VPORT_ZSCALE_11            regPA_CL_VPORT_ZSCALE_11;
typedef union PA_CL_VPORT_ZSCALE_12            regPA_CL_VPORT_ZSCALE_12;
typedef union PA_CL_VPORT_ZSCALE_13            regPA_CL_VPORT_ZSCALE_13;
typedef union PA_CL_VPORT_ZSCALE_14            regPA_CL_VPORT_ZSCALE_14;
typedef union PA_CL_VPORT_ZSCALE_15            regPA_CL_VPORT_ZSCALE_15;
typedef union PA_CL_VPORT_ZSCALE_2             regPA_CL_VPORT_ZSCALE_2;
typedef union PA_CL_VPORT_ZSCALE_3             regPA_CL_VPORT_ZSCALE_3;
typedef union PA_CL_VPORT_ZSCALE_4             regPA_CL_VPORT_ZSCALE_4;
typedef union PA_CL_VPORT_ZSCALE_5             regPA_CL_VPORT_ZSCALE_5;
typedef union PA_CL_VPORT_ZSCALE_6             regPA_CL_VPORT_ZSCALE_6;
typedef union PA_CL_VPORT_ZSCALE_7             regPA_CL_VPORT_ZSCALE_7;
typedef union PA_CL_VPORT_ZSCALE_8             regPA_CL_VPORT_ZSCALE_8;
typedef union PA_CL_VPORT_ZSCALE_9             regPA_CL_VPORT_ZSCALE_9;
typedef union PA_CL_VS_OUT_CNTL                regPA_CL_VS_OUT_CNTL;
typedef union PA_CL_VTE_CNTL                   regPA_CL_VTE_CNTL;
typedef union PA_SC_AA_CONFIG                  regPA_SC_AA_CONFIG;
typedef union PA_SC_AA_MASK_X0Y0_X1Y0          regPA_SC_AA_MASK_X0Y0_X1Y0;
typedef union PA_SC_AA_MASK_X0Y1_X1Y1          regPA_SC_AA_MASK_X0Y1_X1Y1;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2;
typedef union PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3;
typedef union PA_SC_CENTROID_PRIORITY_0        regPA_SC_CENTROID_PRIORITY_0;
typedef union PA_SC_CENTROID_PRIORITY_1        regPA_SC_CENTROID_PRIORITY_1;
typedef union PA_SC_CLIPRECT_0_BR              regPA_SC_CLIPRECT_0_BR;
typedef union PA_SC_CLIPRECT_0_TL              regPA_SC_CLIPRECT_0_TL;
typedef union PA_SC_CLIPRECT_1_BR              regPA_SC_CLIPRECT_1_BR;
typedef union PA_SC_CLIPRECT_1_TL              regPA_SC_CLIPRECT_1_TL;
typedef union PA_SC_CLIPRECT_2_BR              regPA_SC_CLIPRECT_2_BR;
typedef union PA_SC_CLIPRECT_2_TL              regPA_SC_CLIPRECT_2_TL;
typedef union PA_SC_CLIPRECT_3_BR              regPA_SC_CLIPRECT_3_BR;
typedef union PA_SC_CLIPRECT_3_TL              regPA_SC_CLIPRECT_3_TL;
typedef union PA_SC_CLIPRECT_RULE              regPA_SC_CLIPRECT_RULE;
typedef union PA_SC_DEBUG_CNTL                 regPA_SC_DEBUG_CNTL;
typedef union PA_SC_DEBUG_DATA                 regPA_SC_DEBUG_DATA;
typedef union PA_SC_DEBUG_REG0                 regPA_SC_DEBUG_REG0;
typedef union PA_SC_DEBUG_REG1                 regPA_SC_DEBUG_REG1;
typedef union PA_SC_EDGERULE                   regPA_SC_EDGERULE;
typedef union PA_SC_ENHANCE__CI__VI            regPA_SC_ENHANCE__CI__VI;
typedef union PA_SC_ENHANCE__SI                regPA_SC_ENHANCE__SI;
typedef union PA_SC_FIFO_DEPTH_CNTL            regPA_SC_FIFO_DEPTH_CNTL;
typedef union PA_SC_FIFO_SIZE                  regPA_SC_FIFO_SIZE;
typedef union PA_SC_FORCE_EOV_MAX_CNTS         regPA_SC_FORCE_EOV_MAX_CNTS;
typedef union PA_SC_GENERIC_SCISSOR_BR         regPA_SC_GENERIC_SCISSOR_BR;
typedef union PA_SC_GENERIC_SCISSOR_TL         regPA_SC_GENERIC_SCISSOR_TL;
typedef union PA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI regPA_SC_HP3D_TRAP_SCREEN_COUNT__CI__VI;
typedef union PA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI regPA_SC_HP3D_TRAP_SCREEN_HV_EN__CI__VI;
typedef union PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK__CI__VI;
typedef union PA_SC_HP3D_TRAP_SCREEN_H__CI__VI regPA_SC_HP3D_TRAP_SCREEN_H__CI__VI;
typedef union PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__CI__VI;
typedef union PA_SC_HP3D_TRAP_SCREEN_V__CI__VI regPA_SC_HP3D_TRAP_SCREEN_V__CI__VI;
typedef union PA_SC_IF_FIFO_SIZE               regPA_SC_IF_FIFO_SIZE;
typedef union PA_SC_LINE_CNTL                  regPA_SC_LINE_CNTL;
typedef union PA_SC_LINE_STIPPLE               regPA_SC_LINE_STIPPLE;
typedef union PA_SC_LINE_STIPPLE_STATE         regPA_SC_LINE_STIPPLE_STATE;
typedef union PA_SC_MODE_CNTL_0                regPA_SC_MODE_CNTL_0;
typedef union PA_SC_MODE_CNTL_1                regPA_SC_MODE_CNTL_1;
typedef union PA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI regPA_SC_P3D_TRAP_SCREEN_COUNT__CI__VI;
typedef union PA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI regPA_SC_P3D_TRAP_SCREEN_HV_EN__CI__VI;
typedef union PA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI regPA_SC_P3D_TRAP_SCREEN_HV_LOCK__CI__VI;
typedef union PA_SC_P3D_TRAP_SCREEN_H__CI__VI  regPA_SC_P3D_TRAP_SCREEN_H__CI__VI;
typedef union PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE__CI__VI;
typedef union PA_SC_P3D_TRAP_SCREEN_V__CI__VI  regPA_SC_P3D_TRAP_SCREEN_V__CI__VI;
typedef union PA_SC_PERFCOUNTER0_HI            regPA_SC_PERFCOUNTER0_HI;
typedef union PA_SC_PERFCOUNTER0_LO            regPA_SC_PERFCOUNTER0_LO;
typedef union PA_SC_PERFCOUNTER0_SELECT        regPA_SC_PERFCOUNTER0_SELECT;
typedef union PA_SC_PERFCOUNTER0_SELECT1__CI__VI regPA_SC_PERFCOUNTER0_SELECT1__CI__VI;
typedef union PA_SC_PERFCOUNTER1_HI            regPA_SC_PERFCOUNTER1_HI;
typedef union PA_SC_PERFCOUNTER1_LO            regPA_SC_PERFCOUNTER1_LO;
typedef union PA_SC_PERFCOUNTER1_SELECT        regPA_SC_PERFCOUNTER1_SELECT;
typedef union PA_SC_PERFCOUNTER2_HI            regPA_SC_PERFCOUNTER2_HI;
typedef union PA_SC_PERFCOUNTER2_LO            regPA_SC_PERFCOUNTER2_LO;
typedef union PA_SC_PERFCOUNTER2_SELECT        regPA_SC_PERFCOUNTER2_SELECT;
typedef union PA_SC_PERFCOUNTER3_HI            regPA_SC_PERFCOUNTER3_HI;
typedef union PA_SC_PERFCOUNTER3_LO            regPA_SC_PERFCOUNTER3_LO;
typedef union PA_SC_PERFCOUNTER3_SELECT        regPA_SC_PERFCOUNTER3_SELECT;
typedef union PA_SC_PERFCOUNTER4_HI            regPA_SC_PERFCOUNTER4_HI;
typedef union PA_SC_PERFCOUNTER4_LO            regPA_SC_PERFCOUNTER4_LO;
typedef union PA_SC_PERFCOUNTER4_SELECT        regPA_SC_PERFCOUNTER4_SELECT;
typedef union PA_SC_PERFCOUNTER5_HI            regPA_SC_PERFCOUNTER5_HI;
typedef union PA_SC_PERFCOUNTER5_LO            regPA_SC_PERFCOUNTER5_LO;
typedef union PA_SC_PERFCOUNTER5_SELECT        regPA_SC_PERFCOUNTER5_SELECT;
typedef union PA_SC_PERFCOUNTER6_HI            regPA_SC_PERFCOUNTER6_HI;
typedef union PA_SC_PERFCOUNTER6_LO            regPA_SC_PERFCOUNTER6_LO;
typedef union PA_SC_PERFCOUNTER6_SELECT        regPA_SC_PERFCOUNTER6_SELECT;
typedef union PA_SC_PERFCOUNTER7_HI            regPA_SC_PERFCOUNTER7_HI;
typedef union PA_SC_PERFCOUNTER7_LO            regPA_SC_PERFCOUNTER7_LO;
typedef union PA_SC_PERFCOUNTER7_SELECT        regPA_SC_PERFCOUNTER7_SELECT;
typedef union PA_SC_RASTER_CONFIG              regPA_SC_RASTER_CONFIG;
typedef union PA_SC_RASTER_CONFIG_1__CI__VI    regPA_SC_RASTER_CONFIG_1__CI__VI;
typedef union PA_SC_SCREEN_SCISSOR_BR          regPA_SC_SCREEN_SCISSOR_BR;
typedef union PA_SC_SCREEN_SCISSOR_TL          regPA_SC_SCREEN_SCISSOR_TL;
typedef union PA_SC_TRAP_SCREEN_COUNT__CI__VI  regPA_SC_TRAP_SCREEN_COUNT__CI__VI;
typedef union PA_SC_TRAP_SCREEN_HV_EN__CI__VI  regPA_SC_TRAP_SCREEN_HV_EN__CI__VI;
typedef union PA_SC_TRAP_SCREEN_HV_LOCK__CI__VI regPA_SC_TRAP_SCREEN_HV_LOCK__CI__VI;
typedef union PA_SC_TRAP_SCREEN_H__CI__VI      regPA_SC_TRAP_SCREEN_H__CI__VI;
typedef union PA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI regPA_SC_TRAP_SCREEN_OCCURRENCE__CI__VI;
typedef union PA_SC_TRAP_SCREEN_V__CI__VI      regPA_SC_TRAP_SCREEN_V__CI__VI;
typedef union PA_SC_VPORT_SCISSOR_0_BR         regPA_SC_VPORT_SCISSOR_0_BR;
typedef union PA_SC_VPORT_SCISSOR_0_TL         regPA_SC_VPORT_SCISSOR_0_TL;
typedef union PA_SC_VPORT_SCISSOR_10_BR        regPA_SC_VPORT_SCISSOR_10_BR;
typedef union PA_SC_VPORT_SCISSOR_10_TL        regPA_SC_VPORT_SCISSOR_10_TL;
typedef union PA_SC_VPORT_SCISSOR_11_BR        regPA_SC_VPORT_SCISSOR_11_BR;
typedef union PA_SC_VPORT_SCISSOR_11_TL        regPA_SC_VPORT_SCISSOR_11_TL;
typedef union PA_SC_VPORT_SCISSOR_12_BR        regPA_SC_VPORT_SCISSOR_12_BR;
typedef union PA_SC_VPORT_SCISSOR_12_TL        regPA_SC_VPORT_SCISSOR_12_TL;
typedef union PA_SC_VPORT_SCISSOR_13_BR        regPA_SC_VPORT_SCISSOR_13_BR;
typedef union PA_SC_VPORT_SCISSOR_13_TL        regPA_SC_VPORT_SCISSOR_13_TL;
typedef union PA_SC_VPORT_SCISSOR_14_BR        regPA_SC_VPORT_SCISSOR_14_BR;
typedef union PA_SC_VPORT_SCISSOR_14_TL        regPA_SC_VPORT_SCISSOR_14_TL;
typedef union PA_SC_VPORT_SCISSOR_15_BR        regPA_SC_VPORT_SCISSOR_15_BR;
typedef union PA_SC_VPORT_SCISSOR_15_TL        regPA_SC_VPORT_SCISSOR_15_TL;
typedef union PA_SC_VPORT_SCISSOR_1_BR         regPA_SC_VPORT_SCISSOR_1_BR;
typedef union PA_SC_VPORT_SCISSOR_1_TL         regPA_SC_VPORT_SCISSOR_1_TL;
typedef union PA_SC_VPORT_SCISSOR_2_BR         regPA_SC_VPORT_SCISSOR_2_BR;
typedef union PA_SC_VPORT_SCISSOR_2_TL         regPA_SC_VPORT_SCISSOR_2_TL;
typedef union PA_SC_VPORT_SCISSOR_3_BR         regPA_SC_VPORT_SCISSOR_3_BR;
typedef union PA_SC_VPORT_SCISSOR_3_TL         regPA_SC_VPORT_SCISSOR_3_TL;
typedef union PA_SC_VPORT_SCISSOR_4_BR         regPA_SC_VPORT_SCISSOR_4_BR;
typedef union PA_SC_VPORT_SCISSOR_4_TL         regPA_SC_VPORT_SCISSOR_4_TL;
typedef union PA_SC_VPORT_SCISSOR_5_BR         regPA_SC_VPORT_SCISSOR_5_BR;
typedef union PA_SC_VPORT_SCISSOR_5_TL         regPA_SC_VPORT_SCISSOR_5_TL;
typedef union PA_SC_VPORT_SCISSOR_6_BR         regPA_SC_VPORT_SCISSOR_6_BR;
typedef union PA_SC_VPORT_SCISSOR_6_TL         regPA_SC_VPORT_SCISSOR_6_TL;
typedef union PA_SC_VPORT_SCISSOR_7_BR         regPA_SC_VPORT_SCISSOR_7_BR;
typedef union PA_SC_VPORT_SCISSOR_7_TL         regPA_SC_VPORT_SCISSOR_7_TL;
typedef union PA_SC_VPORT_SCISSOR_8_BR         regPA_SC_VPORT_SCISSOR_8_BR;
typedef union PA_SC_VPORT_SCISSOR_8_TL         regPA_SC_VPORT_SCISSOR_8_TL;
typedef union PA_SC_VPORT_SCISSOR_9_BR         regPA_SC_VPORT_SCISSOR_9_BR;
typedef union PA_SC_VPORT_SCISSOR_9_TL         regPA_SC_VPORT_SCISSOR_9_TL;
typedef union PA_SC_VPORT_ZMAX_0               regPA_SC_VPORT_ZMAX_0;
typedef union PA_SC_VPORT_ZMAX_1               regPA_SC_VPORT_ZMAX_1;
typedef union PA_SC_VPORT_ZMAX_10              regPA_SC_VPORT_ZMAX_10;
typedef union PA_SC_VPORT_ZMAX_11              regPA_SC_VPORT_ZMAX_11;
typedef union PA_SC_VPORT_ZMAX_12              regPA_SC_VPORT_ZMAX_12;
typedef union PA_SC_VPORT_ZMAX_13              regPA_SC_VPORT_ZMAX_13;
typedef union PA_SC_VPORT_ZMAX_14              regPA_SC_VPORT_ZMAX_14;
typedef union PA_SC_VPORT_ZMAX_15              regPA_SC_VPORT_ZMAX_15;
typedef union PA_SC_VPORT_ZMAX_2               regPA_SC_VPORT_ZMAX_2;
typedef union PA_SC_VPORT_ZMAX_3               regPA_SC_VPORT_ZMAX_3;
typedef union PA_SC_VPORT_ZMAX_4               regPA_SC_VPORT_ZMAX_4;
typedef union PA_SC_VPORT_ZMAX_5               regPA_SC_VPORT_ZMAX_5;
typedef union PA_SC_VPORT_ZMAX_6               regPA_SC_VPORT_ZMAX_6;
typedef union PA_SC_VPORT_ZMAX_7               regPA_SC_VPORT_ZMAX_7;
typedef union PA_SC_VPORT_ZMAX_8               regPA_SC_VPORT_ZMAX_8;
typedef union PA_SC_VPORT_ZMAX_9               regPA_SC_VPORT_ZMAX_9;
typedef union PA_SC_VPORT_ZMIN_0               regPA_SC_VPORT_ZMIN_0;
typedef union PA_SC_VPORT_ZMIN_1               regPA_SC_VPORT_ZMIN_1;
typedef union PA_SC_VPORT_ZMIN_10              regPA_SC_VPORT_ZMIN_10;
typedef union PA_SC_VPORT_ZMIN_11              regPA_SC_VPORT_ZMIN_11;
typedef union PA_SC_VPORT_ZMIN_12              regPA_SC_VPORT_ZMIN_12;
typedef union PA_SC_VPORT_ZMIN_13              regPA_SC_VPORT_ZMIN_13;
typedef union PA_SC_VPORT_ZMIN_14              regPA_SC_VPORT_ZMIN_14;
typedef union PA_SC_VPORT_ZMIN_15              regPA_SC_VPORT_ZMIN_15;
typedef union PA_SC_VPORT_ZMIN_2               regPA_SC_VPORT_ZMIN_2;
typedef union PA_SC_VPORT_ZMIN_3               regPA_SC_VPORT_ZMIN_3;
typedef union PA_SC_VPORT_ZMIN_4               regPA_SC_VPORT_ZMIN_4;
typedef union PA_SC_VPORT_ZMIN_5               regPA_SC_VPORT_ZMIN_5;
typedef union PA_SC_VPORT_ZMIN_6               regPA_SC_VPORT_ZMIN_6;
typedef union PA_SC_VPORT_ZMIN_7               regPA_SC_VPORT_ZMIN_7;
typedef union PA_SC_VPORT_ZMIN_8               regPA_SC_VPORT_ZMIN_8;
typedef union PA_SC_VPORT_ZMIN_9               regPA_SC_VPORT_ZMIN_9;
typedef union PA_SC_WINDOW_OFFSET              regPA_SC_WINDOW_OFFSET;
typedef union PA_SC_WINDOW_SCISSOR_BR          regPA_SC_WINDOW_SCISSOR_BR;
typedef union PA_SC_WINDOW_SCISSOR_TL          regPA_SC_WINDOW_SCISSOR_TL;
typedef union PA_SU_CNTL_STATUS                regPA_SU_CNTL_STATUS;
typedef union PA_SU_DEBUG_CNTL                 regPA_SU_DEBUG_CNTL;
typedef union PA_SU_DEBUG_DATA                 regPA_SU_DEBUG_DATA;
typedef union PA_SU_HARDWARE_SCREEN_OFFSET     regPA_SU_HARDWARE_SCREEN_OFFSET;
typedef union PA_SU_LINE_CNTL                  regPA_SU_LINE_CNTL;
typedef union PA_SU_LINE_STIPPLE_CNTL          regPA_SU_LINE_STIPPLE_CNTL;
typedef union PA_SU_LINE_STIPPLE_SCALE         regPA_SU_LINE_STIPPLE_SCALE;
typedef union PA_SU_LINE_STIPPLE_VALUE         regPA_SU_LINE_STIPPLE_VALUE;
typedef union PA_SU_PERFCOUNTER0_HI            regPA_SU_PERFCOUNTER0_HI;
typedef union PA_SU_PERFCOUNTER0_LO            regPA_SU_PERFCOUNTER0_LO;
typedef union PA_SU_PERFCOUNTER0_SELECT        regPA_SU_PERFCOUNTER0_SELECT;
typedef union PA_SU_PERFCOUNTER0_SELECT1__CI__VI regPA_SU_PERFCOUNTER0_SELECT1__CI__VI;
typedef union PA_SU_PERFCOUNTER1_HI            regPA_SU_PERFCOUNTER1_HI;
typedef union PA_SU_PERFCOUNTER1_LO            regPA_SU_PERFCOUNTER1_LO;
typedef union PA_SU_PERFCOUNTER1_SELECT        regPA_SU_PERFCOUNTER1_SELECT;
typedef union PA_SU_PERFCOUNTER1_SELECT1__CI__VI regPA_SU_PERFCOUNTER1_SELECT1__CI__VI;
typedef union PA_SU_PERFCOUNTER2_HI            regPA_SU_PERFCOUNTER2_HI;
typedef union PA_SU_PERFCOUNTER2_LO            regPA_SU_PERFCOUNTER2_LO;
typedef union PA_SU_PERFCOUNTER2_SELECT        regPA_SU_PERFCOUNTER2_SELECT;
typedef union PA_SU_PERFCOUNTER3_HI            regPA_SU_PERFCOUNTER3_HI;
typedef union PA_SU_PERFCOUNTER3_LO            regPA_SU_PERFCOUNTER3_LO;
typedef union PA_SU_PERFCOUNTER3_SELECT        regPA_SU_PERFCOUNTER3_SELECT;
typedef union PA_SU_POINT_MINMAX               regPA_SU_POINT_MINMAX;
typedef union PA_SU_POINT_SIZE                 regPA_SU_POINT_SIZE;
typedef union PA_SU_POLY_OFFSET_BACK_OFFSET    regPA_SU_POLY_OFFSET_BACK_OFFSET;
typedef union PA_SU_POLY_OFFSET_BACK_SCALE     regPA_SU_POLY_OFFSET_BACK_SCALE;
typedef union PA_SU_POLY_OFFSET_CLAMP          regPA_SU_POLY_OFFSET_CLAMP;
typedef union PA_SU_POLY_OFFSET_DB_FMT_CNTL    regPA_SU_POLY_OFFSET_DB_FMT_CNTL;
typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET   regPA_SU_POLY_OFFSET_FRONT_OFFSET;
typedef union PA_SU_POLY_OFFSET_FRONT_SCALE    regPA_SU_POLY_OFFSET_FRONT_SCALE;
typedef union PA_SU_PRIM_FILTER_CNTL           regPA_SU_PRIM_FILTER_CNTL;
typedef union PA_SU_SC_MODE_CNTL               regPA_SU_SC_MODE_CNTL;
typedef union PA_SU_VTX_CNTL                   regPA_SU_VTX_CNTL;
typedef union PB0_DFT_DEBUG_CTRL_REG0__CI__VI  regPB0_DFT_DEBUG_CTRL_REG0__CI__VI;
typedef union PB0_DFT_JIT_INJ_REG0__CI__VI     regPB0_DFT_JIT_INJ_REG0__CI__VI;
typedef union PB0_DFT_JIT_INJ_REG1__CI__VI     regPB0_DFT_JIT_INJ_REG1__CI__VI;
typedef union PB0_DFT_JIT_INJ_REG2__CI__VI     regPB0_DFT_JIT_INJ_REG2__CI__VI;
typedef union PB0_DFT_JIT_INJ_STAT_REG0__CI__VI regPB0_DFT_JIT_INJ_STAT_REG0__CI__VI;
typedef union PB0_GLB_CTRL_REG0__CI__VI        regPB0_GLB_CTRL_REG0__CI__VI;
typedef union PB0_GLB_CTRL_REG1__CI__VI        regPB0_GLB_CTRL_REG1__CI__VI;
typedef union PB0_GLB_CTRL_REG2__CI__VI        regPB0_GLB_CTRL_REG2__CI__VI;
typedef union PB0_GLB_CTRL_REG3__CI__VI        regPB0_GLB_CTRL_REG3__CI__VI;
typedef union PB0_GLB_CTRL_REG4__CI__VI        regPB0_GLB_CTRL_REG4__CI__VI;
typedef union PB0_GLB_CTRL_REG5__CI__VI        regPB0_GLB_CTRL_REG5__CI__VI;
typedef union PB0_GLB_OVRD_REG0__CI__VI        regPB0_GLB_OVRD_REG0__CI__VI;
typedef union PB0_GLB_OVRD_REG1__CI__VI        regPB0_GLB_OVRD_REG1__CI__VI;
typedef union PB0_GLB_OVRD_REG2__CI__VI        regPB0_GLB_OVRD_REG2__CI__VI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG0__CI   regPB0_GLB_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG0__VI   regPB0_GLB_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG1__CI   regPB0_GLB_SCI_STAT_OVRD_REG1__CI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG1__VI   regPB0_GLB_SCI_STAT_OVRD_REG1__VI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG2__CI   regPB0_GLB_SCI_STAT_OVRD_REG2__CI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG2__VI   regPB0_GLB_SCI_STAT_OVRD_REG2__VI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG3__CI   regPB0_GLB_SCI_STAT_OVRD_REG3__CI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG3__VI   regPB0_GLB_SCI_STAT_OVRD_REG3__VI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG4__CI   regPB0_GLB_SCI_STAT_OVRD_REG4__CI;
typedef union PB0_GLB_SCI_STAT_OVRD_REG4__VI   regPB0_GLB_SCI_STAT_OVRD_REG4__VI;
typedef union PB0_HW_DEBUG__CI                 regPB0_HW_DEBUG__CI;
typedef union PB0_HW_DEBUG__VI                 regPB0_HW_DEBUG__VI;
typedef union PB0_PIF_CNTL2__CI                regPB0_PIF_CNTL2__CI;
typedef union PB0_PIF_CNTL__CI                 regPB0_PIF_CNTL__CI;
typedef union PB0_PIF_HW_DEBUG__CI             regPB0_PIF_HW_DEBUG__CI;
typedef union PB0_PIF_HW_DEBUG__VI             regPB0_PIF_HW_DEBUG__VI;
typedef union PB0_PIF_PAIRING__CI              regPB0_PIF_PAIRING__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_0__CI      regPB0_PIF_PDNB_OVERRIDE_0__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_10__CI     regPB0_PIF_PDNB_OVERRIDE_10__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_11__CI     regPB0_PIF_PDNB_OVERRIDE_11__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_12__CI     regPB0_PIF_PDNB_OVERRIDE_12__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_13__CI     regPB0_PIF_PDNB_OVERRIDE_13__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_14__CI     regPB0_PIF_PDNB_OVERRIDE_14__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_15__CI     regPB0_PIF_PDNB_OVERRIDE_15__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_1__CI      regPB0_PIF_PDNB_OVERRIDE_1__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_2__CI      regPB0_PIF_PDNB_OVERRIDE_2__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_3__CI      regPB0_PIF_PDNB_OVERRIDE_3__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_4__CI      regPB0_PIF_PDNB_OVERRIDE_4__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_5__CI      regPB0_PIF_PDNB_OVERRIDE_5__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_6__CI      regPB0_PIF_PDNB_OVERRIDE_6__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_7__CI      regPB0_PIF_PDNB_OVERRIDE_7__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_8__CI      regPB0_PIF_PDNB_OVERRIDE_8__CI;
typedef union PB0_PIF_PDNB_OVERRIDE_9__CI      regPB0_PIF_PDNB_OVERRIDE_9__CI;
typedef union PB0_PIF_PWRDOWN_0__CI            regPB0_PIF_PWRDOWN_0__CI;
typedef union PB0_PIF_PWRDOWN_1__CI            regPB0_PIF_PWRDOWN_1__CI;
typedef union PB0_PIF_PWRDOWN_2__CI            regPB0_PIF_PWRDOWN_2__CI;
typedef union PB0_PIF_PWRDOWN_3__CI            regPB0_PIF_PWRDOWN_3__CI;
typedef union PB0_PIF_SCRATCH__CI__VI          regPB0_PIF_SCRATCH__CI__VI;
typedef union PB0_PIF_SC_CTL__CI               regPB0_PIF_SC_CTL__CI;
typedef union PB0_PIF_SEQ_STATUS_0__CI         regPB0_PIF_SEQ_STATUS_0__CI;
typedef union PB0_PIF_SEQ_STATUS_10__CI        regPB0_PIF_SEQ_STATUS_10__CI;
typedef union PB0_PIF_SEQ_STATUS_11__CI        regPB0_PIF_SEQ_STATUS_11__CI;
typedef union PB0_PIF_SEQ_STATUS_12__CI        regPB0_PIF_SEQ_STATUS_12__CI;
typedef union PB0_PIF_SEQ_STATUS_13__CI        regPB0_PIF_SEQ_STATUS_13__CI;
typedef union PB0_PIF_SEQ_STATUS_14__CI        regPB0_PIF_SEQ_STATUS_14__CI;
typedef union PB0_PIF_SEQ_STATUS_15__CI        regPB0_PIF_SEQ_STATUS_15__CI;
typedef union PB0_PIF_SEQ_STATUS_1__CI         regPB0_PIF_SEQ_STATUS_1__CI;
typedef union PB0_PIF_SEQ_STATUS_2__CI         regPB0_PIF_SEQ_STATUS_2__CI;
typedef union PB0_PIF_SEQ_STATUS_3__CI         regPB0_PIF_SEQ_STATUS_3__CI;
typedef union PB0_PIF_SEQ_STATUS_4__CI         regPB0_PIF_SEQ_STATUS_4__CI;
typedef union PB0_PIF_SEQ_STATUS_5__CI         regPB0_PIF_SEQ_STATUS_5__CI;
typedef union PB0_PIF_SEQ_STATUS_6__CI         regPB0_PIF_SEQ_STATUS_6__CI;
typedef union PB0_PIF_SEQ_STATUS_7__CI         regPB0_PIF_SEQ_STATUS_7__CI;
typedef union PB0_PIF_SEQ_STATUS_8__CI         regPB0_PIF_SEQ_STATUS_8__CI;
typedef union PB0_PIF_SEQ_STATUS_9__CI         regPB0_PIF_SEQ_STATUS_9__CI;
typedef union PB0_PIF_TXPHYSTATUS__CI          regPB0_PIF_TXPHYSTATUS__CI;
typedef union PB0_PLL_LC0_CTRL_REG0__CI__VI    regPB0_PLL_LC0_CTRL_REG0__CI__VI;
typedef union PB0_PLL_LC0_OVRD_REG0__CI__VI    regPB0_PLL_LC0_OVRD_REG0__CI__VI;
typedef union PB0_PLL_LC0_OVRD_REG1__CI__VI    regPB0_PLL_LC0_OVRD_REG1__CI__VI;
typedef union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC0_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_LC0_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC0_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC1_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_LC1_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC1_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC2_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_LC2_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC2_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__CI regPB0_PLL_LC3_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_LC3_SCI_STAT_OVRD_REG0__VI regPB0_PLL_LC3_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_RO0_CTRL_REG0__CI__VI    regPB0_PLL_RO0_CTRL_REG0__CI__VI;
typedef union PB0_PLL_RO0_OVRD_REG0__CI__VI    regPB0_PLL_RO0_OVRD_REG0__CI__VI;
typedef union PB0_PLL_RO0_OVRD_REG1__CI__VI    regPB0_PLL_RO0_OVRD_REG1__CI__VI;
typedef union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO0_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_RO0_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO0_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO1_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_RO1_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO1_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO2_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_RO2_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO2_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__CI regPB0_PLL_RO3_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_PLL_RO3_SCI_STAT_OVRD_REG0__VI regPB0_PLL_RO3_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_PLL_RO_GLB_CTRL_REG0__CI     regPB0_PLL_RO_GLB_CTRL_REG0__CI;
typedef union PB0_PLL_RO_GLB_CTRL_REG0__VI     regPB0_PLL_RO_GLB_CTRL_REG0__VI;
typedef union PB0_RX_GLB_CTRL_REG0__CI__VI     regPB0_RX_GLB_CTRL_REG0__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG1__CI__VI     regPB0_RX_GLB_CTRL_REG1__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG2__CI__VI     regPB0_RX_GLB_CTRL_REG2__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG3__CI__VI     regPB0_RX_GLB_CTRL_REG3__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG4__CI__VI     regPB0_RX_GLB_CTRL_REG4__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG5__CI__VI     regPB0_RX_GLB_CTRL_REG5__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG6__CI__VI     regPB0_RX_GLB_CTRL_REG6__CI__VI;
typedef union PB0_RX_GLB_CTRL_REG7__CI         regPB0_RX_GLB_CTRL_REG7__CI;
typedef union PB0_RX_GLB_CTRL_REG7__VI         regPB0_RX_GLB_CTRL_REG7__VI;
typedef union PB0_RX_GLB_CTRL_REG8__CI__VI     regPB0_RX_GLB_CTRL_REG8__CI__VI;
typedef union PB0_RX_GLB_OVRD_REG0__CI__VI     regPB0_RX_GLB_OVRD_REG0__CI__VI;
typedef union PB0_RX_GLB_OVRD_REG1__CI__VI     regPB0_RX_GLB_OVRD_REG1__CI__VI;
typedef union PB0_RX_GLB_SCI_STAT_OVRD_REG0__CI regPB0_RX_GLB_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_GLB_SCI_STAT_OVRD_REG0__VI regPB0_RX_GLB_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE0_CTRL_REG0__CI__VI   regPB0_RX_LANE0_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE0_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE0_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE0_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE10_CTRL_REG0__CI__VI  regPB0_RX_LANE10_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE10_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE10_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE10_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE11_CTRL_REG0__CI__VI  regPB0_RX_LANE11_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE11_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE11_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE11_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE12_CTRL_REG0__CI__VI  regPB0_RX_LANE12_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE12_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE12_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE12_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE13_CTRL_REG0__CI__VI  regPB0_RX_LANE13_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE13_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE13_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE13_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE14_CTRL_REG0__CI__VI  regPB0_RX_LANE14_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE14_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE14_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE14_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE15_CTRL_REG0__CI__VI  regPB0_RX_LANE15_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE15_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE15_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE15_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE1_CTRL_REG0__CI__VI   regPB0_RX_LANE1_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE1_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE1_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE1_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE2_CTRL_REG0__CI__VI   regPB0_RX_LANE2_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE2_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE2_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE2_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE3_CTRL_REG0__CI__VI   regPB0_RX_LANE3_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE3_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE3_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE3_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE4_CTRL_REG0__CI__VI   regPB0_RX_LANE4_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE4_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE4_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE4_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE5_CTRL_REG0__CI__VI   regPB0_RX_LANE5_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE5_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE5_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE5_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE6_CTRL_REG0__CI__VI   regPB0_RX_LANE6_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE6_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE6_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE6_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE7_CTRL_REG0__CI__VI   regPB0_RX_LANE7_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE7_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE7_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE7_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE8_CTRL_REG0__CI__VI   regPB0_RX_LANE8_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE8_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE8_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE8_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_RX_LANE9_CTRL_REG0__CI__VI   regPB0_RX_LANE9_CTRL_REG0__CI__VI;
typedef union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__CI regPB0_RX_LANE9_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_RX_LANE9_SCI_STAT_OVRD_REG0__VI regPB0_RX_LANE9_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_STRAP_GLB_REG0__CI__VI       regPB0_STRAP_GLB_REG0__CI__VI;
typedef union PB0_STRAP_PIN_REG0__CI__VI       regPB0_STRAP_PIN_REG0__CI__VI;
typedef union PB0_STRAP_PLL_REG0__CI__VI       regPB0_STRAP_PLL_REG0__CI__VI;
typedef union PB0_STRAP_RX_REG0__CI__VI        regPB0_STRAP_RX_REG0__CI__VI;
typedef union PB0_STRAP_RX_REG1__CI__VI        regPB0_STRAP_RX_REG1__CI__VI;
typedef union PB0_STRAP_TX_REG0__CI__VI        regPB0_STRAP_TX_REG0__CI__VI;
typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI;
typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI;
typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI;
typedef union PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI regPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI;
typedef union PB0_TX_GLB_CTRL_REG0__CI         regPB0_TX_GLB_CTRL_REG0__CI;
typedef union PB0_TX_GLB_CTRL_REG0__VI         regPB0_TX_GLB_CTRL_REG0__VI;
typedef union PB0_TX_GLB_LANE_SKEW_CTRL__CI__VI regPB0_TX_GLB_LANE_SKEW_CTRL__CI__VI;
typedef union PB0_TX_GLB_OVRD_REG0__CI__VI     regPB0_TX_GLB_OVRD_REG0__CI__VI;
typedef union PB0_TX_GLB_OVRD_REG1__CI__VI     regPB0_TX_GLB_OVRD_REG1__CI__VI;
typedef union PB0_TX_GLB_OVRD_REG2__CI__VI     regPB0_TX_GLB_OVRD_REG2__CI__VI;
typedef union PB0_TX_GLB_OVRD_REG3__CI__VI     regPB0_TX_GLB_OVRD_REG3__CI__VI;
typedef union PB0_TX_GLB_OVRD_REG4__CI__VI     regPB0_TX_GLB_OVRD_REG4__CI__VI;
typedef union PB0_TX_GLB_SCI_STAT_OVRD_REG0__CI regPB0_TX_GLB_SCI_STAT_OVRD_REG0__CI;
typedef union PB0_TX_GLB_SCI_STAT_OVRD_REG0__VI regPB0_TX_GLB_SCI_STAT_OVRD_REG0__VI;
typedef union PB0_TX_LANE0_CTRL_REG0__CI__VI   regPB0_TX_LANE0_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE0_OVRD_REG0__CI__VI   regPB0_TX_LANE0_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE10_CTRL_REG0__CI__VI  regPB0_TX_LANE10_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE10_OVRD_REG0__CI__VI  regPB0_TX_LANE10_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE11_CTRL_REG0__CI__VI  regPB0_TX_LANE11_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE11_OVRD_REG0__CI__VI  regPB0_TX_LANE11_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE12_CTRL_REG0__CI__VI  regPB0_TX_LANE12_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE12_OVRD_REG0__CI__VI  regPB0_TX_LANE12_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE13_CTRL_REG0__CI__VI  regPB0_TX_LANE13_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE13_OVRD_REG0__CI__VI  regPB0_TX_LANE13_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE14_CTRL_REG0__CI__VI  regPB0_TX_LANE14_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE14_OVRD_REG0__CI__VI  regPB0_TX_LANE14_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE15_CTRL_REG0__CI__VI  regPB0_TX_LANE15_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE15_OVRD_REG0__CI__VI  regPB0_TX_LANE15_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE1_CTRL_REG0__CI__VI   regPB0_TX_LANE1_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE1_OVRD_REG0__CI__VI   regPB0_TX_LANE1_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE2_CTRL_REG0__CI__VI   regPB0_TX_LANE2_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE2_OVRD_REG0__CI__VI   regPB0_TX_LANE2_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE3_CTRL_REG0__CI__VI   regPB0_TX_LANE3_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE3_OVRD_REG0__CI__VI   regPB0_TX_LANE3_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE4_CTRL_REG0__CI__VI   regPB0_TX_LANE4_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE4_OVRD_REG0__CI__VI   regPB0_TX_LANE4_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE5_CTRL_REG0__CI__VI   regPB0_TX_LANE5_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE5_OVRD_REG0__CI__VI   regPB0_TX_LANE5_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE6_CTRL_REG0__CI__VI   regPB0_TX_LANE6_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE6_OVRD_REG0__CI__VI   regPB0_TX_LANE6_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE7_CTRL_REG0__CI__VI   regPB0_TX_LANE7_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE7_OVRD_REG0__CI__VI   regPB0_TX_LANE7_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE8_CTRL_REG0__CI__VI   regPB0_TX_LANE8_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE8_OVRD_REG0__CI__VI   regPB0_TX_LANE8_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE9_CTRL_REG0__CI__VI   regPB0_TX_LANE9_CTRL_REG0__CI__VI;
typedef union PB0_TX_LANE9_OVRD_REG0__CI__VI   regPB0_TX_LANE9_OVRD_REG0__CI__VI;
typedef union PB0_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI regPB0_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_DFT_DEBUG_CTRL_REG0__CI__VI  regPB1_DFT_DEBUG_CTRL_REG0__CI__VI;
typedef union PB1_DFT_JIT_INJ_REG0__CI__VI     regPB1_DFT_JIT_INJ_REG0__CI__VI;
typedef union PB1_DFT_JIT_INJ_REG1__CI__VI     regPB1_DFT_JIT_INJ_REG1__CI__VI;
typedef union PB1_DFT_JIT_INJ_REG2__CI__VI     regPB1_DFT_JIT_INJ_REG2__CI__VI;
typedef union PB1_DFT_JIT_INJ_STAT_REG0__CI__VI regPB1_DFT_JIT_INJ_STAT_REG0__CI__VI;
typedef union PB1_GLB_CTRL_REG0__CI__VI        regPB1_GLB_CTRL_REG0__CI__VI;
typedef union PB1_GLB_CTRL_REG1__CI__VI        regPB1_GLB_CTRL_REG1__CI__VI;
typedef union PB1_GLB_CTRL_REG2__CI__VI        regPB1_GLB_CTRL_REG2__CI__VI;
typedef union PB1_GLB_CTRL_REG3__CI__VI        regPB1_GLB_CTRL_REG3__CI__VI;
typedef union PB1_GLB_CTRL_REG4__CI__VI        regPB1_GLB_CTRL_REG4__CI__VI;
typedef union PB1_GLB_CTRL_REG5__CI__VI        regPB1_GLB_CTRL_REG5__CI__VI;
typedef union PB1_GLB_OVRD_REG0__CI__VI        regPB1_GLB_OVRD_REG0__CI__VI;
typedef union PB1_GLB_OVRD_REG1__CI__VI        regPB1_GLB_OVRD_REG1__CI__VI;
typedef union PB1_GLB_OVRD_REG2__CI__VI        regPB1_GLB_OVRD_REG2__CI__VI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG0__CI   regPB1_GLB_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG0__VI   regPB1_GLB_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG1__CI   regPB1_GLB_SCI_STAT_OVRD_REG1__CI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG1__VI   regPB1_GLB_SCI_STAT_OVRD_REG1__VI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG2__CI   regPB1_GLB_SCI_STAT_OVRD_REG2__CI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG2__VI   regPB1_GLB_SCI_STAT_OVRD_REG2__VI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG3__CI   regPB1_GLB_SCI_STAT_OVRD_REG3__CI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG3__VI   regPB1_GLB_SCI_STAT_OVRD_REG3__VI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG4__CI   regPB1_GLB_SCI_STAT_OVRD_REG4__CI;
typedef union PB1_GLB_SCI_STAT_OVRD_REG4__VI   regPB1_GLB_SCI_STAT_OVRD_REG4__VI;
typedef union PB1_HW_DEBUG__CI                 regPB1_HW_DEBUG__CI;
typedef union PB1_HW_DEBUG__VI                 regPB1_HW_DEBUG__VI;
typedef union PB1_PIF_CNTL2__CI                regPB1_PIF_CNTL2__CI;
typedef union PB1_PIF_CNTL__CI                 regPB1_PIF_CNTL__CI;
typedef union PB1_PIF_HW_DEBUG__CI             regPB1_PIF_HW_DEBUG__CI;
typedef union PB1_PIF_HW_DEBUG__VI             regPB1_PIF_HW_DEBUG__VI;
typedef union PB1_PIF_PAIRING__CI              regPB1_PIF_PAIRING__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_0__CI      regPB1_PIF_PDNB_OVERRIDE_0__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_10__CI     regPB1_PIF_PDNB_OVERRIDE_10__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_11__CI     regPB1_PIF_PDNB_OVERRIDE_11__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_12__CI     regPB1_PIF_PDNB_OVERRIDE_12__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_13__CI     regPB1_PIF_PDNB_OVERRIDE_13__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_14__CI     regPB1_PIF_PDNB_OVERRIDE_14__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_15__CI     regPB1_PIF_PDNB_OVERRIDE_15__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_1__CI      regPB1_PIF_PDNB_OVERRIDE_1__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_2__CI      regPB1_PIF_PDNB_OVERRIDE_2__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_3__CI      regPB1_PIF_PDNB_OVERRIDE_3__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_4__CI      regPB1_PIF_PDNB_OVERRIDE_4__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_5__CI      regPB1_PIF_PDNB_OVERRIDE_5__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_6__CI      regPB1_PIF_PDNB_OVERRIDE_6__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_7__CI      regPB1_PIF_PDNB_OVERRIDE_7__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_8__CI      regPB1_PIF_PDNB_OVERRIDE_8__CI;
typedef union PB1_PIF_PDNB_OVERRIDE_9__CI      regPB1_PIF_PDNB_OVERRIDE_9__CI;
typedef union PB1_PIF_PWRDOWN_0__CI            regPB1_PIF_PWRDOWN_0__CI;
typedef union PB1_PIF_PWRDOWN_1__CI            regPB1_PIF_PWRDOWN_1__CI;
typedef union PB1_PIF_PWRDOWN_2__CI            regPB1_PIF_PWRDOWN_2__CI;
typedef union PB1_PIF_PWRDOWN_3__CI            regPB1_PIF_PWRDOWN_3__CI;
typedef union PB1_PIF_SCRATCH__CI__VI          regPB1_PIF_SCRATCH__CI__VI;
typedef union PB1_PIF_SC_CTL__CI               regPB1_PIF_SC_CTL__CI;
typedef union PB1_PIF_SEQ_STATUS_0__CI         regPB1_PIF_SEQ_STATUS_0__CI;
typedef union PB1_PIF_SEQ_STATUS_10__CI        regPB1_PIF_SEQ_STATUS_10__CI;
typedef union PB1_PIF_SEQ_STATUS_11__CI        regPB1_PIF_SEQ_STATUS_11__CI;
typedef union PB1_PIF_SEQ_STATUS_12__CI        regPB1_PIF_SEQ_STATUS_12__CI;
typedef union PB1_PIF_SEQ_STATUS_13__CI        regPB1_PIF_SEQ_STATUS_13__CI;
typedef union PB1_PIF_SEQ_STATUS_14__CI        regPB1_PIF_SEQ_STATUS_14__CI;
typedef union PB1_PIF_SEQ_STATUS_15__CI        regPB1_PIF_SEQ_STATUS_15__CI;
typedef union PB1_PIF_SEQ_STATUS_1__CI         regPB1_PIF_SEQ_STATUS_1__CI;
typedef union PB1_PIF_SEQ_STATUS_2__CI         regPB1_PIF_SEQ_STATUS_2__CI;
typedef union PB1_PIF_SEQ_STATUS_3__CI         regPB1_PIF_SEQ_STATUS_3__CI;
typedef union PB1_PIF_SEQ_STATUS_4__CI         regPB1_PIF_SEQ_STATUS_4__CI;
typedef union PB1_PIF_SEQ_STATUS_5__CI         regPB1_PIF_SEQ_STATUS_5__CI;
typedef union PB1_PIF_SEQ_STATUS_6__CI         regPB1_PIF_SEQ_STATUS_6__CI;
typedef union PB1_PIF_SEQ_STATUS_7__CI         regPB1_PIF_SEQ_STATUS_7__CI;
typedef union PB1_PIF_SEQ_STATUS_8__CI         regPB1_PIF_SEQ_STATUS_8__CI;
typedef union PB1_PIF_SEQ_STATUS_9__CI         regPB1_PIF_SEQ_STATUS_9__CI;
typedef union PB1_PIF_TXPHYSTATUS__CI          regPB1_PIF_TXPHYSTATUS__CI;
typedef union PB1_PLL_LC0_CTRL_REG0__CI__VI    regPB1_PLL_LC0_CTRL_REG0__CI__VI;
typedef union PB1_PLL_LC0_OVRD_REG0__CI__VI    regPB1_PLL_LC0_OVRD_REG0__CI__VI;
typedef union PB1_PLL_LC0_OVRD_REG1__CI__VI    regPB1_PLL_LC0_OVRD_REG1__CI__VI;
typedef union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC0_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_LC0_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC0_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC1_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_LC1_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC1_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC2_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_LC2_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC2_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__CI regPB1_PLL_LC3_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_LC3_SCI_STAT_OVRD_REG0__VI regPB1_PLL_LC3_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_RO0_CTRL_REG0__CI__VI    regPB1_PLL_RO0_CTRL_REG0__CI__VI;
typedef union PB1_PLL_RO0_OVRD_REG0__CI__VI    regPB1_PLL_RO0_OVRD_REG0__CI__VI;
typedef union PB1_PLL_RO0_OVRD_REG1__CI__VI    regPB1_PLL_RO0_OVRD_REG1__CI__VI;
typedef union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO0_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_RO0_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO0_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO1_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_RO1_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO1_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO2_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_RO2_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO2_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__CI regPB1_PLL_RO3_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_PLL_RO3_SCI_STAT_OVRD_REG0__VI regPB1_PLL_RO3_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_PLL_RO_GLB_CTRL_REG0__CI     regPB1_PLL_RO_GLB_CTRL_REG0__CI;
typedef union PB1_PLL_RO_GLB_CTRL_REG0__VI     regPB1_PLL_RO_GLB_CTRL_REG0__VI;
typedef union PB1_RX_GLB_CTRL_REG0__CI__VI     regPB1_RX_GLB_CTRL_REG0__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG1__CI__VI     regPB1_RX_GLB_CTRL_REG1__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG2__CI__VI     regPB1_RX_GLB_CTRL_REG2__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG3__CI__VI     regPB1_RX_GLB_CTRL_REG3__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG4__CI__VI     regPB1_RX_GLB_CTRL_REG4__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG5__CI__VI     regPB1_RX_GLB_CTRL_REG5__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG6__CI__VI     regPB1_RX_GLB_CTRL_REG6__CI__VI;
typedef union PB1_RX_GLB_CTRL_REG7__CI         regPB1_RX_GLB_CTRL_REG7__CI;
typedef union PB1_RX_GLB_CTRL_REG7__VI         regPB1_RX_GLB_CTRL_REG7__VI;
typedef union PB1_RX_GLB_CTRL_REG8__CI__VI     regPB1_RX_GLB_CTRL_REG8__CI__VI;
typedef union PB1_RX_GLB_OVRD_REG0__CI__VI     regPB1_RX_GLB_OVRD_REG0__CI__VI;
typedef union PB1_RX_GLB_OVRD_REG1__CI__VI     regPB1_RX_GLB_OVRD_REG1__CI__VI;
typedef union PB1_RX_GLB_SCI_STAT_OVRD_REG0__CI regPB1_RX_GLB_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_GLB_SCI_STAT_OVRD_REG0__VI regPB1_RX_GLB_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE0_CTRL_REG0__CI__VI   regPB1_RX_LANE0_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE0_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE0_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE0_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE10_CTRL_REG0__CI__VI  regPB1_RX_LANE10_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE10_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE10_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE10_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE11_CTRL_REG0__CI__VI  regPB1_RX_LANE11_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE11_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE11_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE11_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE12_CTRL_REG0__CI__VI  regPB1_RX_LANE12_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE12_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE12_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE12_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE13_CTRL_REG0__CI__VI  regPB1_RX_LANE13_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE13_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE13_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE13_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE14_CTRL_REG0__CI__VI  regPB1_RX_LANE14_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE14_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE14_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE14_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE15_CTRL_REG0__CI__VI  regPB1_RX_LANE15_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE15_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE15_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE15_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE1_CTRL_REG0__CI__VI   regPB1_RX_LANE1_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE1_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE1_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE1_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE2_CTRL_REG0__CI__VI   regPB1_RX_LANE2_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE2_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE2_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE2_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE3_CTRL_REG0__CI__VI   regPB1_RX_LANE3_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE3_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE3_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE3_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE4_CTRL_REG0__CI__VI   regPB1_RX_LANE4_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE4_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE4_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE4_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE5_CTRL_REG0__CI__VI   regPB1_RX_LANE5_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE5_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE5_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE5_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE6_CTRL_REG0__CI__VI   regPB1_RX_LANE6_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE6_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE6_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE6_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE7_CTRL_REG0__CI__VI   regPB1_RX_LANE7_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE7_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE7_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE7_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE8_CTRL_REG0__CI__VI   regPB1_RX_LANE8_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE8_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE8_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE8_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_RX_LANE9_CTRL_REG0__CI__VI   regPB1_RX_LANE9_CTRL_REG0__CI__VI;
typedef union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__CI regPB1_RX_LANE9_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_RX_LANE9_SCI_STAT_OVRD_REG0__VI regPB1_RX_LANE9_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_STRAP_GLB_REG0__CI__VI       regPB1_STRAP_GLB_REG0__CI__VI;
typedef union PB1_STRAP_PIN_REG0__CI__VI       regPB1_STRAP_PIN_REG0__CI__VI;
typedef union PB1_STRAP_PLL_REG0__CI__VI       regPB1_STRAP_PLL_REG0__CI__VI;
typedef union PB1_STRAP_RX_REG0__CI__VI        regPB1_STRAP_RX_REG0__CI__VI;
typedef union PB1_STRAP_RX_REG1__CI__VI        regPB1_STRAP_RX_REG1__CI__VI;
typedef union PB1_STRAP_TX_REG0__CI__VI        regPB1_STRAP_TX_REG0__CI__VI;
typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__CI__VI;
typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__CI__VI;
typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__CI__VI;
typedef union PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI regPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__CI__VI;
typedef union PB1_TX_GLB_CTRL_REG0__CI         regPB1_TX_GLB_CTRL_REG0__CI;
typedef union PB1_TX_GLB_CTRL_REG0__VI         regPB1_TX_GLB_CTRL_REG0__VI;
typedef union PB1_TX_GLB_LANE_SKEW_CTRL__CI__VI regPB1_TX_GLB_LANE_SKEW_CTRL__CI__VI;
typedef union PB1_TX_GLB_OVRD_REG0__CI__VI     regPB1_TX_GLB_OVRD_REG0__CI__VI;
typedef union PB1_TX_GLB_OVRD_REG1__CI__VI     regPB1_TX_GLB_OVRD_REG1__CI__VI;
typedef union PB1_TX_GLB_OVRD_REG2__CI__VI     regPB1_TX_GLB_OVRD_REG2__CI__VI;
typedef union PB1_TX_GLB_OVRD_REG3__CI__VI     regPB1_TX_GLB_OVRD_REG3__CI__VI;
typedef union PB1_TX_GLB_OVRD_REG4__CI__VI     regPB1_TX_GLB_OVRD_REG4__CI__VI;
typedef union PB1_TX_GLB_SCI_STAT_OVRD_REG0__CI regPB1_TX_GLB_SCI_STAT_OVRD_REG0__CI;
typedef union PB1_TX_GLB_SCI_STAT_OVRD_REG0__VI regPB1_TX_GLB_SCI_STAT_OVRD_REG0__VI;
typedef union PB1_TX_LANE0_CTRL_REG0__CI__VI   regPB1_TX_LANE0_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE0_OVRD_REG0__CI__VI   regPB1_TX_LANE0_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE0_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE10_CTRL_REG0__CI__VI  regPB1_TX_LANE10_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE10_OVRD_REG0__CI__VI  regPB1_TX_LANE10_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE10_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE11_CTRL_REG0__CI__VI  regPB1_TX_LANE11_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE11_OVRD_REG0__CI__VI  regPB1_TX_LANE11_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE11_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE12_CTRL_REG0__CI__VI  regPB1_TX_LANE12_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE12_OVRD_REG0__CI__VI  regPB1_TX_LANE12_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE12_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE13_CTRL_REG0__CI__VI  regPB1_TX_LANE13_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE13_OVRD_REG0__CI__VI  regPB1_TX_LANE13_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE13_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE14_CTRL_REG0__CI__VI  regPB1_TX_LANE14_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE14_OVRD_REG0__CI__VI  regPB1_TX_LANE14_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE14_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE15_CTRL_REG0__CI__VI  regPB1_TX_LANE15_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE15_OVRD_REG0__CI__VI  regPB1_TX_LANE15_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE15_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE1_CTRL_REG0__CI__VI   regPB1_TX_LANE1_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE1_OVRD_REG0__CI__VI   regPB1_TX_LANE1_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE1_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE2_CTRL_REG0__CI__VI   regPB1_TX_LANE2_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE2_OVRD_REG0__CI__VI   regPB1_TX_LANE2_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE2_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE3_CTRL_REG0__CI__VI   regPB1_TX_LANE3_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE3_OVRD_REG0__CI__VI   regPB1_TX_LANE3_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE3_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE4_CTRL_REG0__CI__VI   regPB1_TX_LANE4_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE4_OVRD_REG0__CI__VI   regPB1_TX_LANE4_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE4_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE5_CTRL_REG0__CI__VI   regPB1_TX_LANE5_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE5_OVRD_REG0__CI__VI   regPB1_TX_LANE5_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE5_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE6_CTRL_REG0__CI__VI   regPB1_TX_LANE6_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE6_OVRD_REG0__CI__VI   regPB1_TX_LANE6_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE6_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE7_CTRL_REG0__CI__VI   regPB1_TX_LANE7_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE7_OVRD_REG0__CI__VI   regPB1_TX_LANE7_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE7_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE8_CTRL_REG0__CI__VI   regPB1_TX_LANE8_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE8_OVRD_REG0__CI__VI   regPB1_TX_LANE8_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE8_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE9_CTRL_REG0__CI__VI   regPB1_TX_LANE9_CTRL_REG0__CI__VI;
typedef union PB1_TX_LANE9_OVRD_REG0__CI__VI   regPB1_TX_LANE9_OVRD_REG0__CI__VI;
typedef union PB1_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI regPB1_TX_LANE9_SCI_STAT_OVRD_REG0__CI__VI;
typedef union PCIEP_BCH_ECC_CNTL__CI__VI       regPCIEP_BCH_ECC_CNTL__CI__VI;
typedef union PCIEP_HW_DEBUG                   regPCIEP_HW_DEBUG;
typedef union PCIEP_PORT_CNTL__CI__VI          regPCIEP_PORT_CNTL__CI__VI;
typedef union PCIEP_PORT_CNTL__SI              regPCIEP_PORT_CNTL__SI;
typedef union PCIEP_RESERVED                   regPCIEP_RESERVED;
typedef union PCIEP_SCRATCH                    regPCIEP_SCRATCH;
typedef union PCIEP_STRAP_LC                   regPCIEP_STRAP_LC;
typedef union PCIEP_STRAP_MISC__CI__VI         regPCIEP_STRAP_MISC__CI__VI;
typedef union PCIEP_STRAP_MISC__SI             regPCIEP_STRAP_MISC__SI;
typedef union PCIE_ACS_CAP__CI__VI             regPCIE_ACS_CAP__CI__VI;
typedef union PCIE_ACS_CNTL__CI__VI            regPCIE_ACS_CNTL__CI__VI;
typedef union PCIE_ACS_ENH_CAP_LIST__CI__VI    regPCIE_ACS_ENH_CAP_LIST__CI__VI;
typedef union PCIE_ADV_ERR_CAP_CNTL__SI__CI    regPCIE_ADV_ERR_CAP_CNTL__SI__CI;
typedef union PCIE_ADV_ERR_CAP_CNTL__VI        regPCIE_ADV_ERR_CAP_CNTL__VI;
typedef union PCIE_ADV_ERR_RPT_ENH_CAP_LIST    regPCIE_ADV_ERR_RPT_ENH_CAP_LIST;
typedef union PCIE_ATS_CAP__CI                 regPCIE_ATS_CAP__CI;
typedef union PCIE_ATS_CAP__VI                 regPCIE_ATS_CAP__VI;
typedef union PCIE_ATS_CNTL__CI__VI            regPCIE_ATS_CNTL__CI__VI;
typedef union PCIE_ATS_ENH_CAP_LIST__CI__VI    regPCIE_ATS_ENH_CAP_LIST__CI__VI;
typedef union PCIE_BAR1_CAP__CI__VI            regPCIE_BAR1_CAP__CI__VI;
typedef union PCIE_BAR1_CNTL__CI__VI           regPCIE_BAR1_CNTL__CI__VI;
typedef union PCIE_BAR2_CAP__CI__VI            regPCIE_BAR2_CAP__CI__VI;
typedef union PCIE_BAR2_CNTL__CI__VI           regPCIE_BAR2_CNTL__CI__VI;
typedef union PCIE_BAR3_CAP__CI__VI            regPCIE_BAR3_CAP__CI__VI;
typedef union PCIE_BAR3_CNTL__CI__VI           regPCIE_BAR3_CNTL__CI__VI;
typedef union PCIE_BAR4_CAP__CI__VI            regPCIE_BAR4_CAP__CI__VI;
typedef union PCIE_BAR4_CNTL__CI__VI           regPCIE_BAR4_CNTL__CI__VI;
typedef union PCIE_BAR5_CAP__CI__VI            regPCIE_BAR5_CAP__CI__VI;
typedef union PCIE_BAR5_CNTL__CI__VI           regPCIE_BAR5_CNTL__CI__VI;
typedef union PCIE_BAR6_CAP__CI__VI            regPCIE_BAR6_CAP__CI__VI;
typedef union PCIE_BAR6_CNTL__CI__VI           regPCIE_BAR6_CNTL__CI__VI;
typedef union PCIE_BAR_ENH_CAP_LIST__CI__VI    regPCIE_BAR_ENH_CAP_LIST__CI__VI;
typedef union PCIE_BUS_CNTL                    regPCIE_BUS_CNTL;
typedef union PCIE_CAP                         regPCIE_CAP;
typedef union PCIE_CAP_LIST                    regPCIE_CAP_LIST;
typedef union PCIE_CFG_CNTL__CI__VI            regPCIE_CFG_CNTL__CI__VI;
typedef union PCIE_CFG_CNTL__SI                regPCIE_CFG_CNTL__SI;
typedef union PCIE_CI_CNTL__CI__VI             regPCIE_CI_CNTL__CI__VI;
typedef union PCIE_CI_CNTL__SI                 regPCIE_CI_CNTL__SI;
typedef union PCIE_CNTL2                       regPCIE_CNTL2;
typedef union PCIE_CNTL__CI                    regPCIE_CNTL__CI;
typedef union PCIE_CNTL__VI                    regPCIE_CNTL__VI;
typedef union PCIE_CNTL__SI                    regPCIE_CNTL__SI;
typedef union PCIE_CONFIG_CNTL                 regPCIE_CONFIG_CNTL;
typedef union PCIE_CORR_ERR_MASK               regPCIE_CORR_ERR_MASK;
typedef union PCIE_CORR_ERR_STATUS             regPCIE_CORR_ERR_STATUS;
typedef union PCIE_DATA                        regPCIE_DATA;
typedef union PCIE_DATA_2__CI__VI              regPCIE_DATA_2__CI__VI;
typedef union PCIE_DEBUG_CNTL                  regPCIE_DEBUG_CNTL;
typedef union PCIE_DEV_SERIAL_NUM_DW1          regPCIE_DEV_SERIAL_NUM_DW1;
typedef union PCIE_DEV_SERIAL_NUM_DW2          regPCIE_DEV_SERIAL_NUM_DW2;
typedef union PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST regPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST;
typedef union PCIE_DPA_CAP__CI__VI             regPCIE_DPA_CAP__CI__VI;
typedef union PCIE_DPA_CNTL__CI__VI            regPCIE_DPA_CNTL__CI__VI;
typedef union PCIE_DPA_ENH_CAP_LIST__CI__VI    regPCIE_DPA_ENH_CAP_LIST__CI__VI;
typedef union PCIE_DPA_LATENCY_INDICATOR__CI__VI regPCIE_DPA_LATENCY_INDICATOR__CI__VI;
typedef union PCIE_DPA_STATUS__CI__VI          regPCIE_DPA_STATUS__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI;
typedef union PCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI regPCIE_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI;
typedef union PCIE_ERR_CNTL__CI__VI            regPCIE_ERR_CNTL__CI__VI;
typedef union PCIE_ERR_CNTL__SI                regPCIE_ERR_CNTL__SI;
typedef union PCIE_F0_DPA_CAP__CI__VI          regPCIE_F0_DPA_CAP__CI__VI;
typedef union PCIE_F0_DPA_CNTL__CI__VI         regPCIE_F0_DPA_CNTL__CI__VI;
typedef union PCIE_F0_DPA_LATENCY_INDICATOR__CI__VI regPCIE_F0_DPA_LATENCY_INDICATOR__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__CI__VI;
typedef union PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI regPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__CI__VI;
typedef union PCIE_FC_CPL                      regPCIE_FC_CPL;
typedef union PCIE_FC_NP                       regPCIE_FC_NP;
typedef union PCIE_FC_P                        regPCIE_FC_P;
typedef union PCIE_HDR_LOG0                    regPCIE_HDR_LOG0;
typedef union PCIE_HDR_LOG1                    regPCIE_HDR_LOG1;
typedef union PCIE_HDR_LOG2                    regPCIE_HDR_LOG2;
typedef union PCIE_HDR_LOG3                    regPCIE_HDR_LOG3;
typedef union PCIE_HW_DEBUG                    regPCIE_HW_DEBUG;
typedef union PCIE_I2C_REG_ADDR_EXPAND         regPCIE_I2C_REG_ADDR_EXPAND;
typedef union PCIE_I2C_REG_DATA                regPCIE_I2C_REG_DATA;
typedef union PCIE_INDEX_2__CI__VI             regPCIE_INDEX_2__CI__VI;
typedef union PCIE_INDEX__CI__VI               regPCIE_INDEX__CI__VI;
typedef union PCIE_INDEX__SI                   regPCIE_INDEX__SI;
typedef union PCIE_INT_CNTL                    regPCIE_INT_CNTL;
typedef union PCIE_INT_STATUS                  regPCIE_INT_STATUS;
typedef union PCIE_LANE_0_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_0_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_10_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_10_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_11_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_11_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_12_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_12_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_13_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_13_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_14_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_14_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_15_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_15_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_1_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_1_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_2_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_2_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_3_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_3_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_4_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_4_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_5_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_5_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_6_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_6_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_7_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_7_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_8_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_8_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_9_EQUALIZATION_CNTL__CI__VI regPCIE_LANE_9_EQUALIZATION_CNTL__CI__VI;
typedef union PCIE_LANE_ERROR_STATUS__CI__VI   regPCIE_LANE_ERROR_STATUS__CI__VI;
typedef union PCIE_LC_BW_CHANGE_CNTL           regPCIE_LC_BW_CHANGE_CNTL;
typedef union PCIE_LC_CDR_CNTL                 regPCIE_LC_CDR_CNTL;
typedef union PCIE_LC_CNTL                     regPCIE_LC_CNTL;
typedef union PCIE_LC_CNTL2__CI__VI            regPCIE_LC_CNTL2__CI__VI;
typedef union PCIE_LC_CNTL2__SI                regPCIE_LC_CNTL2__SI;
typedef union PCIE_LC_CNTL3                    regPCIE_LC_CNTL3;
typedef union PCIE_LC_CNTL4__CI                regPCIE_LC_CNTL4__CI;
typedef union PCIE_LC_CNTL4__VI                regPCIE_LC_CNTL4__VI;
typedef union PCIE_LC_CNTL5__CI__VI            regPCIE_LC_CNTL5__CI__VI;
typedef union PCIE_LC_FORCE_COEFF__CI__VI      regPCIE_LC_FORCE_COEFF__CI__VI;
typedef union PCIE_LC_LANE_CNTL                regPCIE_LC_LANE_CNTL;
typedef union PCIE_LC_LINK_WIDTH_CNTL          regPCIE_LC_LINK_WIDTH_CNTL;
typedef union PCIE_LC_N_FTS_CNTL               regPCIE_LC_N_FTS_CNTL;
typedef union PCIE_LC_SPEED_CNTL__CI__VI       regPCIE_LC_SPEED_CNTL__CI__VI;
typedef union PCIE_LC_SPEED_CNTL__SI           regPCIE_LC_SPEED_CNTL__SI;
typedef union PCIE_LC_STATE0                   regPCIE_LC_STATE0;
typedef union PCIE_LC_STATE1                   regPCIE_LC_STATE1;
typedef union PCIE_LC_STATE10                  regPCIE_LC_STATE10;
typedef union PCIE_LC_STATE11                  regPCIE_LC_STATE11;
typedef union PCIE_LC_STATE2                   regPCIE_LC_STATE2;
typedef union PCIE_LC_STATE3                   regPCIE_LC_STATE3;
typedef union PCIE_LC_STATE4                   regPCIE_LC_STATE4;
typedef union PCIE_LC_STATE5                   regPCIE_LC_STATE5;
typedef union PCIE_LC_STATE6                   regPCIE_LC_STATE6;
typedef union PCIE_LC_STATE7                   regPCIE_LC_STATE7;
typedef union PCIE_LC_STATE8                   regPCIE_LC_STATE8;
typedef union PCIE_LC_STATE9                   regPCIE_LC_STATE9;
typedef union PCIE_LC_STATUS1                  regPCIE_LC_STATUS1;
typedef union PCIE_LC_STATUS2                  regPCIE_LC_STATUS2;
typedef union PCIE_LC_TRAINING_CNTL__CI        regPCIE_LC_TRAINING_CNTL__CI;
typedef union PCIE_LC_TRAINING_CNTL__VI        regPCIE_LC_TRAINING_CNTL__VI;
typedef union PCIE_LC_TRAINING_CNTL__SI        regPCIE_LC_TRAINING_CNTL__SI;
typedef union PCIE_LINK_CNTL3__CI__VI          regPCIE_LINK_CNTL3__CI__VI;
typedef union PCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI regPCIE_OUTSTAND_PAGE_REQ_ALLOC__CI__VI;
typedef union PCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI regPCIE_OUTSTAND_PAGE_REQ_CAPACITY__CI__VI;
typedef union PCIE_PAGE_REQ_CNTL__CI__VI       regPCIE_PAGE_REQ_CNTL__CI__VI;
typedef union PCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI regPCIE_PAGE_REQ_ENH_CAP_LIST__CI__VI;
typedef union PCIE_PAGE_REQ_STATUS__CI__VI     regPCIE_PAGE_REQ_STATUS__CI__VI;
typedef union PCIE_PASID_CAP__CI__VI           regPCIE_PASID_CAP__CI__VI;
typedef union PCIE_PASID_CNTL__CI__VI          regPCIE_PASID_CNTL__CI__VI;
typedef union PCIE_PASID_ENH_CAP_LIST__CI__VI  regPCIE_PASID_ENH_CAP_LIST__CI__VI;
typedef union PCIE_PERF_CNTL_EVENT0_PORT_SEL   regPCIE_PERF_CNTL_EVENT0_PORT_SEL;
typedef union PCIE_PERF_CNTL_EVENT1_PORT_SEL   regPCIE_PERF_CNTL_EVENT1_PORT_SEL;
typedef union PCIE_PERF_CNTL_MST_C_CLK         regPCIE_PERF_CNTL_MST_C_CLK;
typedef union PCIE_PERF_CNTL_MST_R_CLK         regPCIE_PERF_CNTL_MST_R_CLK;
typedef union PCIE_PERF_CNTL_SLV_NS_C_CLK      regPCIE_PERF_CNTL_SLV_NS_C_CLK;
typedef union PCIE_PERF_CNTL_SLV_R_CLK         regPCIE_PERF_CNTL_SLV_R_CLK;
typedef union PCIE_PERF_CNTL_SLV_S_C_CLK       regPCIE_PERF_CNTL_SLV_S_C_CLK;
typedef union PCIE_PERF_CNTL_TXCLK             regPCIE_PERF_CNTL_TXCLK;
typedef union PCIE_PERF_CNTL_TXCLK2            regPCIE_PERF_CNTL_TXCLK2;
typedef union PCIE_PERF_COUNT0_MST_C_CLK       regPCIE_PERF_COUNT0_MST_C_CLK;
typedef union PCIE_PERF_COUNT0_MST_R_CLK       regPCIE_PERF_COUNT0_MST_R_CLK;
typedef union PCIE_PERF_COUNT0_SLV_NS_C_CLK    regPCIE_PERF_COUNT0_SLV_NS_C_CLK;
typedef union PCIE_PERF_COUNT0_SLV_R_CLK       regPCIE_PERF_COUNT0_SLV_R_CLK;
typedef union PCIE_PERF_COUNT0_SLV_S_C_CLK     regPCIE_PERF_COUNT0_SLV_S_C_CLK;
typedef union PCIE_PERF_COUNT0_TXCLK           regPCIE_PERF_COUNT0_TXCLK;
typedef union PCIE_PERF_COUNT0_TXCLK2          regPCIE_PERF_COUNT0_TXCLK2;
typedef union PCIE_PERF_COUNT1_MST_C_CLK       regPCIE_PERF_COUNT1_MST_C_CLK;
typedef union PCIE_PERF_COUNT1_MST_R_CLK       regPCIE_PERF_COUNT1_MST_R_CLK;
typedef union PCIE_PERF_COUNT1_SLV_NS_C_CLK    regPCIE_PERF_COUNT1_SLV_NS_C_CLK;
typedef union PCIE_PERF_COUNT1_SLV_R_CLK       regPCIE_PERF_COUNT1_SLV_R_CLK;
typedef union PCIE_PERF_COUNT1_SLV_S_C_CLK     regPCIE_PERF_COUNT1_SLV_S_C_CLK;
typedef union PCIE_PERF_COUNT1_TXCLK           regPCIE_PERF_COUNT1_TXCLK;
typedef union PCIE_PERF_COUNT1_TXCLK2          regPCIE_PERF_COUNT1_TXCLK2;
typedef union PCIE_PERF_COUNT_CNTL             regPCIE_PERF_COUNT_CNTL;
typedef union PCIE_PORT_DATA__SI               regPCIE_PORT_DATA__SI;
typedef union PCIE_PORT_INDEX__SI              regPCIE_PORT_INDEX__SI;
typedef union PCIE_PORT_VC_CAP_REG1            regPCIE_PORT_VC_CAP_REG1;
typedef union PCIE_PORT_VC_CAP_REG2            regPCIE_PORT_VC_CAP_REG2;
typedef union PCIE_PORT_VC_CNTL                regPCIE_PORT_VC_CNTL;
typedef union PCIE_PORT_VC_STATUS              regPCIE_PORT_VC_STATUS;
typedef union PCIE_PRBS_CLR                    regPCIE_PRBS_CLR;
typedef union PCIE_PRBS_ERRCNT_0               regPCIE_PRBS_ERRCNT_0;
typedef union PCIE_PRBS_ERRCNT_1               regPCIE_PRBS_ERRCNT_1;
typedef union PCIE_PRBS_ERRCNT_10              regPCIE_PRBS_ERRCNT_10;
typedef union PCIE_PRBS_ERRCNT_11              regPCIE_PRBS_ERRCNT_11;
typedef union PCIE_PRBS_ERRCNT_12              regPCIE_PRBS_ERRCNT_12;
typedef union PCIE_PRBS_ERRCNT_13              regPCIE_PRBS_ERRCNT_13;
typedef union PCIE_PRBS_ERRCNT_14              regPCIE_PRBS_ERRCNT_14;
typedef union PCIE_PRBS_ERRCNT_15              regPCIE_PRBS_ERRCNT_15;
typedef union PCIE_PRBS_ERRCNT_2               regPCIE_PRBS_ERRCNT_2;
typedef union PCIE_PRBS_ERRCNT_3               regPCIE_PRBS_ERRCNT_3;
typedef union PCIE_PRBS_ERRCNT_4               regPCIE_PRBS_ERRCNT_4;
typedef union PCIE_PRBS_ERRCNT_5               regPCIE_PRBS_ERRCNT_5;
typedef union PCIE_PRBS_ERRCNT_6               regPCIE_PRBS_ERRCNT_6;
typedef union PCIE_PRBS_ERRCNT_7               regPCIE_PRBS_ERRCNT_7;
typedef union PCIE_PRBS_ERRCNT_8               regPCIE_PRBS_ERRCNT_8;
typedef union PCIE_PRBS_ERRCNT_9               regPCIE_PRBS_ERRCNT_9;
typedef union PCIE_PRBS_FREERUN                regPCIE_PRBS_FREERUN;
typedef union PCIE_PRBS_HI_BITCNT              regPCIE_PRBS_HI_BITCNT;
typedef union PCIE_PRBS_LO_BITCNT              regPCIE_PRBS_LO_BITCNT;
typedef union PCIE_PRBS_MISC__CI               regPCIE_PRBS_MISC__CI;
typedef union PCIE_PRBS_MISC__VI               regPCIE_PRBS_MISC__VI;
typedef union PCIE_PRBS_MISC__SI               regPCIE_PRBS_MISC__SI;
typedef union PCIE_PRBS_STATUS1                regPCIE_PRBS_STATUS1;
typedef union PCIE_PRBS_STATUS2                regPCIE_PRBS_STATUS2;
typedef union PCIE_PRBS_USER_PATTERN__CI__VI   regPCIE_PRBS_USER_PATTERN__CI__VI;
typedef union PCIE_PRBS_USER_PATTERN__SI       regPCIE_PRBS_USER_PATTERN__SI;
typedef union PCIE_PWR_BUDGET_CAP__CI__VI      regPCIE_PWR_BUDGET_CAP__CI__VI;
typedef union PCIE_PWR_BUDGET_DATA_SELECT__CI__VI regPCIE_PWR_BUDGET_DATA_SELECT__CI__VI;
typedef union PCIE_PWR_BUDGET_DATA__CI__VI     regPCIE_PWR_BUDGET_DATA__CI__VI;
typedef union PCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI regPCIE_PWR_BUDGET_ENH_CAP_LIST__CI__VI;
typedef union PCIE_P_BUF_STATUS__CI__VI        regPCIE_P_BUF_STATUS__CI__VI;
typedef union PCIE_P_BUF_STATUS__SI            regPCIE_P_BUF_STATUS__SI;
typedef union PCIE_P_CNTL__CI__VI              regPCIE_P_CNTL__CI__VI;
typedef union PCIE_P_CNTL__SI                  regPCIE_P_CNTL__SI;
typedef union PCIE_P_DECODER_STATUS__CI__VI    regPCIE_P_DECODER_STATUS__CI__VI;
typedef union PCIE_P_DECODER_STATUS__SI        regPCIE_P_DECODER_STATUS__SI;
typedef union PCIE_P_MISC_STATUS__CI__VI       regPCIE_P_MISC_STATUS__CI__VI;
typedef union PCIE_P_PORT_LANE_STATUS          regPCIE_P_PORT_LANE_STATUS;
typedef union PCIE_P_RCV_L0S_FTS_DET__CI__VI   regPCIE_P_RCV_L0S_FTS_DET__CI__VI;
typedef union PCIE_RESERVED                    regPCIE_RESERVED;
typedef union PCIE_RX_CNTL2__CI__VI            regPCIE_RX_CNTL2__CI__VI;
typedef union PCIE_RX_CNTL3__CI__VI            regPCIE_RX_CNTL3__CI__VI;
typedef union PCIE_RX_CNTL__CI__VI             regPCIE_RX_CNTL__CI__VI;
typedef union PCIE_RX_CNTL__SI                 regPCIE_RX_CNTL__SI;
typedef union PCIE_RX_CREDITS_ALLOCATED_CPL    regPCIE_RX_CREDITS_ALLOCATED_CPL;
typedef union PCIE_RX_CREDITS_ALLOCATED_NP     regPCIE_RX_CREDITS_ALLOCATED_NP;
typedef union PCIE_RX_CREDITS_ALLOCATED_P      regPCIE_RX_CREDITS_ALLOCATED_P;
typedef union PCIE_RX_EXPECTED_SEQNUM__CI__VI  regPCIE_RX_EXPECTED_SEQNUM__CI__VI;
typedef union PCIE_RX_LAST_TLP0                regPCIE_RX_LAST_TLP0;
typedef union PCIE_RX_LAST_TLP1                regPCIE_RX_LAST_TLP1;
typedef union PCIE_RX_LAST_TLP2                regPCIE_RX_LAST_TLP2;
typedef union PCIE_RX_LAST_TLP3                regPCIE_RX_LAST_TLP3;
typedef union PCIE_RX_NUM_NAK_GENERATED__CI__VI regPCIE_RX_NUM_NAK_GENERATED__CI__VI;
typedef union PCIE_RX_NUM_NAK__CI__VI          regPCIE_RX_NUM_NAK__CI__VI;
typedef union PCIE_RX_VENDOR_SPECIFIC          regPCIE_RX_VENDOR_SPECIFIC;
typedef union PCIE_SCRATCH                     regPCIE_SCRATCH;
typedef union PCIE_SECONDARY_ENH_CAP_LIST__CI__VI regPCIE_SECONDARY_ENH_CAP_LIST__CI__VI;
typedef union PCIE_STRAP_F0__CI                regPCIE_STRAP_F0__CI;
typedef union PCIE_STRAP_F0__VI                regPCIE_STRAP_F0__VI;
typedef union PCIE_STRAP_F1__CI__VI            regPCIE_STRAP_F1__CI__VI;
typedef union PCIE_STRAP_F2__CI__VI            regPCIE_STRAP_F2__CI__VI;
typedef union PCIE_STRAP_F3__CI__VI            regPCIE_STRAP_F3__CI__VI;
typedef union PCIE_STRAP_F4__CI__VI            regPCIE_STRAP_F4__CI__VI;
typedef union PCIE_STRAP_F5__CI__VI            regPCIE_STRAP_F5__CI__VI;
typedef union PCIE_STRAP_F6__CI__VI            regPCIE_STRAP_F6__CI__VI;
typedef union PCIE_STRAP_F7__CI__VI            regPCIE_STRAP_F7__CI__VI;
typedef union PCIE_STRAP_I2C_BD                regPCIE_STRAP_I2C_BD;
typedef union PCIE_STRAP_MISC2                 regPCIE_STRAP_MISC2;
typedef union PCIE_STRAP_MISC__CI__VI          regPCIE_STRAP_MISC__CI__VI;
typedef union PCIE_STRAP_MISC__SI              regPCIE_STRAP_MISC__SI;
typedef union PCIE_STRAP_PI                    regPCIE_STRAP_PI;
typedef union PCIE_TLP_PREFIX_LOG0__CI__VI     regPCIE_TLP_PREFIX_LOG0__CI__VI;
typedef union PCIE_TLP_PREFIX_LOG1__CI__VI     regPCIE_TLP_PREFIX_LOG1__CI__VI;
typedef union PCIE_TLP_PREFIX_LOG2__CI__VI     regPCIE_TLP_PREFIX_LOG2__CI__VI;
typedef union PCIE_TLP_PREFIX_LOG3__CI__VI     regPCIE_TLP_PREFIX_LOG3__CI__VI;
typedef union PCIE_TX_ACK_LATENCY_LIMIT__CI__VI regPCIE_TX_ACK_LATENCY_LIMIT__CI__VI;
typedef union PCIE_TX_ACK_LATENCY_LIMIT__SI    regPCIE_TX_ACK_LATENCY_LIMIT__SI;
typedef union PCIE_TX_CNTL__CI__VI             regPCIE_TX_CNTL__CI__VI;
typedef union PCIE_TX_CNTL__SI                 regPCIE_TX_CNTL__SI;
typedef union PCIE_TX_CREDITS_ADVT_CPL         regPCIE_TX_CREDITS_ADVT_CPL;
typedef union PCIE_TX_CREDITS_ADVT_NP          regPCIE_TX_CREDITS_ADVT_NP;
typedef union PCIE_TX_CREDITS_ADVT_P           regPCIE_TX_CREDITS_ADVT_P;
typedef union PCIE_TX_CREDITS_FCU_THRESHOLD__CI__VI regPCIE_TX_CREDITS_FCU_THRESHOLD__CI__VI;
typedef union PCIE_TX_CREDITS_INIT_CPL         regPCIE_TX_CREDITS_INIT_CPL;
typedef union PCIE_TX_CREDITS_INIT_NP          regPCIE_TX_CREDITS_INIT_NP;
typedef union PCIE_TX_CREDITS_INIT_P           regPCIE_TX_CREDITS_INIT_P;
typedef union PCIE_TX_CREDITS_STATUS           regPCIE_TX_CREDITS_STATUS;
typedef union PCIE_TX_F0_ATTR_CNTL__CI__VI     regPCIE_TX_F0_ATTR_CNTL__CI__VI;
typedef union PCIE_TX_F1_F2_ATTR_CNTL__CI__VI  regPCIE_TX_F1_F2_ATTR_CNTL__CI__VI;
typedef union PCIE_TX_LAST_TLP0                regPCIE_TX_LAST_TLP0;
typedef union PCIE_TX_LAST_TLP1                regPCIE_TX_LAST_TLP1;
typedef union PCIE_TX_LAST_TLP2                regPCIE_TX_LAST_TLP2;
typedef union PCIE_TX_LAST_TLP3                regPCIE_TX_LAST_TLP3;
typedef union PCIE_TX_REPLAY                   regPCIE_TX_REPLAY;
typedef union PCIE_TX_REQUESTER_ID             regPCIE_TX_REQUESTER_ID;
typedef union PCIE_TX_REQUEST_NUM_CNTL         regPCIE_TX_REQUEST_NUM_CNTL;
typedef union PCIE_TX_SEQ                      regPCIE_TX_SEQ;
typedef union PCIE_TX_VENDOR_SPECIFIC          regPCIE_TX_VENDOR_SPECIFIC;
typedef union PCIE_UNCORR_ERR_MASK             regPCIE_UNCORR_ERR_MASK;
typedef union PCIE_UNCORR_ERR_SEVERITY         regPCIE_UNCORR_ERR_SEVERITY;
typedef union PCIE_UNCORR_ERR_STATUS           regPCIE_UNCORR_ERR_STATUS;
typedef union PCIE_VC0_RESOURCE_CAP            regPCIE_VC0_RESOURCE_CAP;
typedef union PCIE_VC0_RESOURCE_CNTL           regPCIE_VC0_RESOURCE_CNTL;
typedef union PCIE_VC0_RESOURCE_STATUS         regPCIE_VC0_RESOURCE_STATUS;
typedef union PCIE_VC1_RESOURCE_CAP            regPCIE_VC1_RESOURCE_CAP;
typedef union PCIE_VC1_RESOURCE_CNTL           regPCIE_VC1_RESOURCE_CNTL;
typedef union PCIE_VC1_RESOURCE_STATUS         regPCIE_VC1_RESOURCE_STATUS;
typedef union PCIE_VC_ENH_CAP_LIST             regPCIE_VC_ENH_CAP_LIST;
typedef union PCIE_VENDOR_SPECIFIC1            regPCIE_VENDOR_SPECIFIC1;
typedef union PCIE_VENDOR_SPECIFIC2            regPCIE_VENDOR_SPECIFIC2;
typedef union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST regPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST;
typedef union PCIE_VENDOR_SPECIFIC_HDR         regPCIE_VENDOR_SPECIFIC_HDR;
typedef union PCIE_WPR_CNTL                    regPCIE_WPR_CNTL;
typedef union PEER0_FB_OFFSET_HI__CI__VI       regPEER0_FB_OFFSET_HI__CI__VI;
typedef union PEER0_FB_OFFSET_LO__CI__VI       regPEER0_FB_OFFSET_LO__CI__VI;
typedef union PEER1_FB_OFFSET_HI__CI__VI       regPEER1_FB_OFFSET_HI__CI__VI;
typedef union PEER1_FB_OFFSET_LO__CI__VI       regPEER1_FB_OFFSET_LO__CI__VI;
typedef union PEER2_FB_OFFSET_HI__CI__VI       regPEER2_FB_OFFSET_HI__CI__VI;
typedef union PEER2_FB_OFFSET_LO__CI__VI       regPEER2_FB_OFFSET_LO__CI__VI;
typedef union PEER3_FB_OFFSET_HI__CI__VI       regPEER3_FB_OFFSET_HI__CI__VI;
typedef union PEER3_FB_OFFSET_LO__CI__VI       regPEER3_FB_OFFSET_LO__CI__VI;
typedef union PEER_REG_RANGE0                  regPEER_REG_RANGE0;
typedef union PEER_REG_RANGE1                  regPEER_REG_RANGE1;
typedef union PHY_AUX_CNTL__SI__VI             regPHY_AUX_CNTL__SI__VI;
typedef union PIPE0_ARBITRATION_CONTROL3__SI__VI regPIPE0_ARBITRATION_CONTROL3__SI__VI;
typedef union PIPE1_ARBITRATION_CONTROL3__SI__VI regPIPE1_ARBITRATION_CONTROL3__SI__VI;
typedef union PIPE2_ARBITRATION_CONTROL3__SI__VI regPIPE2_ARBITRATION_CONTROL3__SI__VI;
typedef union PIPE3_ARBITRATION_CONTROL3__SI__VI regPIPE3_ARBITRATION_CONTROL3__SI__VI;
typedef union PIPE4_ARBITRATION_CONTROL3__SI__VI regPIPE4_ARBITRATION_CONTROL3__SI__VI;
typedef union PIPE5_ARBITRATION_CONTROL3__SI__VI regPIPE5_ARBITRATION_CONTROL3__SI__VI;
typedef union PIXCLK1_RESYNC_CNTL__SI__VI      regPIXCLK1_RESYNC_CNTL__SI__VI;
typedef union PIXCLK2_RESYNC_CNTL__SI__VI      regPIXCLK2_RESYNC_CNTL__SI__VI;
typedef union PLL_TEST_CNTL                    regPLL_TEST_CNTL;
typedef union PMI_CAP                          regPMI_CAP;
typedef union PMI_CAP_LIST                     regPMI_CAP_LIST;
typedef union PMI_STATUS_CNTL                  regPMI_STATUS_CNTL;
typedef union PROG_INTERFACE                   regPROG_INTERFACE;
typedef union RAS_BCI_SIGNATURE0               regRAS_BCI_SIGNATURE0;
typedef union RAS_BCI_SIGNATURE1               regRAS_BCI_SIGNATURE1;
typedef union RAS_CB_SIGNATURE0                regRAS_CB_SIGNATURE0;
typedef union RAS_DB_SIGNATURE0                regRAS_DB_SIGNATURE0;
typedef union RAS_IA_SIGNATURE0                regRAS_IA_SIGNATURE0;
typedef union RAS_IA_SIGNATURE1                regRAS_IA_SIGNATURE1;
typedef union RAS_PA_SIGNATURE0                regRAS_PA_SIGNATURE0;
typedef union RAS_SC_SIGNATURE0                regRAS_SC_SIGNATURE0;
typedef union RAS_SC_SIGNATURE1                regRAS_SC_SIGNATURE1;
typedef union RAS_SC_SIGNATURE2                regRAS_SC_SIGNATURE2;
typedef union RAS_SC_SIGNATURE3                regRAS_SC_SIGNATURE3;
typedef union RAS_SC_SIGNATURE4                regRAS_SC_SIGNATURE4;
typedef union RAS_SC_SIGNATURE5                regRAS_SC_SIGNATURE5;
typedef union RAS_SC_SIGNATURE6                regRAS_SC_SIGNATURE6;
typedef union RAS_SC_SIGNATURE7                regRAS_SC_SIGNATURE7;
typedef union RAS_SIGNATURE_CONTROL            regRAS_SIGNATURE_CONTROL;
typedef union RAS_SIGNATURE_MASK               regRAS_SIGNATURE_MASK;
typedef union RAS_SPI_SIGNATURE0               regRAS_SPI_SIGNATURE0;
typedef union RAS_SPI_SIGNATURE1               regRAS_SPI_SIGNATURE1;
typedef union RAS_SQ_SIGNATURE0                regRAS_SQ_SIGNATURE0;
typedef union RAS_SX_SIGNATURE0                regRAS_SX_SIGNATURE0;
typedef union RAS_SX_SIGNATURE1                regRAS_SX_SIGNATURE1;
typedef union RAS_SX_SIGNATURE2                regRAS_SX_SIGNATURE2;
typedef union RAS_SX_SIGNATURE3                regRAS_SX_SIGNATURE3;
typedef union RAS_TA_SIGNATURE0                regRAS_TA_SIGNATURE0;
typedef union RAS_TD_SIGNATURE0                regRAS_TD_SIGNATURE0;
typedef union RAS_VGT_SIGNATURE0               regRAS_VGT_SIGNATURE0;
typedef union RCU_MISC_CTRL__CI__VI            regRCU_MISC_CTRL__CI__VI;
typedef union RCU_MISC_CTRL__SI                regRCU_MISC_CTRL__SI;
typedef union RCU_UC_EVENTS__CI__VI            regRCU_UC_EVENTS__CI__VI;
typedef union RCU_UC_EVENTS__SI                regRCU_UC_EVENTS__SI;
typedef union RESPONSE_INTERRUPT_COUNT__SI__VI regRESPONSE_INTERRUPT_COUNT__SI__VI;
typedef union REVISION_ID                      regREVISION_ID;
typedef union RINGOSC_MASK                     regRINGOSC_MASK;
typedef union RIRB_CONTROL__SI__VI             regRIRB_CONTROL__SI__VI;
typedef union RIRB_LOWER_BASE_ADDRESS__SI__VI  regRIRB_LOWER_BASE_ADDRESS__SI__VI;
typedef union RIRB_SIZE__SI__VI                regRIRB_SIZE__SI__VI;
typedef union RIRB_STATUS__SI__VI              regRIRB_STATUS__SI__VI;
typedef union RIRB_UPPER_BASE_ADDRESS__SI__VI  regRIRB_UPPER_BASE_ADDRESS__SI__VI;
typedef union RIRB_WRITE_POINTER__SI__VI       regRIRB_WRITE_POINTER__SI__VI;
typedef union RLC_AUTO_PG_CTRL                 regRLC_AUTO_PG_CTRL;
typedef union RLC_CAPTURE_GPU_CLOCK_COUNT      regRLC_CAPTURE_GPU_CLOCK_COUNT;
typedef union RLC_CGCG_CGLS_CTRL__CI           regRLC_CGCG_CGLS_CTRL__CI;
typedef union RLC_CGCG_CGLS_CTRL__VI           regRLC_CGCG_CGLS_CTRL__VI;
typedef union RLC_CGCG_CGLS_CTRL__SI           regRLC_CGCG_CGLS_CTRL__SI;
typedef union RLC_CGCG_RAMP_CTRL               regRLC_CGCG_RAMP_CTRL;
typedef union RLC_CGTT_MGCG_OVERRIDE           regRLC_CGTT_MGCG_OVERRIDE;
typedef union RLC_CNTL                         regRLC_CNTL;
typedef union RLC_CU_STATUS__CI__VI            regRLC_CU_STATUS__CI__VI;
typedef union RLC_CU_STATUS__SI                regRLC_CU_STATUS__SI;
typedef union RLC_DEBUG                        regRLC_DEBUG;
typedef union RLC_DEBUG_SELECT                 regRLC_DEBUG_SELECT;
typedef union RLC_DRIVER_CPDMA_STATUS          regRLC_DRIVER_CPDMA_STATUS;
typedef union RLC_DYN_PG_REQUEST__CI__VI       regRLC_DYN_PG_REQUEST__CI__VI;
typedef union RLC_DYN_PG_REQUEST__SI           regRLC_DYN_PG_REQUEST__SI;
typedef union RLC_DYN_PG_STATUS__CI__VI        regRLC_DYN_PG_STATUS__CI__VI;
typedef union RLC_DYN_PG_STATUS__SI            regRLC_DYN_PG_STATUS__SI;
typedef union RLC_GPM_CU_PD_TIMEOUT__CI__VI    regRLC_GPM_CU_PD_TIMEOUT__CI__VI;
typedef union RLC_GPM_DEBUG_SELECT__CI__VI     regRLC_GPM_DEBUG_SELECT__CI__VI;
typedef union RLC_GPM_DEBUG__CI__VI            regRLC_GPM_DEBUG__CI__VI;
typedef union RLC_GPM_GENERAL_0__CI__VI        regRLC_GPM_GENERAL_0__CI__VI;
typedef union RLC_GPM_GENERAL_1__CI__VI        regRLC_GPM_GENERAL_1__CI__VI;
typedef union RLC_GPM_GENERAL_2__CI__VI        regRLC_GPM_GENERAL_2__CI__VI;
typedef union RLC_GPM_GENERAL_3__CI__VI        regRLC_GPM_GENERAL_3__CI__VI;
typedef union RLC_GPM_GENERAL_4__CI__VI        regRLC_GPM_GENERAL_4__CI__VI;
typedef union RLC_GPM_GENERAL_5__CI__VI        regRLC_GPM_GENERAL_5__CI__VI;
typedef union RLC_GPM_GENERAL_6__CI__VI        regRLC_GPM_GENERAL_6__CI__VI;
typedef union RLC_GPM_GENERAL_7__CI__VI        regRLC_GPM_GENERAL_7__CI__VI;
typedef union RLC_GPM_LOG_ADDR__CI__VI         regRLC_GPM_LOG_ADDR__CI__VI;
typedef union RLC_GPM_LOG_CONT__CI__VI         regRLC_GPM_LOG_CONT__CI__VI;
typedef union RLC_GPM_LOG_SIZE__CI__VI         regRLC_GPM_LOG_SIZE__CI__VI;
typedef union RLC_GPM_PERF_COUNT_0__CI__VI     regRLC_GPM_PERF_COUNT_0__CI__VI;
typedef union RLC_GPM_PERF_COUNT_1__CI__VI     regRLC_GPM_PERF_COUNT_1__CI__VI;
typedef union RLC_GPM_SCRATCH_ADDR__CI__VI     regRLC_GPM_SCRATCH_ADDR__CI__VI;
typedef union RLC_GPM_SCRATCH_DATA__CI__VI     regRLC_GPM_SCRATCH_DATA__CI__VI;
typedef union RLC_GPM_STAT__CI__VI             regRLC_GPM_STAT__CI__VI;
typedef union RLC_GPM_THREAD_ENABLE__CI__VI    regRLC_GPM_THREAD_ENABLE__CI__VI;
typedef union RLC_GPM_THREAD_PRIORITY__CI__VI  regRLC_GPM_THREAD_PRIORITY__CI__VI;
typedef union RLC_GPM_UCODE_ADDR__CI__VI       regRLC_GPM_UCODE_ADDR__CI__VI;
typedef union RLC_GPM_UCODE_DATA__CI__VI       regRLC_GPM_UCODE_DATA__CI__VI;
typedef union RLC_GPM_VMID_THREAD0__CI__VI     regRLC_GPM_VMID_THREAD0__CI__VI;
typedef union RLC_GPM_VMID_THREAD1__CI__VI     regRLC_GPM_VMID_THREAD1__CI__VI;
typedef union RLC_GPR_REG1__CI__VI             regRLC_GPR_REG1__CI__VI;
typedef union RLC_GPR_REG2__CI__VI             regRLC_GPR_REG2__CI__VI;
typedef union RLC_GPU_CLOCK_32                 regRLC_GPU_CLOCK_32;
typedef union RLC_GPU_CLOCK_32_RES_SEL         regRLC_GPU_CLOCK_32_RES_SEL;
typedef union RLC_GPU_CLOCK_COUNT_LSB          regRLC_GPU_CLOCK_COUNT_LSB;
typedef union RLC_GPU_CLOCK_COUNT_MSB          regRLC_GPU_CLOCK_COUNT_MSB;
typedef union RLC_JUMP_TABLE_RESTORE__CI__VI   regRLC_JUMP_TABLE_RESTORE__CI__VI;
typedef union RLC_LB_ALWAYS_ACTIVE_CU_MASK__CI__VI regRLC_LB_ALWAYS_ACTIVE_CU_MASK__CI__VI;
typedef union RLC_LB_ALWAYS_ACTIVE_CU_MASK__SI regRLC_LB_ALWAYS_ACTIVE_CU_MASK__SI;
typedef union RLC_LB_CNTL                      regRLC_LB_CNTL;
typedef union RLC_LB_CNTR_INIT                 regRLC_LB_CNTR_INIT;
typedef union RLC_LB_CNTR_MAX                  regRLC_LB_CNTR_MAX;
typedef union RLC_LB_INIT_CU_MASK__CI__VI      regRLC_LB_INIT_CU_MASK__CI__VI;
typedef union RLC_LB_INIT_CU_MASK__SI          regRLC_LB_INIT_CU_MASK__SI;
typedef union RLC_LB_PARAMS                    regRLC_LB_PARAMS;
typedef union RLC_LOAD_BALANCE_CNTR            regRLC_LOAD_BALANCE_CNTR;
typedef union RLC_MAX_PG_CU                    regRLC_MAX_PG_CU;
typedef union RLC_MC_CNTL                      regRLC_MC_CNTL;
typedef union RLC_MEM_SLP_CNTL                 regRLC_MEM_SLP_CNTL;
typedef union RLC_PERFCOUNTER0_HI              regRLC_PERFCOUNTER0_HI;
typedef union RLC_PERFCOUNTER0_LO              regRLC_PERFCOUNTER0_LO;
typedef union RLC_PERFCOUNTER0_SELECT          regRLC_PERFCOUNTER0_SELECT;
typedef union RLC_PERFCOUNTER1_HI              regRLC_PERFCOUNTER1_HI;
typedef union RLC_PERFCOUNTER1_LO              regRLC_PERFCOUNTER1_LO;
typedef union RLC_PERFCOUNTER1_SELECT          regRLC_PERFCOUNTER1_SELECT;
typedef union RLC_PERFMON_CNTL                 regRLC_PERFMON_CNTL;
typedef union RLC_PG_ALWAYS_ON_CU_MASK__CI__VI regRLC_PG_ALWAYS_ON_CU_MASK__CI__VI;
typedef union RLC_PG_ALWAYS_ON_CU_MASK__SI     regRLC_PG_ALWAYS_ON_CU_MASK__SI;
typedef union RLC_PG_CNTL                      regRLC_PG_CNTL;
typedef union RLC_PG_DELAY_2__CI__VI           regRLC_PG_DELAY_2__CI__VI;
typedef union RLC_PG_DELAY__CI__VI             regRLC_PG_DELAY__CI__VI;
typedef union RLC_SAFE_MODE__CI                regRLC_SAFE_MODE__CI;
typedef union RLC_SAFE_MODE__VI                regRLC_SAFE_MODE__VI;
typedef union RLC_SAVE_AND_RESTORE_BASE        regRLC_SAVE_AND_RESTORE_BASE;
typedef union RLC_SERDES_CU_MASTER_BUSY__CI__VI regRLC_SERDES_CU_MASTER_BUSY__CI__VI;
typedef union RLC_SERDES_NONCU_MASTER_BUSY__CI regRLC_SERDES_NONCU_MASTER_BUSY__CI;
typedef union RLC_SERDES_NONCU_MASTER_BUSY__VI regRLC_SERDES_NONCU_MASTER_BUSY__VI;
typedef union RLC_SERDES_RD_DATA_0             regRLC_SERDES_RD_DATA_0;
typedef union RLC_SERDES_RD_DATA_1             regRLC_SERDES_RD_DATA_1;
typedef union RLC_SERDES_RD_DATA_2             regRLC_SERDES_RD_DATA_2;
typedef union RLC_SERDES_RD_MASTER_INDEX__CI   regRLC_SERDES_RD_MASTER_INDEX__CI;
typedef union RLC_SERDES_RD_MASTER_INDEX__VI   regRLC_SERDES_RD_MASTER_INDEX__VI;
typedef union RLC_SERDES_RD_MASTER_INDEX__SI   regRLC_SERDES_RD_MASTER_INDEX__SI;
typedef union RLC_SERDES_WR_CTRL__CI           regRLC_SERDES_WR_CTRL__CI;
typedef union RLC_SERDES_WR_CTRL__VI           regRLC_SERDES_WR_CTRL__VI;
typedef union RLC_SERDES_WR_CTRL__SI           regRLC_SERDES_WR_CTRL__SI;
typedef union RLC_SERDES_WR_CU_MASTER_MASK__CI__VI regRLC_SERDES_WR_CU_MASTER_MASK__CI__VI;
typedef union RLC_SERDES_WR_DATA               regRLC_SERDES_WR_DATA;
typedef union RLC_SERDES_WR_NONCU_MASTER_MASK__CI regRLC_SERDES_WR_NONCU_MASTER_MASK__CI;
typedef union RLC_SERDES_WR_NONCU_MASTER_MASK__VI regRLC_SERDES_WR_NONCU_MASTER_MASK__VI;
typedef union RLC_SMU_GRBM_REG_SAVE_CTRL       regRLC_SMU_GRBM_REG_SAVE_CTRL;
typedef union RLC_SMU_PG_CTRL                  regRLC_SMU_PG_CTRL;
typedef union RLC_SMU_PG_WAKE_UP_CTRL          regRLC_SMU_PG_WAKE_UP_CTRL;
typedef union RLC_SOFT_RESET_GPU               regRLC_SOFT_RESET_GPU;
typedef union RLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CB_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_DB_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_DEBUG_SELECT__CI__VI     regRLC_SPM_DEBUG_SELECT__CI__VI;
typedef union RLC_SPM_DEBUG__CI__VI            regRLC_SPM_DEBUG__CI__VI;
typedef union RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI regRLC_SPM_GLOBAL_MUXSEL_ADDR__CI__VI;
typedef union RLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI regRLC_SPM_GLOBAL_MUXSEL_DATA__CI__VI;
typedef union RLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_IA_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_INT_CNTL__CI__VI         regRLC_SPM_INT_CNTL__CI__VI;
typedef union RLC_SPM_INT_STATUS__CI__VI       regRLC_SPM_INT_STATUS__CI__VI;
typedef union RLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_PA_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_PERFMON_CNTL__CI__VI     regRLC_SPM_PERFMON_CNTL__CI__VI;
typedef union RLC_SPM_PERFMON_RING_BASE_HI__CI__VI regRLC_SPM_PERFMON_RING_BASE_HI__CI__VI;
typedef union RLC_SPM_PERFMON_RING_BASE_LO__CI__VI regRLC_SPM_PERFMON_RING_BASE_LO__CI__VI;
typedef union RLC_SPM_PERFMON_RING_SIZE__CI__VI regRLC_SPM_PERFMON_RING_SIZE__CI__VI;
typedef union RLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI regRLC_SPM_PERFMON_SEGMENT_SIZE__CI__VI;
typedef union RLC_SPM_RING_RDPTR__CI__VI       regRLC_SPM_RING_RDPTR__CI__VI;
typedef union RLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SC_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_SEGMENT_THRESHOLD__CI__VI regRLC_SPM_SEGMENT_THRESHOLD__CI__VI;
typedef union RLC_SPM_SE_MUXSEL_ADDR__CI__VI   regRLC_SPM_SE_MUXSEL_ADDR__CI__VI;
typedef union RLC_SPM_SE_MUXSEL_DATA__CI__VI   regRLC_SPM_SE_MUXSEL_DATA__CI__VI;
typedef union RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_SX_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TA_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI regRLC_SPM_TCS_PERFMON_SAMPLE_DELAY__CI;
typedef union RLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_TD_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY__CI__VI;
typedef union RLC_SPM_VMID__CI__VI             regRLC_SPM_VMID__CI__VI;
typedef union RLC_STATIC_PG_STATUS__CI__VI     regRLC_STATIC_PG_STATUS__CI__VI;
typedef union RLC_STAT__CI__VI                 regRLC_STAT__CI__VI;
typedef union RLC_STAT__SI                     regRLC_STAT__SI;
typedef union RLC_THREAD1_DELAY                regRLC_THREAD1_DELAY;
typedef union RLC_UCODE_CNTL                   regRLC_UCODE_CNTL;
typedef union ROM_BASE_ADDR                    regROM_BASE_ADDR;
typedef union ROM_CNTL                         regROM_CNTL;
typedef union ROM_DATA                         regROM_DATA;
typedef union ROM_INDEX                        regROM_INDEX;
typedef union ROM_SMC_IND_DATA__CI__VI         regROM_SMC_IND_DATA__CI__VI;
typedef union ROM_SMC_IND_INDEX__CI__VI        regROM_SMC_IND_INDEX__CI__VI;
typedef union ROM_START                        regROM_START;
typedef union ROM_STATUS                       regROM_STATUS;
typedef union ROM_SW_CNTL                      regROM_SW_CNTL;
typedef union ROM_SW_COMMAND                   regROM_SW_COMMAND;
typedef union ROM_SW_DATA_1                    regROM_SW_DATA_1;
typedef union ROM_SW_DATA_10                   regROM_SW_DATA_10;
typedef union ROM_SW_DATA_11                   regROM_SW_DATA_11;
typedef union ROM_SW_DATA_12                   regROM_SW_DATA_12;
typedef union ROM_SW_DATA_13                   regROM_SW_DATA_13;
typedef union ROM_SW_DATA_14                   regROM_SW_DATA_14;
typedef union ROM_SW_DATA_15                   regROM_SW_DATA_15;
typedef union ROM_SW_DATA_16                   regROM_SW_DATA_16;
typedef union ROM_SW_DATA_17                   regROM_SW_DATA_17;
typedef union ROM_SW_DATA_18                   regROM_SW_DATA_18;
typedef union ROM_SW_DATA_19                   regROM_SW_DATA_19;
typedef union ROM_SW_DATA_2                    regROM_SW_DATA_2;
typedef union ROM_SW_DATA_20                   regROM_SW_DATA_20;
typedef union ROM_SW_DATA_21                   regROM_SW_DATA_21;
typedef union ROM_SW_DATA_22                   regROM_SW_DATA_22;
typedef union ROM_SW_DATA_23                   regROM_SW_DATA_23;
typedef union ROM_SW_DATA_24                   regROM_SW_DATA_24;
typedef union ROM_SW_DATA_25                   regROM_SW_DATA_25;
typedef union ROM_SW_DATA_26                   regROM_SW_DATA_26;
typedef union ROM_SW_DATA_27                   regROM_SW_DATA_27;
typedef union ROM_SW_DATA_28                   regROM_SW_DATA_28;
typedef union ROM_SW_DATA_29                   regROM_SW_DATA_29;
typedef union ROM_SW_DATA_3                    regROM_SW_DATA_3;
typedef union ROM_SW_DATA_30                   regROM_SW_DATA_30;
typedef union ROM_SW_DATA_31                   regROM_SW_DATA_31;
typedef union ROM_SW_DATA_32                   regROM_SW_DATA_32;
typedef union ROM_SW_DATA_33                   regROM_SW_DATA_33;
typedef union ROM_SW_DATA_34                   regROM_SW_DATA_34;
typedef union ROM_SW_DATA_35                   regROM_SW_DATA_35;
typedef union ROM_SW_DATA_36                   regROM_SW_DATA_36;
typedef union ROM_SW_DATA_37                   regROM_SW_DATA_37;
typedef union ROM_SW_DATA_38                   regROM_SW_DATA_38;
typedef union ROM_SW_DATA_39                   regROM_SW_DATA_39;
typedef union ROM_SW_DATA_4                    regROM_SW_DATA_4;
typedef union ROM_SW_DATA_40                   regROM_SW_DATA_40;
typedef union ROM_SW_DATA_41                   regROM_SW_DATA_41;
typedef union ROM_SW_DATA_42                   regROM_SW_DATA_42;
typedef union ROM_SW_DATA_43                   regROM_SW_DATA_43;
typedef union ROM_SW_DATA_44                   regROM_SW_DATA_44;
typedef union ROM_SW_DATA_45                   regROM_SW_DATA_45;
typedef union ROM_SW_DATA_46                   regROM_SW_DATA_46;
typedef union ROM_SW_DATA_47                   regROM_SW_DATA_47;
typedef union ROM_SW_DATA_48                   regROM_SW_DATA_48;
typedef union ROM_SW_DATA_49                   regROM_SW_DATA_49;
typedef union ROM_SW_DATA_5                    regROM_SW_DATA_5;
typedef union ROM_SW_DATA_50                   regROM_SW_DATA_50;
typedef union ROM_SW_DATA_51                   regROM_SW_DATA_51;
typedef union ROM_SW_DATA_52                   regROM_SW_DATA_52;
typedef union ROM_SW_DATA_53                   regROM_SW_DATA_53;
typedef union ROM_SW_DATA_54                   regROM_SW_DATA_54;
typedef union ROM_SW_DATA_55                   regROM_SW_DATA_55;
typedef union ROM_SW_DATA_56                   regROM_SW_DATA_56;
typedef union ROM_SW_DATA_57                   regROM_SW_DATA_57;
typedef union ROM_SW_DATA_58                   regROM_SW_DATA_58;
typedef union ROM_SW_DATA_59                   regROM_SW_DATA_59;
typedef union ROM_SW_DATA_6                    regROM_SW_DATA_6;
typedef union ROM_SW_DATA_60                   regROM_SW_DATA_60;
typedef union ROM_SW_DATA_61                   regROM_SW_DATA_61;
typedef union ROM_SW_DATA_62                   regROM_SW_DATA_62;
typedef union ROM_SW_DATA_63                   regROM_SW_DATA_63;
typedef union ROM_SW_DATA_64                   regROM_SW_DATA_64;
typedef union ROM_SW_DATA_7                    regROM_SW_DATA_7;
typedef union ROM_SW_DATA_8                    regROM_SW_DATA_8;
typedef union ROM_SW_DATA_9                    regROM_SW_DATA_9;
typedef union ROM_SW_STATUS                    regROM_SW_STATUS;
typedef union SCLK_CGTT_BLK_CTRL_REG__SI__VI   regSCLK_CGTT_BLK_CTRL_REG__SI__VI;
typedef union SCLK_DEEP_SLEEP_CNTL2__CI        regSCLK_DEEP_SLEEP_CNTL2__CI;
typedef union SCLK_DEEP_SLEEP_CNTL2__VI        regSCLK_DEEP_SLEEP_CNTL2__VI;
typedef union SCLK_DEEP_SLEEP_CNTL3__CI__VI    regSCLK_DEEP_SLEEP_CNTL3__CI__VI;
typedef union SCLK_DEEP_SLEEP_CNTL__CI__VI     regSCLK_DEEP_SLEEP_CNTL__CI__VI;
typedef union SCLK_DEEP_SLEEP_MISC_CNTL__CI__VI regSCLK_DEEP_SLEEP_MISC_CNTL__CI__VI;
typedef union SCLK_MIN_DIV__CI__VI             regSCLK_MIN_DIV__CI__VI;
typedef union SCLK_PWRMGT_CNTL__CI__VI         regSCLK_PWRMGT_CNTL__CI__VI;
typedef union SCLK_PWRMGT_CNTL__SI             regSCLK_PWRMGT_CNTL__SI;
typedef union SCL_ALU_CONTROL__SI__VI          regSCL_ALU_CONTROL__SI__VI;
typedef union SCL_AUTOMATIC_MODE_CONTROL__SI   regSCL_AUTOMATIC_MODE_CONTROL__SI;
typedef union SCL_AUTOMATIC_MODE_CONTROL__VI   regSCL_AUTOMATIC_MODE_CONTROL__VI;
typedef union SCL_BYPASS_CONTROL__SI__VI       regSCL_BYPASS_CONTROL__SI__VI;
typedef union SCL_COEF_RAM_CONFLICT_STATUS__SI__VI regSCL_COEF_RAM_CONFLICT_STATUS__SI__VI;
typedef union SCL_COEF_RAM_SELECT__SI__VI      regSCL_COEF_RAM_SELECT__SI__VI;
typedef union SCL_COEF_RAM_TAP_DATA__SI__VI    regSCL_COEF_RAM_TAP_DATA__SI__VI;
typedef union SCL_CONTROL__SI                  regSCL_CONTROL__SI;
typedef union SCL_CONTROL__VI                  regSCL_CONTROL__VI;
typedef union SCL_DEBUG__SI__VI                regSCL_DEBUG__SI__VI;
typedef union SCL_F_SHARP_CONTROL__SI__VI      regSCL_F_SHARP_CONTROL__SI__VI;
typedef union SCL_HORZ_FILTER_CONTROL__SI      regSCL_HORZ_FILTER_CONTROL__SI;
typedef union SCL_HORZ_FILTER_CONTROL__VI      regSCL_HORZ_FILTER_CONTROL__VI;
typedef union SCL_HORZ_FILTER_SCALE_RATIO__SI__VI regSCL_HORZ_FILTER_SCALE_RATIO__SI__VI;
typedef union SCL_MANUAL_REPLICATE_CONTROL__SI__VI regSCL_MANUAL_REPLICATE_CONTROL__SI__VI;
typedef union SCL_MODE_CHANGE_DET1__SI__VI     regSCL_MODE_CHANGE_DET1__SI__VI;
typedef union SCL_MODE_CHANGE_DET2__SI__VI     regSCL_MODE_CHANGE_DET2__SI__VI;
typedef union SCL_MODE_CHANGE_DET3__SI__VI     regSCL_MODE_CHANGE_DET3__SI__VI;
typedef union SCL_MODE_CHANGE_MASK__SI__VI     regSCL_MODE_CHANGE_MASK__SI__VI;
typedef union SCL_TAP_CONTROL__SI              regSCL_TAP_CONTROL__SI;
typedef union SCL_TAP_CONTROL__VI              regSCL_TAP_CONTROL__VI;
typedef union SCL_TEST_DEBUG_DATA__SI__VI      regSCL_TEST_DEBUG_DATA__SI__VI;
typedef union SCL_TEST_DEBUG_INDEX__SI__VI     regSCL_TEST_DEBUG_INDEX__SI__VI;
typedef union SCL_UPDATE__SI__VI               regSCL_UPDATE__SI__VI;
typedef union SCL_VERT_FILTER_CONTROL__SI      regSCL_VERT_FILTER_CONTROL__SI;
typedef union SCL_VERT_FILTER_CONTROL__VI      regSCL_VERT_FILTER_CONTROL__VI;
typedef union SCL_VERT_FILTER_INIT_BOT__SI     regSCL_VERT_FILTER_INIT_BOT__SI;
typedef union SCL_VERT_FILTER_INIT_BOT__VI     regSCL_VERT_FILTER_INIT_BOT__VI;
typedef union SCL_VERT_FILTER_INIT__SI         regSCL_VERT_FILTER_INIT__SI;
typedef union SCL_VERT_FILTER_INIT__VI         regSCL_VERT_FILTER_INIT__VI;
typedef union SCL_VERT_FILTER_SCALE_RATIO__SI__VI regSCL_VERT_FILTER_SCALE_RATIO__SI__VI;
typedef union SCRATCH_ADDR__CI__VI             regSCRATCH_ADDR__CI__VI;
typedef union SCRATCH_ADDR__SI                 regSCRATCH_ADDR__SI;
typedef union SCRATCH_REG0                     regSCRATCH_REG0;
typedef union SCRATCH_REG1                     regSCRATCH_REG1;
typedef union SCRATCH_REG2                     regSCRATCH_REG2;
typedef union SCRATCH_REG3                     regSCRATCH_REG3;
typedef union SCRATCH_REG4                     regSCRATCH_REG4;
typedef union SCRATCH_REG5                     regSCRATCH_REG5;
typedef union SCRATCH_REG6                     regSCRATCH_REG6;
typedef union SCRATCH_REG7                     regSCRATCH_REG7;
typedef union SCRATCH_UMSK__CI__VI             regSCRATCH_UMSK__CI__VI;
typedef union SCRATCH_UMSK__SI                 regSCRATCH_UMSK__SI;
typedef union SDMA0_CHICKEN_BITS__CI__VI       regSDMA0_CHICKEN_BITS__CI__VI;
typedef union SDMA0_CLK_CTRL__CI__VI           regSDMA0_CLK_CTRL__CI__VI;
typedef union SDMA0_CNTL__CI                   regSDMA0_CNTL__CI;
typedef union SDMA0_CNTL__VI                   regSDMA0_CNTL__VI;
typedef union SDMA0_F32_CNTL__CI__VI           regSDMA0_F32_CNTL__CI__VI;
typedef union SDMA0_FREEZE__CI__VI             regSDMA0_FREEZE__CI__VI;
typedef union SDMA0_GFX_APE1_CNTL__CI__VI      regSDMA0_GFX_APE1_CNTL__CI__VI;
typedef union SDMA0_GFX_CONTEXT_CNTL__CI__VI   regSDMA0_GFX_CONTEXT_CNTL__CI__VI;
typedef union SDMA0_GFX_CONTEXT_STATUS__CI__VI regSDMA0_GFX_CONTEXT_STATUS__CI__VI;
typedef union SDMA0_GFX_IB_BASE_HI__CI__VI     regSDMA0_GFX_IB_BASE_HI__CI__VI;
typedef union SDMA0_GFX_IB_BASE_LO__CI__VI     regSDMA0_GFX_IB_BASE_LO__CI__VI;
typedef union SDMA0_GFX_IB_CNTL__CI__VI        regSDMA0_GFX_IB_CNTL__CI__VI;
typedef union SDMA0_GFX_IB_OFFSET__CI__VI      regSDMA0_GFX_IB_OFFSET__CI__VI;
typedef union SDMA0_GFX_IB_RPTR__CI__VI        regSDMA0_GFX_IB_RPTR__CI__VI;
typedef union SDMA0_GFX_IB_SIZE__CI__VI        regSDMA0_GFX_IB_SIZE__CI__VI;
typedef union SDMA0_GFX_RB_BASE_HI__CI__VI     regSDMA0_GFX_RB_BASE_HI__CI__VI;
typedef union SDMA0_GFX_RB_BASE__CI__VI        regSDMA0_GFX_RB_BASE__CI__VI;
typedef union SDMA0_GFX_RB_CNTL__CI__VI        regSDMA0_GFX_RB_CNTL__CI__VI;
typedef union SDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI regSDMA0_GFX_RB_RPTR_ADDR_HI__CI__VI;
typedef union SDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI regSDMA0_GFX_RB_RPTR_ADDR_LO__CI__VI;
typedef union SDMA0_GFX_RB_RPTR__CI__VI        regSDMA0_GFX_RB_RPTR__CI__VI;
typedef union SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI;
typedef union SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI;
typedef union SDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI regSDMA0_GFX_RB_WPTR_POLL_CNTL__CI__VI;
typedef union SDMA0_GFX_RB_WPTR__CI__VI        regSDMA0_GFX_RB_WPTR__CI__VI;
typedef union SDMA0_GFX_SKIP_CNTL__CI__VI      regSDMA0_GFX_SKIP_CNTL__CI__VI;
typedef union SDMA0_GFX_VIRTUAL_ADDR__CI__VI   regSDMA0_GFX_VIRTUAL_ADDR__CI__VI;
typedef union SDMA0_HASH__CI__VI               regSDMA0_HASH__CI__VI;
typedef union SDMA0_IB_OFFSET_FETCH__CI__VI    regSDMA0_IB_OFFSET_FETCH__CI__VI;
typedef union SDMA0_PERFCOUNTER0_RESULT__CI__VI regSDMA0_PERFCOUNTER0_RESULT__CI__VI;
typedef union SDMA0_PERFCOUNTER1_RESULT__CI__VI regSDMA0_PERFCOUNTER1_RESULT__CI__VI;
typedef union SDMA0_PERFMON_CNTL__CI__VI       regSDMA0_PERFMON_CNTL__CI__VI;
typedef union SDMA0_PHASE0_QUANTUM__CI__VI     regSDMA0_PHASE0_QUANTUM__CI__VI;
typedef union SDMA0_PHASE1_QUANTUM__CI__VI     regSDMA0_PHASE1_QUANTUM__CI__VI;
typedef union SDMA0_POWER_CNTL__CI__VI         regSDMA0_POWER_CNTL__CI__VI;
typedef union SDMA0_PROGRAM__CI__VI            regSDMA0_PROGRAM__CI__VI;
typedef union SDMA0_RB_RPTR_FETCH__CI__VI      regSDMA0_RB_RPTR_FETCH__CI__VI;
typedef union SDMA0_RLC0_APE1_CNTL__CI__VI     regSDMA0_RLC0_APE1_CNTL__CI__VI;
typedef union SDMA0_RLC0_CONTEXT_STATUS__CI__VI regSDMA0_RLC0_CONTEXT_STATUS__CI__VI;
typedef union SDMA0_RLC0_DOORBELL_LOG__CI__VI  regSDMA0_RLC0_DOORBELL_LOG__CI__VI;
typedef union SDMA0_RLC0_DOORBELL__CI__VI      regSDMA0_RLC0_DOORBELL__CI__VI;
typedef union SDMA0_RLC0_IB_BASE_HI__CI__VI    regSDMA0_RLC0_IB_BASE_HI__CI__VI;
typedef union SDMA0_RLC0_IB_BASE_LO__CI__VI    regSDMA0_RLC0_IB_BASE_LO__CI__VI;
typedef union SDMA0_RLC0_IB_CNTL__CI__VI       regSDMA0_RLC0_IB_CNTL__CI__VI;
typedef union SDMA0_RLC0_IB_OFFSET__CI__VI     regSDMA0_RLC0_IB_OFFSET__CI__VI;
typedef union SDMA0_RLC0_IB_RPTR__CI__VI       regSDMA0_RLC0_IB_RPTR__CI__VI;
typedef union SDMA0_RLC0_IB_SIZE__CI__VI       regSDMA0_RLC0_IB_SIZE__CI__VI;
typedef union SDMA0_RLC0_RB_BASE_HI__CI__VI    regSDMA0_RLC0_RB_BASE_HI__CI__VI;
typedef union SDMA0_RLC0_RB_BASE__CI__VI       regSDMA0_RLC0_RB_BASE__CI__VI;
typedef union SDMA0_RLC0_RB_CNTL__CI__VI       regSDMA0_RLC0_RB_CNTL__CI__VI;
typedef union SDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI regSDMA0_RLC0_RB_RPTR_ADDR_HI__CI__VI;
typedef union SDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI regSDMA0_RLC0_RB_RPTR_ADDR_LO__CI__VI;
typedef union SDMA0_RLC0_RB_RPTR__CI__VI       regSDMA0_RLC0_RB_RPTR__CI__VI;
typedef union SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI;
typedef union SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI;
typedef union SDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI regSDMA0_RLC0_RB_WPTR_POLL_CNTL__CI__VI;
typedef union SDMA0_RLC0_RB_WPTR__CI__VI       regSDMA0_RLC0_RB_WPTR__CI__VI;
typedef union SDMA0_RLC0_SKIP_CNTL__CI__VI     regSDMA0_RLC0_SKIP_CNTL__CI__VI;
typedef union SDMA0_RLC0_VIRTUAL_ADDR__CI__VI  regSDMA0_RLC0_VIRTUAL_ADDR__CI__VI;
typedef union SDMA0_RLC1_APE1_CNTL__CI__VI     regSDMA0_RLC1_APE1_CNTL__CI__VI;
typedef union SDMA0_RLC1_CONTEXT_STATUS__CI__VI regSDMA0_RLC1_CONTEXT_STATUS__CI__VI;
typedef union SDMA0_RLC1_DOORBELL_LOG__CI__VI  regSDMA0_RLC1_DOORBELL_LOG__CI__VI;
typedef union SDMA0_RLC1_DOORBELL__CI__VI      regSDMA0_RLC1_DOORBELL__CI__VI;
typedef union SDMA0_RLC1_IB_BASE_HI__CI__VI    regSDMA0_RLC1_IB_BASE_HI__CI__VI;
typedef union SDMA0_RLC1_IB_BASE_LO__CI__VI    regSDMA0_RLC1_IB_BASE_LO__CI__VI;
typedef union SDMA0_RLC1_IB_CNTL__CI__VI       regSDMA0_RLC1_IB_CNTL__CI__VI;
typedef union SDMA0_RLC1_IB_OFFSET__CI__VI     regSDMA0_RLC1_IB_OFFSET__CI__VI;
typedef union SDMA0_RLC1_IB_RPTR__CI__VI       regSDMA0_RLC1_IB_RPTR__CI__VI;
typedef union SDMA0_RLC1_IB_SIZE__CI__VI       regSDMA0_RLC1_IB_SIZE__CI__VI;
typedef union SDMA0_RLC1_RB_BASE_HI__CI__VI    regSDMA0_RLC1_RB_BASE_HI__CI__VI;
typedef union SDMA0_RLC1_RB_BASE__CI__VI       regSDMA0_RLC1_RB_BASE__CI__VI;
typedef union SDMA0_RLC1_RB_CNTL__CI__VI       regSDMA0_RLC1_RB_CNTL__CI__VI;
typedef union SDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI regSDMA0_RLC1_RB_RPTR_ADDR_HI__CI__VI;
typedef union SDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI regSDMA0_RLC1_RB_RPTR_ADDR_LO__CI__VI;
typedef union SDMA0_RLC1_RB_RPTR__CI__VI       regSDMA0_RLC1_RB_RPTR__CI__VI;
typedef union SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI;
typedef union SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI;
typedef union SDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI regSDMA0_RLC1_RB_WPTR_POLL_CNTL__CI__VI;
typedef union SDMA0_RLC1_RB_WPTR__CI__VI       regSDMA0_RLC1_RB_WPTR__CI__VI;
typedef union SDMA0_RLC1_SKIP_CNTL__CI__VI     regSDMA0_RLC1_SKIP_CNTL__CI__VI;
typedef union SDMA0_RLC1_VIRTUAL_ADDR__CI__VI  regSDMA0_RLC1_VIRTUAL_ADDR__CI__VI;
typedef union SDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI regSDMA0_SEM_INCOMPLETE_TIMER_CNTL__CI;
typedef union SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI;
typedef union SDMA0_STATUS1_REG__CI__VI        regSDMA0_STATUS1_REG__CI__VI;
typedef union SDMA0_STATUS_REG__CI             regSDMA0_STATUS_REG__CI;
typedef union SDMA0_STATUS_REG__VI             regSDMA0_STATUS_REG__VI;
typedef union SDMA0_TILING_CONFIG__CI__VI      regSDMA0_TILING_CONFIG__CI__VI;
typedef union SDMA0_UCODE_ADDR__CI__VI         regSDMA0_UCODE_ADDR__CI__VI;
typedef union SDMA0_UCODE_DATA__CI__VI         regSDMA0_UCODE_DATA__CI__VI;
typedef union SDMA1_CHICKEN_BITS__CI__VI       regSDMA1_CHICKEN_BITS__CI__VI;
typedef union SDMA1_CLK_CTRL__CI__VI           regSDMA1_CLK_CTRL__CI__VI;
typedef union SDMA1_CNTL__CI                   regSDMA1_CNTL__CI;
typedef union SDMA1_CNTL__VI                   regSDMA1_CNTL__VI;
typedef union SDMA1_CONFIG__CI__VI             regSDMA1_CONFIG__CI__VI;
typedef union SDMA1_F32_CNTL__CI__VI           regSDMA1_F32_CNTL__CI__VI;
typedef union SDMA1_FREEZE__CI__VI             regSDMA1_FREEZE__CI__VI;
typedef union SDMA1_GFX_APE1_CNTL__CI__VI      regSDMA1_GFX_APE1_CNTL__CI__VI;
typedef union SDMA1_GFX_CONTEXT_CNTL__CI__VI   regSDMA1_GFX_CONTEXT_CNTL__CI__VI;
typedef union SDMA1_GFX_CONTEXT_STATUS__CI__VI regSDMA1_GFX_CONTEXT_STATUS__CI__VI;
typedef union SDMA1_GFX_IB_BASE_HI__CI__VI     regSDMA1_GFX_IB_BASE_HI__CI__VI;
typedef union SDMA1_GFX_IB_BASE_LO__CI__VI     regSDMA1_GFX_IB_BASE_LO__CI__VI;
typedef union SDMA1_GFX_IB_CNTL__CI__VI        regSDMA1_GFX_IB_CNTL__CI__VI;
typedef union SDMA1_GFX_IB_OFFSET__CI__VI      regSDMA1_GFX_IB_OFFSET__CI__VI;
typedef union SDMA1_GFX_IB_RPTR__CI__VI        regSDMA1_GFX_IB_RPTR__CI__VI;
typedef union SDMA1_GFX_IB_SIZE__CI__VI        regSDMA1_GFX_IB_SIZE__CI__VI;
typedef union SDMA1_GFX_RB_BASE_HI__CI__VI     regSDMA1_GFX_RB_BASE_HI__CI__VI;
typedef union SDMA1_GFX_RB_BASE__CI__VI        regSDMA1_GFX_RB_BASE__CI__VI;
typedef union SDMA1_GFX_RB_CNTL__CI__VI        regSDMA1_GFX_RB_CNTL__CI__VI;
typedef union SDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI regSDMA1_GFX_RB_RPTR_ADDR_HI__CI__VI;
typedef union SDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI regSDMA1_GFX_RB_RPTR_ADDR_LO__CI__VI;
typedef union SDMA1_GFX_RB_RPTR__CI__VI        regSDMA1_GFX_RB_RPTR__CI__VI;
typedef union SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI__CI__VI;
typedef union SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO__CI__VI;
typedef union SDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI regSDMA1_GFX_RB_WPTR_POLL_CNTL__CI__VI;
typedef union SDMA1_GFX_RB_WPTR__CI__VI        regSDMA1_GFX_RB_WPTR__CI__VI;
typedef union SDMA1_GFX_SKIP_CNTL__CI__VI      regSDMA1_GFX_SKIP_CNTL__CI__VI;
typedef union SDMA1_GFX_VIRTUAL_ADDR__CI__VI   regSDMA1_GFX_VIRTUAL_ADDR__CI__VI;
typedef union SDMA1_HASH__CI__VI               regSDMA1_HASH__CI__VI;
typedef union SDMA1_IB_OFFSET_FETCH__CI__VI    regSDMA1_IB_OFFSET_FETCH__CI__VI;
typedef union SDMA1_PERFCOUNTER0_RESULT__CI__VI regSDMA1_PERFCOUNTER0_RESULT__CI__VI;
typedef union SDMA1_PERFCOUNTER1_RESULT__CI__VI regSDMA1_PERFCOUNTER1_RESULT__CI__VI;
typedef union SDMA1_PERFMON_CNTL__CI__VI       regSDMA1_PERFMON_CNTL__CI__VI;
typedef union SDMA1_PHASE0_QUANTUM__CI__VI     regSDMA1_PHASE0_QUANTUM__CI__VI;
typedef union SDMA1_PHASE1_QUANTUM__CI__VI     regSDMA1_PHASE1_QUANTUM__CI__VI;
typedef union SDMA1_POWER_CNTL__CI__VI         regSDMA1_POWER_CNTL__CI__VI;
typedef union SDMA1_PROGRAM__CI__VI            regSDMA1_PROGRAM__CI__VI;
typedef union SDMA1_RB_RPTR_FETCH__CI__VI      regSDMA1_RB_RPTR_FETCH__CI__VI;
typedef union SDMA1_RLC0_APE1_CNTL__CI__VI     regSDMA1_RLC0_APE1_CNTL__CI__VI;
typedef union SDMA1_RLC0_CONTEXT_STATUS__CI__VI regSDMA1_RLC0_CONTEXT_STATUS__CI__VI;
typedef union SDMA1_RLC0_DOORBELL_LOG__CI__VI  regSDMA1_RLC0_DOORBELL_LOG__CI__VI;
typedef union SDMA1_RLC0_DOORBELL__CI__VI      regSDMA1_RLC0_DOORBELL__CI__VI;
typedef union SDMA1_RLC0_IB_BASE_HI__CI__VI    regSDMA1_RLC0_IB_BASE_HI__CI__VI;
typedef union SDMA1_RLC0_IB_BASE_LO__CI__VI    regSDMA1_RLC0_IB_BASE_LO__CI__VI;
typedef union SDMA1_RLC0_IB_CNTL__CI__VI       regSDMA1_RLC0_IB_CNTL__CI__VI;
typedef union SDMA1_RLC0_IB_OFFSET__CI__VI     regSDMA1_RLC0_IB_OFFSET__CI__VI;
typedef union SDMA1_RLC0_IB_RPTR__CI__VI       regSDMA1_RLC0_IB_RPTR__CI__VI;
typedef union SDMA1_RLC0_IB_SIZE__CI__VI       regSDMA1_RLC0_IB_SIZE__CI__VI;
typedef union SDMA1_RLC0_RB_BASE_HI__CI__VI    regSDMA1_RLC0_RB_BASE_HI__CI__VI;
typedef union SDMA1_RLC0_RB_BASE__CI__VI       regSDMA1_RLC0_RB_BASE__CI__VI;
typedef union SDMA1_RLC0_RB_CNTL__CI__VI       regSDMA1_RLC0_RB_CNTL__CI__VI;
typedef union SDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI regSDMA1_RLC0_RB_RPTR_ADDR_HI__CI__VI;
typedef union SDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI regSDMA1_RLC0_RB_RPTR_ADDR_LO__CI__VI;
typedef union SDMA1_RLC0_RB_RPTR__CI__VI       regSDMA1_RLC0_RB_RPTR__CI__VI;
typedef union SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__CI__VI;
typedef union SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__CI__VI;
typedef union SDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI regSDMA1_RLC0_RB_WPTR_POLL_CNTL__CI__VI;
typedef union SDMA1_RLC0_RB_WPTR__CI__VI       regSDMA1_RLC0_RB_WPTR__CI__VI;
typedef union SDMA1_RLC0_SKIP_CNTL__CI__VI     regSDMA1_RLC0_SKIP_CNTL__CI__VI;
typedef union SDMA1_RLC0_VIRTUAL_ADDR__CI__VI  regSDMA1_RLC0_VIRTUAL_ADDR__CI__VI;
typedef union SDMA1_RLC1_APE1_CNTL__CI__VI     regSDMA1_RLC1_APE1_CNTL__CI__VI;
typedef union SDMA1_RLC1_CONTEXT_STATUS__CI__VI regSDMA1_RLC1_CONTEXT_STATUS__CI__VI;
typedef union SDMA1_RLC1_DOORBELL_LOG__CI__VI  regSDMA1_RLC1_DOORBELL_LOG__CI__VI;
typedef union SDMA1_RLC1_DOORBELL__CI__VI      regSDMA1_RLC1_DOORBELL__CI__VI;
typedef union SDMA1_RLC1_IB_BASE_HI__CI__VI    regSDMA1_RLC1_IB_BASE_HI__CI__VI;
typedef union SDMA1_RLC1_IB_BASE_LO__CI__VI    regSDMA1_RLC1_IB_BASE_LO__CI__VI;
typedef union SDMA1_RLC1_IB_CNTL__CI__VI       regSDMA1_RLC1_IB_CNTL__CI__VI;
typedef union SDMA1_RLC1_IB_OFFSET__CI__VI     regSDMA1_RLC1_IB_OFFSET__CI__VI;
typedef union SDMA1_RLC1_IB_RPTR__CI__VI       regSDMA1_RLC1_IB_RPTR__CI__VI;
typedef union SDMA1_RLC1_IB_SIZE__CI__VI       regSDMA1_RLC1_IB_SIZE__CI__VI;
typedef union SDMA1_RLC1_RB_BASE_HI__CI__VI    regSDMA1_RLC1_RB_BASE_HI__CI__VI;
typedef union SDMA1_RLC1_RB_BASE__CI__VI       regSDMA1_RLC1_RB_BASE__CI__VI;
typedef union SDMA1_RLC1_RB_CNTL__CI__VI       regSDMA1_RLC1_RB_CNTL__CI__VI;
typedef union SDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI regSDMA1_RLC1_RB_RPTR_ADDR_HI__CI__VI;
typedef union SDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI regSDMA1_RLC1_RB_RPTR_ADDR_LO__CI__VI;
typedef union SDMA1_RLC1_RB_RPTR__CI__VI       regSDMA1_RLC1_RB_RPTR__CI__VI;
typedef union SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__CI__VI;
typedef union SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__CI__VI;
typedef union SDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI regSDMA1_RLC1_RB_WPTR_POLL_CNTL__CI__VI;
typedef union SDMA1_RLC1_RB_WPTR__CI__VI       regSDMA1_RLC1_RB_WPTR__CI__VI;
typedef union SDMA1_RLC1_SKIP_CNTL__CI__VI     regSDMA1_RLC1_SKIP_CNTL__CI__VI;
typedef union SDMA1_RLC1_VIRTUAL_ADDR__CI__VI  regSDMA1_RLC1_VIRTUAL_ADDR__CI__VI;
typedef union SDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI regSDMA1_SEM_INCOMPLETE_TIMER_CNTL__CI;
typedef union SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL__CI__VI;
typedef union SDMA1_STATUS1_REG__CI__VI        regSDMA1_STATUS1_REG__CI__VI;
typedef union SDMA1_STATUS_REG__CI             regSDMA1_STATUS_REG__CI;
typedef union SDMA1_STATUS_REG__VI             regSDMA1_STATUS_REG__VI;
typedef union SDMA1_TILING_CONFIG__CI__VI      regSDMA1_TILING_CONFIG__CI__VI;
typedef union SDMA1_UCODE_ADDR__CI__VI         regSDMA1_UCODE_ADDR__CI__VI;
typedef union SDMA1_UCODE_DATA__CI__VI         regSDMA1_UCODE_DATA__CI__VI;
typedef union SDMA_CONFIG__CI__VI              regSDMA_CONFIG__CI__VI;
typedef union SDMA_PGFSM_CONFIG__CI__VI        regSDMA_PGFSM_CONFIG__CI__VI;
typedef union SDMA_PGFSM_READ__CI__VI          regSDMA_PGFSM_READ__CI__VI;
typedef union SDMA_PGFSM_WRITE__CI__VI         regSDMA_PGFSM_WRITE__CI__VI;
typedef union SDMA_POWER_GATING__CI__VI        regSDMA_POWER_GATING__CI__VI;
typedef union SEM_CHICKEN_BITS__CI__VI         regSEM_CHICKEN_BITS__CI__VI;
typedef union SEM_EDC_CONFIG__CI__VI           regSEM_EDC_CONFIG__CI__VI;
typedef union SEM_MAILBOX                      regSEM_MAILBOX;
typedef union SEM_MAILBOX_CLIENTCONFIG__CI__VI regSEM_MAILBOX_CLIENTCONFIG__CI__VI;
typedef union SEM_MAILBOX_CLIENTCONFIG__SI     regSEM_MAILBOX_CLIENTCONFIG__SI;
typedef union SEM_MAILBOX_CONTROL              regSEM_MAILBOX_CONTROL;
typedef union SEM_MCIF_CONFIG                  regSEM_MCIF_CONFIG;
typedef union SEM_STATUS__CI__VI               regSEM_STATUS__CI__VI;
typedef union SEQ00__SI__VI                    regSEQ00__SI__VI;
typedef union SEQ01__SI__VI                    regSEQ01__SI__VI;
typedef union SEQ02__SI__VI                    regSEQ02__SI__VI;
typedef union SEQ03__SI__VI                    regSEQ03__SI__VI;
typedef union SEQ04__SI__VI                    regSEQ04__SI__VI;
typedef union SEQ8_DATA__SI__VI                regSEQ8_DATA__SI__VI;
typedef union SEQ8_IDX__SI__VI                 regSEQ8_IDX__SI__VI;
typedef union SETUP_DEBUG_REG0                 regSETUP_DEBUG_REG0;
typedef union SETUP_DEBUG_REG1                 regSETUP_DEBUG_REG1;
typedef union SETUP_DEBUG_REG2                 regSETUP_DEBUG_REG2;
typedef union SETUP_DEBUG_REG3                 regSETUP_DEBUG_REG3;
typedef union SETUP_DEBUG_REG4                 regSETUP_DEBUG_REG4;
typedef union SETUP_DEBUG_REG5                 regSETUP_DEBUG_REG5;
typedef union SH_HIDDEN_PRIVATE_BASE_VMID__CI__VI regSH_HIDDEN_PRIVATE_BASE_VMID__CI__VI;
typedef union SH_MEM_APE1_BASE__CI__VI         regSH_MEM_APE1_BASE__CI__VI;
typedef union SH_MEM_APE1_LIMIT__CI__VI        regSH_MEM_APE1_LIMIT__CI__VI;
typedef union SH_MEM_BASES__CI__VI             regSH_MEM_BASES__CI__VI;
typedef union SH_MEM_CONFIG__CI                regSH_MEM_CONFIG__CI;
typedef union SH_MEM_CONFIG__VI                regSH_MEM_CONFIG__VI;
typedef union SH_STATIC_MEM_CONFIG__CI__VI     regSH_STATIC_MEM_CONFIG__CI__VI;
typedef union SLAVE_COMM_CMD_REG__SI__VI       regSLAVE_COMM_CMD_REG__SI__VI;
typedef union SLAVE_COMM_CNTL_REG__SI__VI      regSLAVE_COMM_CNTL_REG__SI__VI;
typedef union SLAVE_COMM_DATA_REG1__SI__VI     regSLAVE_COMM_DATA_REG1__SI__VI;
typedef union SLAVE_COMM_DATA_REG2__SI__VI     regSLAVE_COMM_DATA_REG2__SI__VI;
typedef union SLAVE_COMM_DATA_REG3__SI__VI     regSLAVE_COMM_DATA_REG3__SI__VI;
typedef union SLAVE_HANG_ERROR                 regSLAVE_HANG_ERROR;
typedef union SLAVE_HANG_PROTECTION_CNTL       regSLAVE_HANG_PROTECTION_CNTL;
typedef union SLAVE_REQ_CREDIT_CNTL            regSLAVE_REQ_CREDIT_CNTL;
typedef union SMBCLK_PAD_CNTL__CI              regSMBCLK_PAD_CNTL__CI;
typedef union SMBCLK_PAD_CNTL__VI              regSMBCLK_PAD_CNTL__VI;
typedef union SMBDAT_PAD_CNTL__CI              regSMBDAT_PAD_CNTL__CI;
typedef union SMBDAT_PAD_CNTL__VI              regSMBDAT_PAD_CNTL__VI;
typedef union SMBUS_SLV_CNTL__CI               regSMBUS_SLV_CNTL__CI;
typedef union SMC_IND_ACCESS_CNTL__SI__CI      regSMC_IND_ACCESS_CNTL__SI__CI;
typedef union SMC_IND_ACCESS_CNTL__VI          regSMC_IND_ACCESS_CNTL__VI;
typedef union SMC_IND_DATA                     regSMC_IND_DATA;
typedef union SMC_IND_DATA_0__CI__VI           regSMC_IND_DATA_0__CI__VI;
typedef union SMC_IND_DATA_1__CI__VI           regSMC_IND_DATA_1__CI__VI;
typedef union SMC_IND_DATA_2__CI__VI           regSMC_IND_DATA_2__CI__VI;
typedef union SMC_IND_DATA_3__CI__VI           regSMC_IND_DATA_3__CI__VI;
typedef union SMC_IND_DATA_4__CI__VI           regSMC_IND_DATA_4__CI__VI;
typedef union SMC_IND_DATA_5__CI__VI           regSMC_IND_DATA_5__CI__VI;
typedef union SMC_IND_DATA_6__CI__VI           regSMC_IND_DATA_6__CI__VI;
typedef union SMC_IND_DATA_7__CI__VI           regSMC_IND_DATA_7__CI__VI;
typedef union SMC_IND_INDEX                    regSMC_IND_INDEX;
typedef union SMC_IND_INDEX_0__CI__VI          regSMC_IND_INDEX_0__CI__VI;
typedef union SMC_IND_INDEX_1__CI__VI          regSMC_IND_INDEX_1__CI__VI;
typedef union SMC_IND_INDEX_2__CI__VI          regSMC_IND_INDEX_2__CI__VI;
typedef union SMC_IND_INDEX_3__CI__VI          regSMC_IND_INDEX_3__CI__VI;
typedef union SMC_IND_INDEX_4__CI__VI          regSMC_IND_INDEX_4__CI__VI;
typedef union SMC_IND_INDEX_5__CI__VI          regSMC_IND_INDEX_5__CI__VI;
typedef union SMC_IND_INDEX_6__CI__VI          regSMC_IND_INDEX_6__CI__VI;
typedef union SMC_IND_INDEX_7__CI__VI          regSMC_IND_INDEX_7__CI__VI;
typedef union SMC_MESSAGE_0__CI__VI            regSMC_MESSAGE_0__CI__VI;
typedef union SMC_MESSAGE_0__SI                regSMC_MESSAGE_0__SI;
typedef union SMC_MESSAGE_10__CI__VI           regSMC_MESSAGE_10__CI__VI;
typedef union SMC_MESSAGE_11__CI__VI           regSMC_MESSAGE_11__CI__VI;
typedef union SMC_MESSAGE_1__CI__VI            regSMC_MESSAGE_1__CI__VI;
typedef union SMC_MESSAGE_1__SI                regSMC_MESSAGE_1__SI;
typedef union SMC_MESSAGE_2__CI__VI            regSMC_MESSAGE_2__CI__VI;
typedef union SMC_MESSAGE_3__CI__VI            regSMC_MESSAGE_3__CI__VI;
typedef union SMC_MESSAGE_4__CI__VI            regSMC_MESSAGE_4__CI__VI;
typedef union SMC_MESSAGE_5__CI__VI            regSMC_MESSAGE_5__CI__VI;
typedef union SMC_MESSAGE_6__CI__VI            regSMC_MESSAGE_6__CI__VI;
typedef union SMC_MESSAGE_7__CI__VI            regSMC_MESSAGE_7__CI__VI;
typedef union SMC_MESSAGE_8__CI__VI            regSMC_MESSAGE_8__CI__VI;
typedef union SMC_MESSAGE_9__CI__VI            regSMC_MESSAGE_9__CI__VI;
typedef union SMC_MSG_ARG_0__CI__VI            regSMC_MSG_ARG_0__CI__VI;
typedef union SMC_MSG_ARG_10__CI__VI           regSMC_MSG_ARG_10__CI__VI;
typedef union SMC_MSG_ARG_11__CI__VI           regSMC_MSG_ARG_11__CI__VI;
typedef union SMC_MSG_ARG_1__CI__VI            regSMC_MSG_ARG_1__CI__VI;
typedef union SMC_MSG_ARG_2__CI__VI            regSMC_MSG_ARG_2__CI__VI;
typedef union SMC_MSG_ARG_3__CI__VI            regSMC_MSG_ARG_3__CI__VI;
typedef union SMC_MSG_ARG_4__CI__VI            regSMC_MSG_ARG_4__CI__VI;
typedef union SMC_MSG_ARG_5__CI__VI            regSMC_MSG_ARG_5__CI__VI;
typedef union SMC_MSG_ARG_6__CI__VI            regSMC_MSG_ARG_6__CI__VI;
typedef union SMC_MSG_ARG_7__CI__VI            regSMC_MSG_ARG_7__CI__VI;
typedef union SMC_MSG_ARG_8__CI__VI            regSMC_MSG_ARG_8__CI__VI;
typedef union SMC_MSG_ARG_9__CI__VI            regSMC_MSG_ARG_9__CI__VI;
typedef union SMC_PC_C__CI__VI                 regSMC_PC_C__CI__VI;
typedef union SMC_PC__SI                       regSMC_PC__SI;
typedef union SMC_RESP_0__CI__VI               regSMC_RESP_0__CI__VI;
typedef union SMC_RESP_0__SI                   regSMC_RESP_0__SI;
typedef union SMC_RESP_10__CI__VI              regSMC_RESP_10__CI__VI;
typedef union SMC_RESP_11__CI__VI              regSMC_RESP_11__CI__VI;
typedef union SMC_RESP_1__CI__VI               regSMC_RESP_1__CI__VI;
typedef union SMC_RESP_1__SI                   regSMC_RESP_1__SI;
typedef union SMC_RESP_2__CI__VI               regSMC_RESP_2__CI__VI;
typedef union SMC_RESP_3__CI__VI               regSMC_RESP_3__CI__VI;
typedef union SMC_RESP_4__CI__VI               regSMC_RESP_4__CI__VI;
typedef union SMC_RESP_5__CI__VI               regSMC_RESP_5__CI__VI;
typedef union SMC_RESP_6__CI__VI               regSMC_RESP_6__CI__VI;
typedef union SMC_RESP_7__CI__VI               regSMC_RESP_7__CI__VI;
typedef union SMC_RESP_8__CI__VI               regSMC_RESP_8__CI__VI;
typedef union SMC_RESP_9__CI__VI               regSMC_RESP_9__CI__VI;
typedef union SMC_SCRATCH9                     regSMC_SCRATCH9;
typedef union SMC_SYSCON_MISC_CNTL__CI__VI     regSMC_SYSCON_MISC_CNTL__CI__VI;
typedef union SMC_SYSCON_MSG_ARG_0__CI__VI     regSMC_SYSCON_MSG_ARG_0__CI__VI;
typedef union SMU_EFUSE_0__CI__VI              regSMU_EFUSE_0__CI__VI;
typedef union SMU_MAIN_PLL_OP_FREQ__CI__VI     regSMU_MAIN_PLL_OP_FREQ__CI__VI;
typedef union SMU_SMC_IND_DATA__CI__VI         regSMU_SMC_IND_DATA__CI__VI;
typedef union SMU_SMC_IND_INDEX__CI__VI        regSMU_SMC_IND_INDEX__CI__VI;
typedef union SPI_ARB_CYCLES_0                 regSPI_ARB_CYCLES_0;
typedef union SPI_ARB_CYCLES_1                 regSPI_ARB_CYCLES_1;
typedef union SPI_ARB_PRIORITY__CI__VI         regSPI_ARB_PRIORITY__CI__VI;
typedef union SPI_ARB_PRIORITY__SI             regSPI_ARB_PRIORITY__SI;
typedef union SPI_BARYC_CNTL                   regSPI_BARYC_CNTL;
typedef union SPI_CDBG_SYS_CS0__CI__VI         regSPI_CDBG_SYS_CS0__CI__VI;
typedef union SPI_CDBG_SYS_CS1__CI__VI         regSPI_CDBG_SYS_CS1__CI__VI;
typedef union SPI_CDBG_SYS_GFX__CI__VI         regSPI_CDBG_SYS_GFX__CI__VI;
typedef union SPI_CDBG_SYS_HP3D__CI__VI        regSPI_CDBG_SYS_HP3D__CI__VI;
typedef union SPI_COMPUTE_QUEUE_RESET__CI__VI  regSPI_COMPUTE_QUEUE_RESET__CI__VI;
typedef union SPI_CONFIG_CNTL                  regSPI_CONFIG_CNTL;
typedef union SPI_CONFIG_CNTL_1                regSPI_CONFIG_CNTL_1;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_0__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_1__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_2__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_3__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_4__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_5__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_6__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI regSPI_CSQ_WF_ACTIVE_COUNT_7__CI__VI;
typedef union SPI_CSQ_WF_ACTIVE_STATUS__CI__VI regSPI_CSQ_WF_ACTIVE_STATUS__CI__VI;
typedef union SPI_DEBUG_BUSY__CI__VI           regSPI_DEBUG_BUSY__CI__VI;
typedef union SPI_DEBUG_BUSY__SI               regSPI_DEBUG_BUSY__SI;
typedef union SPI_DEBUG_CNTL__CI__VI           regSPI_DEBUG_CNTL__CI__VI;
typedef union SPI_DEBUG_CNTL__SI               regSPI_DEBUG_CNTL__SI;
typedef union SPI_DEBUG_READ                   regSPI_DEBUG_READ;
typedef union SPI_GDBG_TBA_HI__CI__VI          regSPI_GDBG_TBA_HI__CI__VI;
typedef union SPI_GDBG_TBA_LO__CI__VI          regSPI_GDBG_TBA_LO__CI__VI;
typedef union SPI_GDBG_TMA_HI__CI__VI          regSPI_GDBG_TMA_HI__CI__VI;
typedef union SPI_GDBG_TMA_LO__CI__VI          regSPI_GDBG_TMA_LO__CI__VI;
typedef union SPI_GDBG_TRAP_CONFIG__CI__VI     regSPI_GDBG_TRAP_CONFIG__CI__VI;
typedef union SPI_GDBG_TRAP_DATA0__CI__VI      regSPI_GDBG_TRAP_DATA0__CI__VI;
typedef union SPI_GDBG_TRAP_DATA1__CI__VI      regSPI_GDBG_TRAP_DATA1__CI__VI;
typedef union SPI_GDBG_TRAP_MASK__CI__VI       regSPI_GDBG_TRAP_MASK__CI__VI;
typedef union SPI_GDBG_WAVE_CNTL__CI__VI       regSPI_GDBG_WAVE_CNTL__CI__VI;
typedef union SPI_GDS_CREDITS                  regSPI_GDS_CREDITS;
typedef union SPI_INTERP_CONTROL_0             regSPI_INTERP_CONTROL_0;
typedef union SPI_LB_CTR_CTRL                  regSPI_LB_CTR_CTRL;
typedef union SPI_LB_CU_MASK                   regSPI_LB_CU_MASK;
typedef union SPI_LB_DATA_REG                  regSPI_LB_DATA_REG;
typedef union SPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI regSPI_P0_TRAP_SCREEN_GPR_MIN__CI__VI;
typedef union SPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI regSPI_P0_TRAP_SCREEN_PSBA_HI__CI__VI;
typedef union SPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI regSPI_P0_TRAP_SCREEN_PSBA_LO__CI__VI;
typedef union SPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI regSPI_P0_TRAP_SCREEN_PSMA_HI__CI__VI;
typedef union SPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI regSPI_P0_TRAP_SCREEN_PSMA_LO__CI__VI;
typedef union SPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI regSPI_P1_TRAP_SCREEN_GPR_MIN__CI__VI;
typedef union SPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI regSPI_P1_TRAP_SCREEN_PSBA_HI__CI__VI;
typedef union SPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI regSPI_P1_TRAP_SCREEN_PSBA_LO__CI__VI;
typedef union SPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI regSPI_P1_TRAP_SCREEN_PSMA_HI__CI__VI;
typedef union SPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI regSPI_P1_TRAP_SCREEN_PSMA_LO__CI__VI;
typedef union SPI_PERFCOUNTER0_HI              regSPI_PERFCOUNTER0_HI;
typedef union SPI_PERFCOUNTER0_LO              regSPI_PERFCOUNTER0_LO;
typedef union SPI_PERFCOUNTER0_SELECT          regSPI_PERFCOUNTER0_SELECT;
typedef union SPI_PERFCOUNTER0_SELECT1__CI__VI regSPI_PERFCOUNTER0_SELECT1__CI__VI;
typedef union SPI_PERFCOUNTER1_HI              regSPI_PERFCOUNTER1_HI;
typedef union SPI_PERFCOUNTER1_LO              regSPI_PERFCOUNTER1_LO;
typedef union SPI_PERFCOUNTER1_SELECT          regSPI_PERFCOUNTER1_SELECT;
typedef union SPI_PERFCOUNTER1_SELECT1__CI__VI regSPI_PERFCOUNTER1_SELECT1__CI__VI;
typedef union SPI_PERFCOUNTER2_HI              regSPI_PERFCOUNTER2_HI;
typedef union SPI_PERFCOUNTER2_LO              regSPI_PERFCOUNTER2_LO;
typedef union SPI_PERFCOUNTER2_SELECT          regSPI_PERFCOUNTER2_SELECT;
typedef union SPI_PERFCOUNTER2_SELECT1__CI__VI regSPI_PERFCOUNTER2_SELECT1__CI__VI;
typedef union SPI_PERFCOUNTER3_HI              regSPI_PERFCOUNTER3_HI;
typedef union SPI_PERFCOUNTER3_LO              regSPI_PERFCOUNTER3_LO;
typedef union SPI_PERFCOUNTER3_SELECT          regSPI_PERFCOUNTER3_SELECT;
typedef union SPI_PERFCOUNTER3_SELECT1__CI__VI regSPI_PERFCOUNTER3_SELECT1__CI__VI;
typedef union SPI_PERFCOUNTER4_HI__CI__VI      regSPI_PERFCOUNTER4_HI__CI__VI;
typedef union SPI_PERFCOUNTER4_LO__CI__VI      regSPI_PERFCOUNTER4_LO__CI__VI;
typedef union SPI_PERFCOUNTER4_SELECT__CI__VI  regSPI_PERFCOUNTER4_SELECT__CI__VI;
typedef union SPI_PERFCOUNTER5_HI__CI__VI      regSPI_PERFCOUNTER5_HI__CI__VI;
typedef union SPI_PERFCOUNTER5_LO__CI__VI      regSPI_PERFCOUNTER5_LO__CI__VI;
typedef union SPI_PERFCOUNTER5_SELECT__CI__VI  regSPI_PERFCOUNTER5_SELECT__CI__VI;
typedef union SPI_PERFCOUNTER_BINS             regSPI_PERFCOUNTER_BINS;
typedef union SPI_PG_ENABLE_STATIC_CU_MASK     regSPI_PG_ENABLE_STATIC_CU_MASK;
typedef union SPI_PS_INPUT_ADDR                regSPI_PS_INPUT_ADDR;
typedef union SPI_PS_INPUT_CNTL_0              regSPI_PS_INPUT_CNTL_0;
typedef union SPI_PS_INPUT_CNTL_1              regSPI_PS_INPUT_CNTL_1;
typedef union SPI_PS_INPUT_CNTL_10             regSPI_PS_INPUT_CNTL_10;
typedef union SPI_PS_INPUT_CNTL_11             regSPI_PS_INPUT_CNTL_11;
typedef union SPI_PS_INPUT_CNTL_12             regSPI_PS_INPUT_CNTL_12;
typedef union SPI_PS_INPUT_CNTL_13             regSPI_PS_INPUT_CNTL_13;
typedef union SPI_PS_INPUT_CNTL_14             regSPI_PS_INPUT_CNTL_14;
typedef union SPI_PS_INPUT_CNTL_15             regSPI_PS_INPUT_CNTL_15;
typedef union SPI_PS_INPUT_CNTL_16             regSPI_PS_INPUT_CNTL_16;
typedef union SPI_PS_INPUT_CNTL_17             regSPI_PS_INPUT_CNTL_17;
typedef union SPI_PS_INPUT_CNTL_18             regSPI_PS_INPUT_CNTL_18;
typedef union SPI_PS_INPUT_CNTL_19             regSPI_PS_INPUT_CNTL_19;
typedef union SPI_PS_INPUT_CNTL_2              regSPI_PS_INPUT_CNTL_2;
typedef union SPI_PS_INPUT_CNTL_20             regSPI_PS_INPUT_CNTL_20;
typedef union SPI_PS_INPUT_CNTL_21             regSPI_PS_INPUT_CNTL_21;
typedef union SPI_PS_INPUT_CNTL_22             regSPI_PS_INPUT_CNTL_22;
typedef union SPI_PS_INPUT_CNTL_23             regSPI_PS_INPUT_CNTL_23;
typedef union SPI_PS_INPUT_CNTL_24             regSPI_PS_INPUT_CNTL_24;
typedef union SPI_PS_INPUT_CNTL_25             regSPI_PS_INPUT_CNTL_25;
typedef union SPI_PS_INPUT_CNTL_26             regSPI_PS_INPUT_CNTL_26;
typedef union SPI_PS_INPUT_CNTL_27             regSPI_PS_INPUT_CNTL_27;
typedef union SPI_PS_INPUT_CNTL_28             regSPI_PS_INPUT_CNTL_28;
typedef union SPI_PS_INPUT_CNTL_29             regSPI_PS_INPUT_CNTL_29;
typedef union SPI_PS_INPUT_CNTL_3              regSPI_PS_INPUT_CNTL_3;
typedef union SPI_PS_INPUT_CNTL_30             regSPI_PS_INPUT_CNTL_30;
typedef union SPI_PS_INPUT_CNTL_31             regSPI_PS_INPUT_CNTL_31;
typedef union SPI_PS_INPUT_CNTL_4              regSPI_PS_INPUT_CNTL_4;
typedef union SPI_PS_INPUT_CNTL_5              regSPI_PS_INPUT_CNTL_5;
typedef union SPI_PS_INPUT_CNTL_6              regSPI_PS_INPUT_CNTL_6;
typedef union SPI_PS_INPUT_CNTL_7              regSPI_PS_INPUT_CNTL_7;
typedef union SPI_PS_INPUT_CNTL_8              regSPI_PS_INPUT_CNTL_8;
typedef union SPI_PS_INPUT_CNTL_9              regSPI_PS_INPUT_CNTL_9;
typedef union SPI_PS_INPUT_ENA                 regSPI_PS_INPUT_ENA;
typedef union SPI_PS_IN_CONTROL                regSPI_PS_IN_CONTROL;
typedef union SPI_PS_MAX_WAVE_ID               regSPI_PS_MAX_WAVE_ID;
typedef union SPI_RESET_DEBUG__CI__VI          regSPI_RESET_DEBUG__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_0__CI__VI regSPI_RESOURCE_RESERVE_CU_0__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_10__CI__VI regSPI_RESOURCE_RESERVE_CU_10__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_11__CI__VI regSPI_RESOURCE_RESERVE_CU_11__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_1__CI__VI regSPI_RESOURCE_RESERVE_CU_1__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_2__CI__VI regSPI_RESOURCE_RESERVE_CU_2__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_3__CI__VI regSPI_RESOURCE_RESERVE_CU_3__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_4__CI__VI regSPI_RESOURCE_RESERVE_CU_4__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_5__CI__VI regSPI_RESOURCE_RESERVE_CU_5__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_6__CI__VI regSPI_RESOURCE_RESERVE_CU_6__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_7__CI__VI regSPI_RESOURCE_RESERVE_CU_7__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_8__CI__VI regSPI_RESOURCE_RESERVE_CU_8__CI__VI;
typedef union SPI_RESOURCE_RESERVE_CU_9__CI__VI regSPI_RESOURCE_RESERVE_CU_9__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_0__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_0__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_10__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_10__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_11__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_11__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_1__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_1__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_2__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_2__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_3__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_3__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_4__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_4__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_5__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_5__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_6__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_6__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_7__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_7__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_8__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_8__CI__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_9__CI__VI regSPI_RESOURCE_RESERVE_EN_CU_9__CI__VI;
typedef union SPI_SHADER_COL_FORMAT            regSPI_SHADER_COL_FORMAT;
typedef union SPI_SHADER_LATE_ALLOC_VS__CI__VI regSPI_SHADER_LATE_ALLOC_VS__CI__VI;
typedef union SPI_SHADER_PGM_HI_ES             regSPI_SHADER_PGM_HI_ES;
typedef union SPI_SHADER_PGM_HI_GS             regSPI_SHADER_PGM_HI_GS;
typedef union SPI_SHADER_PGM_HI_HS             regSPI_SHADER_PGM_HI_HS;
typedef union SPI_SHADER_PGM_HI_LS             regSPI_SHADER_PGM_HI_LS;
typedef union SPI_SHADER_PGM_HI_PS             regSPI_SHADER_PGM_HI_PS;
typedef union SPI_SHADER_PGM_HI_VS             regSPI_SHADER_PGM_HI_VS;
typedef union SPI_SHADER_PGM_LO_ES             regSPI_SHADER_PGM_LO_ES;
typedef union SPI_SHADER_PGM_LO_GS             regSPI_SHADER_PGM_LO_GS;
typedef union SPI_SHADER_PGM_LO_HS             regSPI_SHADER_PGM_LO_HS;
typedef union SPI_SHADER_PGM_LO_LS             regSPI_SHADER_PGM_LO_LS;
typedef union SPI_SHADER_PGM_LO_PS             regSPI_SHADER_PGM_LO_PS;
typedef union SPI_SHADER_PGM_LO_VS             regSPI_SHADER_PGM_LO_VS;
typedef union SPI_SHADER_PGM_RSRC1_ES          regSPI_SHADER_PGM_RSRC1_ES;
typedef union SPI_SHADER_PGM_RSRC1_GS          regSPI_SHADER_PGM_RSRC1_GS;
typedef union SPI_SHADER_PGM_RSRC1_HS          regSPI_SHADER_PGM_RSRC1_HS;
typedef union SPI_SHADER_PGM_RSRC1_LS          regSPI_SHADER_PGM_RSRC1_LS;
typedef union SPI_SHADER_PGM_RSRC1_PS          regSPI_SHADER_PGM_RSRC1_PS;
typedef union SPI_SHADER_PGM_RSRC1_VS          regSPI_SHADER_PGM_RSRC1_VS;
typedef union SPI_SHADER_PGM_RSRC2_ES          regSPI_SHADER_PGM_RSRC2_ES;
typedef union SPI_SHADER_PGM_RSRC2_ES_GS__CI__VI regSPI_SHADER_PGM_RSRC2_ES_GS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC2_ES_VS__CI__VI regSPI_SHADER_PGM_RSRC2_ES_VS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC2_GS          regSPI_SHADER_PGM_RSRC2_GS;
typedef union SPI_SHADER_PGM_RSRC2_HS          regSPI_SHADER_PGM_RSRC2_HS;
typedef union SPI_SHADER_PGM_RSRC2_LS          regSPI_SHADER_PGM_RSRC2_LS;
typedef union SPI_SHADER_PGM_RSRC2_LS_ES__CI__VI regSPI_SHADER_PGM_RSRC2_LS_ES__CI__VI;
typedef union SPI_SHADER_PGM_RSRC2_LS_HS__CI__VI regSPI_SHADER_PGM_RSRC2_LS_HS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC2_LS_VS__CI__VI regSPI_SHADER_PGM_RSRC2_LS_VS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC2_PS          regSPI_SHADER_PGM_RSRC2_PS;
typedef union SPI_SHADER_PGM_RSRC2_VS          regSPI_SHADER_PGM_RSRC2_VS;
typedef union SPI_SHADER_PGM_RSRC3_ES__CI__VI  regSPI_SHADER_PGM_RSRC3_ES__CI__VI;
typedef union SPI_SHADER_PGM_RSRC3_GS__CI__VI  regSPI_SHADER_PGM_RSRC3_GS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC3_HS__CI__VI  regSPI_SHADER_PGM_RSRC3_HS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC3_LS__CI__VI  regSPI_SHADER_PGM_RSRC3_LS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC3_PS__CI__VI  regSPI_SHADER_PGM_RSRC3_PS__CI__VI;
typedef union SPI_SHADER_PGM_RSRC3_VS__CI__VI  regSPI_SHADER_PGM_RSRC3_VS__CI__VI;
typedef union SPI_SHADER_POS_FORMAT            regSPI_SHADER_POS_FORMAT;
typedef union SPI_SHADER_TBA_HI_ES             regSPI_SHADER_TBA_HI_ES;
typedef union SPI_SHADER_TBA_HI_GS             regSPI_SHADER_TBA_HI_GS;
typedef union SPI_SHADER_TBA_HI_HS             regSPI_SHADER_TBA_HI_HS;
typedef union SPI_SHADER_TBA_HI_LS             regSPI_SHADER_TBA_HI_LS;
typedef union SPI_SHADER_TBA_HI_PS             regSPI_SHADER_TBA_HI_PS;
typedef union SPI_SHADER_TBA_HI_VS             regSPI_SHADER_TBA_HI_VS;
typedef union SPI_SHADER_TBA_LO_ES             regSPI_SHADER_TBA_LO_ES;
typedef union SPI_SHADER_TBA_LO_GS             regSPI_SHADER_TBA_LO_GS;
typedef union SPI_SHADER_TBA_LO_HS             regSPI_SHADER_TBA_LO_HS;
typedef union SPI_SHADER_TBA_LO_LS             regSPI_SHADER_TBA_LO_LS;
typedef union SPI_SHADER_TBA_LO_PS             regSPI_SHADER_TBA_LO_PS;
typedef union SPI_SHADER_TBA_LO_VS             regSPI_SHADER_TBA_LO_VS;
typedef union SPI_SHADER_TMA_HI_ES             regSPI_SHADER_TMA_HI_ES;
typedef union SPI_SHADER_TMA_HI_GS             regSPI_SHADER_TMA_HI_GS;
typedef union SPI_SHADER_TMA_HI_HS             regSPI_SHADER_TMA_HI_HS;
typedef union SPI_SHADER_TMA_HI_LS             regSPI_SHADER_TMA_HI_LS;
typedef union SPI_SHADER_TMA_HI_PS             regSPI_SHADER_TMA_HI_PS;
typedef union SPI_SHADER_TMA_HI_VS             regSPI_SHADER_TMA_HI_VS;
typedef union SPI_SHADER_TMA_LO_ES             regSPI_SHADER_TMA_LO_ES;
typedef union SPI_SHADER_TMA_LO_GS             regSPI_SHADER_TMA_LO_GS;
typedef union SPI_SHADER_TMA_LO_HS             regSPI_SHADER_TMA_LO_HS;
typedef union SPI_SHADER_TMA_LO_LS             regSPI_SHADER_TMA_LO_LS;
typedef union SPI_SHADER_TMA_LO_PS             regSPI_SHADER_TMA_LO_PS;
typedef union SPI_SHADER_TMA_LO_VS             regSPI_SHADER_TMA_LO_VS;
typedef union SPI_SHADER_USER_DATA_ES_0        regSPI_SHADER_USER_DATA_ES_0;
typedef union SPI_SHADER_USER_DATA_ES_1        regSPI_SHADER_USER_DATA_ES_1;
typedef union SPI_SHADER_USER_DATA_ES_10       regSPI_SHADER_USER_DATA_ES_10;
typedef union SPI_SHADER_USER_DATA_ES_11       regSPI_SHADER_USER_DATA_ES_11;
typedef union SPI_SHADER_USER_DATA_ES_12       regSPI_SHADER_USER_DATA_ES_12;
typedef union SPI_SHADER_USER_DATA_ES_13       regSPI_SHADER_USER_DATA_ES_13;
typedef union SPI_SHADER_USER_DATA_ES_14       regSPI_SHADER_USER_DATA_ES_14;
typedef union SPI_SHADER_USER_DATA_ES_15       regSPI_SHADER_USER_DATA_ES_15;
typedef union SPI_SHADER_USER_DATA_ES_2        regSPI_SHADER_USER_DATA_ES_2;
typedef union SPI_SHADER_USER_DATA_ES_3        regSPI_SHADER_USER_DATA_ES_3;
typedef union SPI_SHADER_USER_DATA_ES_4        regSPI_SHADER_USER_DATA_ES_4;
typedef union SPI_SHADER_USER_DATA_ES_5        regSPI_SHADER_USER_DATA_ES_5;
typedef union SPI_SHADER_USER_DATA_ES_6        regSPI_SHADER_USER_DATA_ES_6;
typedef union SPI_SHADER_USER_DATA_ES_7        regSPI_SHADER_USER_DATA_ES_7;
typedef union SPI_SHADER_USER_DATA_ES_8        regSPI_SHADER_USER_DATA_ES_8;
typedef union SPI_SHADER_USER_DATA_ES_9        regSPI_SHADER_USER_DATA_ES_9;
typedef union SPI_SHADER_USER_DATA_GS_0        regSPI_SHADER_USER_DATA_GS_0;
typedef union SPI_SHADER_USER_DATA_GS_1        regSPI_SHADER_USER_DATA_GS_1;
typedef union SPI_SHADER_USER_DATA_GS_10       regSPI_SHADER_USER_DATA_GS_10;
typedef union SPI_SHADER_USER_DATA_GS_11       regSPI_SHADER_USER_DATA_GS_11;
typedef union SPI_SHADER_USER_DATA_GS_12       regSPI_SHADER_USER_DATA_GS_12;
typedef union SPI_SHADER_USER_DATA_GS_13       regSPI_SHADER_USER_DATA_GS_13;
typedef union SPI_SHADER_USER_DATA_GS_14       regSPI_SHADER_USER_DATA_GS_14;
typedef union SPI_SHADER_USER_DATA_GS_15       regSPI_SHADER_USER_DATA_GS_15;
typedef union SPI_SHADER_USER_DATA_GS_2        regSPI_SHADER_USER_DATA_GS_2;
typedef union SPI_SHADER_USER_DATA_GS_3        regSPI_SHADER_USER_DATA_GS_3;
typedef union SPI_SHADER_USER_DATA_GS_4        regSPI_SHADER_USER_DATA_GS_4;
typedef union SPI_SHADER_USER_DATA_GS_5        regSPI_SHADER_USER_DATA_GS_5;
typedef union SPI_SHADER_USER_DATA_GS_6        regSPI_SHADER_USER_DATA_GS_6;
typedef union SPI_SHADER_USER_DATA_GS_7        regSPI_SHADER_USER_DATA_GS_7;
typedef union SPI_SHADER_USER_DATA_GS_8        regSPI_SHADER_USER_DATA_GS_8;
typedef union SPI_SHADER_USER_DATA_GS_9        regSPI_SHADER_USER_DATA_GS_9;
typedef union SPI_SHADER_USER_DATA_HS_0        regSPI_SHADER_USER_DATA_HS_0;
typedef union SPI_SHADER_USER_DATA_HS_1        regSPI_SHADER_USER_DATA_HS_1;
typedef union SPI_SHADER_USER_DATA_HS_10       regSPI_SHADER_USER_DATA_HS_10;
typedef union SPI_SHADER_USER_DATA_HS_11       regSPI_SHADER_USER_DATA_HS_11;
typedef union SPI_SHADER_USER_DATA_HS_12       regSPI_SHADER_USER_DATA_HS_12;
typedef union SPI_SHADER_USER_DATA_HS_13       regSPI_SHADER_USER_DATA_HS_13;
typedef union SPI_SHADER_USER_DATA_HS_14       regSPI_SHADER_USER_DATA_HS_14;
typedef union SPI_SHADER_USER_DATA_HS_15       regSPI_SHADER_USER_DATA_HS_15;
typedef union SPI_SHADER_USER_DATA_HS_2        regSPI_SHADER_USER_DATA_HS_2;
typedef union SPI_SHADER_USER_DATA_HS_3        regSPI_SHADER_USER_DATA_HS_3;
typedef union SPI_SHADER_USER_DATA_HS_4        regSPI_SHADER_USER_DATA_HS_4;
typedef union SPI_SHADER_USER_DATA_HS_5        regSPI_SHADER_USER_DATA_HS_5;
typedef union SPI_SHADER_USER_DATA_HS_6        regSPI_SHADER_USER_DATA_HS_6;
typedef union SPI_SHADER_USER_DATA_HS_7        regSPI_SHADER_USER_DATA_HS_7;
typedef union SPI_SHADER_USER_DATA_HS_8        regSPI_SHADER_USER_DATA_HS_8;
typedef union SPI_SHADER_USER_DATA_HS_9        regSPI_SHADER_USER_DATA_HS_9;
typedef union SPI_SHADER_USER_DATA_LS_0        regSPI_SHADER_USER_DATA_LS_0;
typedef union SPI_SHADER_USER_DATA_LS_1        regSPI_SHADER_USER_DATA_LS_1;
typedef union SPI_SHADER_USER_DATA_LS_10       regSPI_SHADER_USER_DATA_LS_10;
typedef union SPI_SHADER_USER_DATA_LS_11       regSPI_SHADER_USER_DATA_LS_11;
typedef union SPI_SHADER_USER_DATA_LS_12       regSPI_SHADER_USER_DATA_LS_12;
typedef union SPI_SHADER_USER_DATA_LS_13       regSPI_SHADER_USER_DATA_LS_13;
typedef union SPI_SHADER_USER_DATA_LS_14       regSPI_SHADER_USER_DATA_LS_14;
typedef union SPI_SHADER_USER_DATA_LS_15       regSPI_SHADER_USER_DATA_LS_15;
typedef union SPI_SHADER_USER_DATA_LS_2        regSPI_SHADER_USER_DATA_LS_2;
typedef union SPI_SHADER_USER_DATA_LS_3        regSPI_SHADER_USER_DATA_LS_3;
typedef union SPI_SHADER_USER_DATA_LS_4        regSPI_SHADER_USER_DATA_LS_4;
typedef union SPI_SHADER_USER_DATA_LS_5        regSPI_SHADER_USER_DATA_LS_5;
typedef union SPI_SHADER_USER_DATA_LS_6        regSPI_SHADER_USER_DATA_LS_6;
typedef union SPI_SHADER_USER_DATA_LS_7        regSPI_SHADER_USER_DATA_LS_7;
typedef union SPI_SHADER_USER_DATA_LS_8        regSPI_SHADER_USER_DATA_LS_8;
typedef union SPI_SHADER_USER_DATA_LS_9        regSPI_SHADER_USER_DATA_LS_9;
typedef union SPI_SHADER_USER_DATA_PS_0        regSPI_SHADER_USER_DATA_PS_0;
typedef union SPI_SHADER_USER_DATA_PS_1        regSPI_SHADER_USER_DATA_PS_1;
typedef union SPI_SHADER_USER_DATA_PS_10       regSPI_SHADER_USER_DATA_PS_10;
typedef union SPI_SHADER_USER_DATA_PS_11       regSPI_SHADER_USER_DATA_PS_11;
typedef union SPI_SHADER_USER_DATA_PS_12       regSPI_SHADER_USER_DATA_PS_12;
typedef union SPI_SHADER_USER_DATA_PS_13       regSPI_SHADER_USER_DATA_PS_13;
typedef union SPI_SHADER_USER_DATA_PS_14       regSPI_SHADER_USER_DATA_PS_14;
typedef union SPI_SHADER_USER_DATA_PS_15       regSPI_SHADER_USER_DATA_PS_15;
typedef union SPI_SHADER_USER_DATA_PS_2        regSPI_SHADER_USER_DATA_PS_2;
typedef union SPI_SHADER_USER_DATA_PS_3        regSPI_SHADER_USER_DATA_PS_3;
typedef union SPI_SHADER_USER_DATA_PS_4        regSPI_SHADER_USER_DATA_PS_4;
typedef union SPI_SHADER_USER_DATA_PS_5        regSPI_SHADER_USER_DATA_PS_5;
typedef union SPI_SHADER_USER_DATA_PS_6        regSPI_SHADER_USER_DATA_PS_6;
typedef union SPI_SHADER_USER_DATA_PS_7        regSPI_SHADER_USER_DATA_PS_7;
typedef union SPI_SHADER_USER_DATA_PS_8        regSPI_SHADER_USER_DATA_PS_8;
typedef union SPI_SHADER_USER_DATA_PS_9        regSPI_SHADER_USER_DATA_PS_9;
typedef union SPI_SHADER_USER_DATA_VS_0        regSPI_SHADER_USER_DATA_VS_0;
typedef union SPI_SHADER_USER_DATA_VS_1        regSPI_SHADER_USER_DATA_VS_1;
typedef union SPI_SHADER_USER_DATA_VS_10       regSPI_SHADER_USER_DATA_VS_10;
typedef union SPI_SHADER_USER_DATA_VS_11       regSPI_SHADER_USER_DATA_VS_11;
typedef union SPI_SHADER_USER_DATA_VS_12       regSPI_SHADER_USER_DATA_VS_12;
typedef union SPI_SHADER_USER_DATA_VS_13       regSPI_SHADER_USER_DATA_VS_13;
typedef union SPI_SHADER_USER_DATA_VS_14       regSPI_SHADER_USER_DATA_VS_14;
typedef union SPI_SHADER_USER_DATA_VS_15       regSPI_SHADER_USER_DATA_VS_15;
typedef union SPI_SHADER_USER_DATA_VS_2        regSPI_SHADER_USER_DATA_VS_2;
typedef union SPI_SHADER_USER_DATA_VS_3        regSPI_SHADER_USER_DATA_VS_3;
typedef union SPI_SHADER_USER_DATA_VS_4        regSPI_SHADER_USER_DATA_VS_4;
typedef union SPI_SHADER_USER_DATA_VS_5        regSPI_SHADER_USER_DATA_VS_5;
typedef union SPI_SHADER_USER_DATA_VS_6        regSPI_SHADER_USER_DATA_VS_6;
typedef union SPI_SHADER_USER_DATA_VS_7        regSPI_SHADER_USER_DATA_VS_7;
typedef union SPI_SHADER_USER_DATA_VS_8        regSPI_SHADER_USER_DATA_VS_8;
typedef union SPI_SHADER_USER_DATA_VS_9        regSPI_SHADER_USER_DATA_VS_9;
typedef union SPI_SHADER_Z_FORMAT              regSPI_SHADER_Z_FORMAT;
typedef union SPI_SLAVE_DEBUG_BUSY             regSPI_SLAVE_DEBUG_BUSY;
typedef union SPI_STATIC_THREAD_MGMT_3__SI     regSPI_STATIC_THREAD_MGMT_3__SI;
typedef union SPI_SX_EXPORT_BUFFER_SIZES       regSPI_SX_EXPORT_BUFFER_SIZES;
typedef union SPI_SX_SCOREBOARD_BUFFER_SIZES   regSPI_SX_SCOREBOARD_BUFFER_SIZES;
typedef union SPI_TMPRING_SIZE                 regSPI_TMPRING_SIZE;
typedef union SPI_VS_OUT_CONFIG                regSPI_VS_OUT_CONFIG;
typedef union SPI_WCL_PIPE_PERCENT_CS0__CI__VI regSPI_WCL_PIPE_PERCENT_CS0__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS1__CI__VI regSPI_WCL_PIPE_PERCENT_CS1__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS2__CI__VI regSPI_WCL_PIPE_PERCENT_CS2__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS3__CI__VI regSPI_WCL_PIPE_PERCENT_CS3__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS4__CI__VI regSPI_WCL_PIPE_PERCENT_CS4__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS5__CI__VI regSPI_WCL_PIPE_PERCENT_CS5__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS6__CI__VI regSPI_WCL_PIPE_PERCENT_CS6__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_CS7__CI__VI regSPI_WCL_PIPE_PERCENT_CS7__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_GFX__CI__VI regSPI_WCL_PIPE_PERCENT_GFX__CI__VI;
typedef union SPI_WCL_PIPE_PERCENT_HP3D__CI__VI regSPI_WCL_PIPE_PERCENT_HP3D__CI__VI;
typedef union SPI_WF_LIFETIME_CNTL__CI__VI     regSPI_WF_LIFETIME_CNTL__CI__VI;
typedef union SPI_WF_LIFETIME_DEBUG__CI__VI    regSPI_WF_LIFETIME_DEBUG__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_0__CI__VI  regSPI_WF_LIFETIME_LIMIT_0__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_1__CI__VI  regSPI_WF_LIFETIME_LIMIT_1__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_2__CI__VI  regSPI_WF_LIFETIME_LIMIT_2__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_3__CI__VI  regSPI_WF_LIFETIME_LIMIT_3__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_4__CI__VI  regSPI_WF_LIFETIME_LIMIT_4__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_5__CI__VI  regSPI_WF_LIFETIME_LIMIT_5__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_6__CI__VI  regSPI_WF_LIFETIME_LIMIT_6__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_7__CI__VI  regSPI_WF_LIFETIME_LIMIT_7__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_8__CI__VI  regSPI_WF_LIFETIME_LIMIT_8__CI__VI;
typedef union SPI_WF_LIFETIME_LIMIT_9__CI__VI  regSPI_WF_LIFETIME_LIMIT_9__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_0__CI__VI regSPI_WF_LIFETIME_STATUS_0__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_10__CI__VI regSPI_WF_LIFETIME_STATUS_10__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_11__CI__VI regSPI_WF_LIFETIME_STATUS_11__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_12__CI__VI regSPI_WF_LIFETIME_STATUS_12__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_13__CI__VI regSPI_WF_LIFETIME_STATUS_13__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_14__CI__VI regSPI_WF_LIFETIME_STATUS_14__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_15__CI__VI regSPI_WF_LIFETIME_STATUS_15__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_16__CI__VI regSPI_WF_LIFETIME_STATUS_16__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_17__CI__VI regSPI_WF_LIFETIME_STATUS_17__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_18__CI__VI regSPI_WF_LIFETIME_STATUS_18__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_19__CI__VI regSPI_WF_LIFETIME_STATUS_19__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_1__CI__VI regSPI_WF_LIFETIME_STATUS_1__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_20__CI__VI regSPI_WF_LIFETIME_STATUS_20__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_2__CI__VI regSPI_WF_LIFETIME_STATUS_2__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_3__CI__VI regSPI_WF_LIFETIME_STATUS_3__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_4__CI__VI regSPI_WF_LIFETIME_STATUS_4__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_5__CI__VI regSPI_WF_LIFETIME_STATUS_5__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_6__CI__VI regSPI_WF_LIFETIME_STATUS_6__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_7__CI__VI regSPI_WF_LIFETIME_STATUS_7__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_8__CI__VI regSPI_WF_LIFETIME_STATUS_8__CI__VI;
typedef union SPI_WF_LIFETIME_STATUS_9__CI__VI regSPI_WF_LIFETIME_STATUS_9__CI__VI;
typedef union SPLL_CNTL_MODE__CI__VI           regSPLL_CNTL_MODE__CI__VI;
typedef union SPLL_CNTL_MODE__SI               regSPLL_CNTL_MODE__SI;
typedef union SPMI_C6_STATE_0__CI__VI          regSPMI_C6_STATE_0__CI__VI;
typedef union SPMI_C6_STATE_1__CI              regSPMI_C6_STATE_1__CI;
typedef union SPMI_FSM_BUSY_0__CI__VI          regSPMI_FSM_BUSY_0__CI__VI;
typedef union SPMI_FSM_BUSY_1__CI              regSPMI_FSM_BUSY_1__CI;
typedef union SPMI_FSM_READ_TRIGGER_0__CI__VI  regSPMI_FSM_READ_TRIGGER_0__CI__VI;
typedef union SPMI_FSM_READ_TRIGGER_1__CI      regSPMI_FSM_READ_TRIGGER_1__CI;
typedef union SPMI_FSM_RESET_TRIGGER_0__CI__VI regSPMI_FSM_RESET_TRIGGER_0__CI__VI;
typedef union SPMI_FSM_RESET_TRIGGER_1__CI     regSPMI_FSM_RESET_TRIGGER_1__CI;
typedef union SPMI_FSM_WRITE_TRIGGER_0__CI__VI regSPMI_FSM_WRITE_TRIGGER_0__CI__VI;
typedef union SPMI_FSM_WRITE_TRIGGER_1__CI     regSPMI_FSM_WRITE_TRIGGER_1__CI;
typedef union SPMI_JTAG_OVER_0__CI__VI         regSPMI_JTAG_OVER_0__CI__VI;
typedef union SPMI_JTAG_OVER_1__CI             regSPMI_JTAG_OVER_1__CI;
typedef union SPMI_PATH_0__CI__VI              regSPMI_PATH_0__CI__VI;
typedef union SPMI_PATH_1__CI                  regSPMI_PATH_1__CI;
typedef union SPMI_RESET__CI                   regSPMI_RESET__CI;
typedef union SPMI_RESET__VI                   regSPMI_RESET__VI;
typedef union SPMI_SRAM_ADDRESS__CI__VI        regSPMI_SRAM_ADDRESS__CI__VI;
typedef union SPMI_SRAM_DATA__CI__VI           regSPMI_SRAM_DATA__CI__VI;
typedef union SQC_CACHES__SI__CI               regSQC_CACHES__SI__CI;
typedef union SQC_CACHES__VI                   regSQC_CACHES__VI;
typedef union SQC_CONFIG                       regSQC_CONFIG;
typedef union SQC_POLICY__CI                   regSQC_POLICY__CI;
typedef union SQC_SECDED_CNT__SI__CI           regSQC_SECDED_CNT__SI__CI;
typedef union SQC_VOLATILE__CI                 regSQC_VOLATILE__CI;
typedef union SQ_ALU_CLK_CTRL                  regSQ_ALU_CLK_CTRL;
typedef union SQ_BUF_RSRC_WORD0                regSQ_BUF_RSRC_WORD0;
typedef union SQ_BUF_RSRC_WORD1                regSQ_BUF_RSRC_WORD1;
typedef union SQ_BUF_RSRC_WORD2                regSQ_BUF_RSRC_WORD2;
typedef union SQ_BUF_RSRC_WORD3                regSQ_BUF_RSRC_WORD3;
typedef union SQ_CMD_TIMESTAMP__CI__VI         regSQ_CMD_TIMESTAMP__CI__VI;
typedef union SQ_CMD__CI                       regSQ_CMD__CI;
typedef union SQ_CMD__VI                       regSQ_CMD__VI;
typedef union SQ_CONFIG__SI__CI                regSQ_CONFIG__SI__CI;
typedef union SQ_CONFIG__VI                    regSQ_CONFIG__VI;
typedef union SQ_DEBUG_CTRL_LOCAL              regSQ_DEBUG_CTRL_LOCAL;
typedef union SQ_DEBUG_STS_GLOBAL              regSQ_DEBUG_STS_GLOBAL;
typedef union SQ_DEBUG_STS_GLOBAL2__CI__VI     regSQ_DEBUG_STS_GLOBAL2__CI__VI;
typedef union SQ_DEBUG_STS_GLOBAL3__CI__VI     regSQ_DEBUG_STS_GLOBAL3__CI__VI;
typedef union SQ_DEBUG_STS_LOCAL               regSQ_DEBUG_STS_LOCAL;
typedef union SQ_DED_CNT__SI__CI               regSQ_DED_CNT__SI__CI;
typedef union SQ_DED_INFO__SI__CI              regSQ_DED_INFO__SI__CI;
typedef union SQ_DS_0__SI__CI                  regSQ_DS_0__SI__CI;
typedef union SQ_DS_0__VI                      regSQ_DS_0__VI;
typedef union SQ_DS_1                          regSQ_DS_1;
typedef union SQ_EXP_0                         regSQ_EXP_0;
typedef union SQ_EXP_1                         regSQ_EXP_1;
typedef union SQ_FIFO_SIZES                    regSQ_FIFO_SIZES;
typedef union SQ_FLAT_0__CI__VI                regSQ_FLAT_0__CI__VI;
typedef union SQ_FLAT_1__CI__VI                regSQ_FLAT_1__CI__VI;
typedef union SQ_FLAT_SCRATCH_WORD0__CI__VI    regSQ_FLAT_SCRATCH_WORD0__CI__VI;
typedef union SQ_FLAT_SCRATCH_WORD1__CI__VI    regSQ_FLAT_SCRATCH_WORD1__CI__VI;
typedef union SQ_HV_VMID_CTRL__CI__VI          regSQ_HV_VMID_CTRL__CI__VI;
typedef union SQ_IMG_RSRC_WORD0                regSQ_IMG_RSRC_WORD0;
typedef union SQ_IMG_RSRC_WORD1                regSQ_IMG_RSRC_WORD1;
typedef union SQ_IMG_RSRC_WORD2                regSQ_IMG_RSRC_WORD2;
typedef union SQ_IMG_RSRC_WORD3                regSQ_IMG_RSRC_WORD3;
typedef union SQ_IMG_RSRC_WORD4                regSQ_IMG_RSRC_WORD4;
typedef union SQ_IMG_RSRC_WORD5                regSQ_IMG_RSRC_WORD5;
typedef union SQ_IMG_RSRC_WORD6                regSQ_IMG_RSRC_WORD6;
typedef union SQ_IMG_RSRC_WORD7                regSQ_IMG_RSRC_WORD7;
typedef union SQ_IMG_SAMP_WORD0                regSQ_IMG_SAMP_WORD0;
typedef union SQ_IMG_SAMP_WORD1                regSQ_IMG_SAMP_WORD1;
typedef union SQ_IMG_SAMP_WORD2                regSQ_IMG_SAMP_WORD2;
typedef union SQ_IMG_SAMP_WORD3                regSQ_IMG_SAMP_WORD3;
typedef union SQ_IND_DATA                      regSQ_IND_DATA;
typedef union SQ_IND_INDEX                     regSQ_IND_INDEX;
typedef union SQ_INST                          regSQ_INST;
typedef union SQ_INTERRUPT_AUTO_MASK__CI__VI   regSQ_INTERRUPT_AUTO_MASK__CI__VI;
typedef union SQ_INTERRUPT_MSG_CTRL__CI__VI    regSQ_INTERRUPT_MSG_CTRL__CI__VI;
typedef union SQ_INTERRUPT_WORD_AUTO__CI__VI   regSQ_INTERRUPT_WORD_AUTO__CI__VI;
typedef union SQ_INTERRUPT_WORD_AUTO__SI       regSQ_INTERRUPT_WORD_AUTO__SI;
typedef union SQ_INTERRUPT_WORD_CMN__CI__VI    regSQ_INTERRUPT_WORD_CMN__CI__VI;
typedef union SQ_INTERRUPT_WORD_CMN__SI        regSQ_INTERRUPT_WORD_CMN__SI;
typedef union SQ_INTERRUPT_WORD_WAVE__CI__VI   regSQ_INTERRUPT_WORD_WAVE__CI__VI;
typedef union SQ_INTERRUPT_WORD_WAVE__SI       regSQ_INTERRUPT_WORD_WAVE__SI;
typedef union SQ_LB_CTR_CTRL                   regSQ_LB_CTR_CTRL;
typedef union SQ_LB_DATA_ALU_CYCLES            regSQ_LB_DATA_ALU_CYCLES;
typedef union SQ_LB_DATA_ALU_STALLS            regSQ_LB_DATA_ALU_STALLS;
typedef union SQ_LB_DATA_TEX_CYCLES            regSQ_LB_DATA_TEX_CYCLES;
typedef union SQ_LB_DATA_TEX_STALLS            regSQ_LB_DATA_TEX_STALLS;
typedef union SQ_LDS_CLK_CTRL__CI__VI          regSQ_LDS_CLK_CTRL__CI__VI;
typedef union SQ_MIMG_0                        regSQ_MIMG_0;
typedef union SQ_MIMG_1                        regSQ_MIMG_1;
typedef union SQ_MTBUF_0__SI__CI               regSQ_MTBUF_0__SI__CI;
typedef union SQ_MTBUF_0__VI                   regSQ_MTBUF_0__VI;
typedef union SQ_MTBUF_1                       regSQ_MTBUF_1;
typedef union SQ_MUBUF_0                       regSQ_MUBUF_0;
typedef union SQ_MUBUF_1__SI__CI               regSQ_MUBUF_1__SI__CI;
typedef union SQ_MUBUF_1__VI                   regSQ_MUBUF_1__VI;
typedef union SQ_PERFCOUNTER0_HI               regSQ_PERFCOUNTER0_HI;
typedef union SQ_PERFCOUNTER0_LO               regSQ_PERFCOUNTER0_LO;
typedef union SQ_PERFCOUNTER0_SELECT__CI__VI   regSQ_PERFCOUNTER0_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER0_SELECT__SI       regSQ_PERFCOUNTER0_SELECT__SI;
typedef union SQ_PERFCOUNTER10_HI              regSQ_PERFCOUNTER10_HI;
typedef union SQ_PERFCOUNTER10_LO              regSQ_PERFCOUNTER10_LO;
typedef union SQ_PERFCOUNTER10_SELECT__CI__VI  regSQ_PERFCOUNTER10_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER10_SELECT__SI      regSQ_PERFCOUNTER10_SELECT__SI;
typedef union SQ_PERFCOUNTER11_HI              regSQ_PERFCOUNTER11_HI;
typedef union SQ_PERFCOUNTER11_LO              regSQ_PERFCOUNTER11_LO;
typedef union SQ_PERFCOUNTER11_SELECT__CI__VI  regSQ_PERFCOUNTER11_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER11_SELECT__SI      regSQ_PERFCOUNTER11_SELECT__SI;
typedef union SQ_PERFCOUNTER12_HI              regSQ_PERFCOUNTER12_HI;
typedef union SQ_PERFCOUNTER12_LO              regSQ_PERFCOUNTER12_LO;
typedef union SQ_PERFCOUNTER12_SELECT__CI__VI  regSQ_PERFCOUNTER12_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER12_SELECT__SI      regSQ_PERFCOUNTER12_SELECT__SI;
typedef union SQ_PERFCOUNTER13_HI              regSQ_PERFCOUNTER13_HI;
typedef union SQ_PERFCOUNTER13_LO              regSQ_PERFCOUNTER13_LO;
typedef union SQ_PERFCOUNTER13_SELECT__CI__VI  regSQ_PERFCOUNTER13_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER13_SELECT__SI      regSQ_PERFCOUNTER13_SELECT__SI;
typedef union SQ_PERFCOUNTER14_HI              regSQ_PERFCOUNTER14_HI;
typedef union SQ_PERFCOUNTER14_LO              regSQ_PERFCOUNTER14_LO;
typedef union SQ_PERFCOUNTER14_SELECT__CI__VI  regSQ_PERFCOUNTER14_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER14_SELECT__SI      regSQ_PERFCOUNTER14_SELECT__SI;
typedef union SQ_PERFCOUNTER15_HI              regSQ_PERFCOUNTER15_HI;
typedef union SQ_PERFCOUNTER15_LO              regSQ_PERFCOUNTER15_LO;
typedef union SQ_PERFCOUNTER15_SELECT__CI__VI  regSQ_PERFCOUNTER15_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER15_SELECT__SI      regSQ_PERFCOUNTER15_SELECT__SI;
typedef union SQ_PERFCOUNTER1_HI               regSQ_PERFCOUNTER1_HI;
typedef union SQ_PERFCOUNTER1_LO               regSQ_PERFCOUNTER1_LO;
typedef union SQ_PERFCOUNTER1_SELECT__CI__VI   regSQ_PERFCOUNTER1_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER1_SELECT__SI       regSQ_PERFCOUNTER1_SELECT__SI;
typedef union SQ_PERFCOUNTER2_HI               regSQ_PERFCOUNTER2_HI;
typedef union SQ_PERFCOUNTER2_LO               regSQ_PERFCOUNTER2_LO;
typedef union SQ_PERFCOUNTER2_SELECT__CI__VI   regSQ_PERFCOUNTER2_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER2_SELECT__SI       regSQ_PERFCOUNTER2_SELECT__SI;
typedef union SQ_PERFCOUNTER3_HI               regSQ_PERFCOUNTER3_HI;
typedef union SQ_PERFCOUNTER3_LO               regSQ_PERFCOUNTER3_LO;
typedef union SQ_PERFCOUNTER3_SELECT__CI__VI   regSQ_PERFCOUNTER3_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER3_SELECT__SI       regSQ_PERFCOUNTER3_SELECT__SI;
typedef union SQ_PERFCOUNTER4_HI               regSQ_PERFCOUNTER4_HI;
typedef union SQ_PERFCOUNTER4_LO               regSQ_PERFCOUNTER4_LO;
typedef union SQ_PERFCOUNTER4_SELECT__CI__VI   regSQ_PERFCOUNTER4_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER4_SELECT__SI       regSQ_PERFCOUNTER4_SELECT__SI;
typedef union SQ_PERFCOUNTER5_HI               regSQ_PERFCOUNTER5_HI;
typedef union SQ_PERFCOUNTER5_LO               regSQ_PERFCOUNTER5_LO;
typedef union SQ_PERFCOUNTER5_SELECT__CI__VI   regSQ_PERFCOUNTER5_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER5_SELECT__SI       regSQ_PERFCOUNTER5_SELECT__SI;
typedef union SQ_PERFCOUNTER6_HI               regSQ_PERFCOUNTER6_HI;
typedef union SQ_PERFCOUNTER6_LO               regSQ_PERFCOUNTER6_LO;
typedef union SQ_PERFCOUNTER6_SELECT__CI__VI   regSQ_PERFCOUNTER6_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER6_SELECT__SI       regSQ_PERFCOUNTER6_SELECT__SI;
typedef union SQ_PERFCOUNTER7_HI               regSQ_PERFCOUNTER7_HI;
typedef union SQ_PERFCOUNTER7_LO               regSQ_PERFCOUNTER7_LO;
typedef union SQ_PERFCOUNTER7_SELECT__CI__VI   regSQ_PERFCOUNTER7_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER7_SELECT__SI       regSQ_PERFCOUNTER7_SELECT__SI;
typedef union SQ_PERFCOUNTER8_HI               regSQ_PERFCOUNTER8_HI;
typedef union SQ_PERFCOUNTER8_LO               regSQ_PERFCOUNTER8_LO;
typedef union SQ_PERFCOUNTER8_SELECT__CI__VI   regSQ_PERFCOUNTER8_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER8_SELECT__SI       regSQ_PERFCOUNTER8_SELECT__SI;
typedef union SQ_PERFCOUNTER9_HI               regSQ_PERFCOUNTER9_HI;
typedef union SQ_PERFCOUNTER9_LO               regSQ_PERFCOUNTER9_LO;
typedef union SQ_PERFCOUNTER9_SELECT__CI__VI   regSQ_PERFCOUNTER9_SELECT__CI__VI;
typedef union SQ_PERFCOUNTER9_SELECT__SI       regSQ_PERFCOUNTER9_SELECT__SI;
typedef union SQ_PERFCOUNTER_CTRL              regSQ_PERFCOUNTER_CTRL;
typedef union SQ_PERFCOUNTER_CTRL2__CI__VI     regSQ_PERFCOUNTER_CTRL2__CI__VI;
typedef union SQ_PERFCOUNTER_MASK__CI__VI      regSQ_PERFCOUNTER_MASK__CI__VI;
typedef union SQ_POWER_THROTTLE                regSQ_POWER_THROTTLE;
typedef union SQ_POWER_THROTTLE2               regSQ_POWER_THROTTLE2;
typedef union SQ_RANDOM_WAVE_PRI               regSQ_RANDOM_WAVE_PRI;
typedef union SQ_REG_CREDITS                   regSQ_REG_CREDITS;
typedef union SQ_REG_TIMESTAMP__CI__VI         regSQ_REG_TIMESTAMP__CI__VI;
typedef union SQ_SEC_CNT__SI__CI               regSQ_SEC_CNT__SI__CI;
typedef union SQ_SMRD__SI__CI                  regSQ_SMRD__SI__CI;
typedef union SQ_SOP1                          regSQ_SOP1;
typedef union SQ_SOP2                          regSQ_SOP2;
typedef union SQ_SOPC                          regSQ_SOPC;
typedef union SQ_SOPK                          regSQ_SOPK;
typedef union SQ_SOPP                          regSQ_SOPP;
typedef union SQ_TEX_CLK_CTRL                  regSQ_TEX_CLK_CTRL;
typedef union SQ_THREAD_TRACE_BASE             regSQ_THREAD_TRACE_BASE;
typedef union SQ_THREAD_TRACE_BASE2__CI__VI    regSQ_THREAD_TRACE_BASE2__CI__VI;
typedef union SQ_THREAD_TRACE_CNTR             regSQ_THREAD_TRACE_CNTR;
typedef union SQ_THREAD_TRACE_CTRL             regSQ_THREAD_TRACE_CTRL;
typedef union SQ_THREAD_TRACE_HIWATER          regSQ_THREAD_TRACE_HIWATER;
typedef union SQ_THREAD_TRACE_MASK             regSQ_THREAD_TRACE_MASK;
typedef union SQ_THREAD_TRACE_MODE             regSQ_THREAD_TRACE_MODE;
typedef union SQ_THREAD_TRACE_PERF_MASK        regSQ_THREAD_TRACE_PERF_MASK;
typedef union SQ_THREAD_TRACE_SIZE             regSQ_THREAD_TRACE_SIZE;
typedef union SQ_THREAD_TRACE_STATUS           regSQ_THREAD_TRACE_STATUS;
typedef union SQ_THREAD_TRACE_TOKEN_MASK       regSQ_THREAD_TRACE_TOKEN_MASK;
typedef union SQ_THREAD_TRACE_TOKEN_MASK2__CI  regSQ_THREAD_TRACE_TOKEN_MASK2__CI;
typedef union SQ_THREAD_TRACE_TOKEN_MASK2__VI  regSQ_THREAD_TRACE_TOKEN_MASK2__VI;
typedef union SQ_THREAD_TRACE_USERDATA_0       regSQ_THREAD_TRACE_USERDATA_0;
typedef union SQ_THREAD_TRACE_USERDATA_1       regSQ_THREAD_TRACE_USERDATA_1;
typedef union SQ_THREAD_TRACE_USERDATA_2       regSQ_THREAD_TRACE_USERDATA_2;
typedef union SQ_THREAD_TRACE_USERDATA_3       regSQ_THREAD_TRACE_USERDATA_3;
typedef union SQ_THREAD_TRACE_WORD_CMN         regSQ_THREAD_TRACE_WORD_CMN;
typedef union SQ_THREAD_TRACE_WORD_EVENT       regSQ_THREAD_TRACE_WORD_EVENT;
typedef union SQ_THREAD_TRACE_WORD_INST__SI__CI regSQ_THREAD_TRACE_WORD_INST__SI__CI;
typedef union SQ_THREAD_TRACE_WORD_INST__VI    regSQ_THREAD_TRACE_WORD_INST__VI;
typedef union SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2;
typedef union SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2;
typedef union SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2;
typedef union SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2;
typedef union SQ_THREAD_TRACE_WORD_ISSUE       regSQ_THREAD_TRACE_WORD_ISSUE;
typedef union SQ_THREAD_TRACE_WORD_MISC__CI__VI regSQ_THREAD_TRACE_WORD_MISC__CI__VI;
typedef union SQ_THREAD_TRACE_WORD_MISC__SI    regSQ_THREAD_TRACE_WORD_MISC__SI;
typedef union SQ_THREAD_TRACE_WORD_PERF_1_OF_2 regSQ_THREAD_TRACE_WORD_PERF_1_OF_2;
typedef union SQ_THREAD_TRACE_WORD_PERF_2_OF_2 regSQ_THREAD_TRACE_WORD_PERF_2_OF_2;
typedef union SQ_THREAD_TRACE_WORD_REG_1_OF_2__CI__VI regSQ_THREAD_TRACE_WORD_REG_1_OF_2__CI__VI;
typedef union SQ_THREAD_TRACE_WORD_REG_1_OF_2__SI regSQ_THREAD_TRACE_WORD_REG_1_OF_2__SI;
typedef union SQ_THREAD_TRACE_WORD_REG_2_OF_2  regSQ_THREAD_TRACE_WORD_REG_2_OF_2;
typedef union SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__CI__VI;
typedef union SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__CI__VI;
typedef union SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2;
typedef union SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2;
typedef union SQ_THREAD_TRACE_WORD_TIME__SI    regSQ_THREAD_TRACE_WORD_TIME__SI;
typedef union SQ_THREAD_TRACE_WORD_WAVE        regSQ_THREAD_TRACE_WORD_WAVE;
typedef union SQ_THREAD_TRACE_WORD_WAVE_START  regSQ_THREAD_TRACE_WORD_WAVE_START;
typedef union SQ_THREAD_TRACE_WPTR             regSQ_THREAD_TRACE_WPTR;
typedef union SQ_TIME_HI                       regSQ_TIME_HI;
typedef union SQ_TIME_LO                       regSQ_TIME_LO;
typedef union SQ_VINTRP                        regSQ_VINTRP;
typedef union SQ_VOP1                          regSQ_VOP1;
typedef union SQ_VOP2                          regSQ_VOP2;
typedef union SQ_VOP3_0__SI__CI                regSQ_VOP3_0__SI__CI;
typedef union SQ_VOP3_0__VI                    regSQ_VOP3_0__VI;
typedef union SQ_VOP3_0_SDST_ENC__SI__CI       regSQ_VOP3_0_SDST_ENC__SI__CI;
typedef union SQ_VOP3_0_SDST_ENC__VI           regSQ_VOP3_0_SDST_ENC__VI;
typedef union SQ_VOP3_1                        regSQ_VOP3_1;
typedef union SQ_VOPC                          regSQ_VOPC;
typedef union SQ_WAVE_EXEC_HI                  regSQ_WAVE_EXEC_HI;
typedef union SQ_WAVE_EXEC_LO                  regSQ_WAVE_EXEC_LO;
typedef union SQ_WAVE_GPR_ALLOC                regSQ_WAVE_GPR_ALLOC;
typedef union SQ_WAVE_HW_ID__CI__VI            regSQ_WAVE_HW_ID__CI__VI;
typedef union SQ_WAVE_HW_ID__SI                regSQ_WAVE_HW_ID__SI;
typedef union SQ_WAVE_IB_DBG0__SI__CI          regSQ_WAVE_IB_DBG0__SI__CI;
typedef union SQ_WAVE_IB_DBG0__VI              regSQ_WAVE_IB_DBG0__VI;
typedef union SQ_WAVE_IB_STS__CI__VI           regSQ_WAVE_IB_STS__CI__VI;
typedef union SQ_WAVE_IB_STS__SI               regSQ_WAVE_IB_STS__SI;
typedef union SQ_WAVE_INST_DW0                 regSQ_WAVE_INST_DW0;
typedef union SQ_WAVE_INST_DW1                 regSQ_WAVE_INST_DW1;
typedef union SQ_WAVE_LDS_ALLOC                regSQ_WAVE_LDS_ALLOC;
typedef union SQ_WAVE_M0                       regSQ_WAVE_M0;
typedef union SQ_WAVE_MODE                     regSQ_WAVE_MODE;
typedef union SQ_WAVE_PC_HI                    regSQ_WAVE_PC_HI;
typedef union SQ_WAVE_PC_LO                    regSQ_WAVE_PC_LO;
typedef union SQ_WAVE_STATUS__SI__CI           regSQ_WAVE_STATUS__SI__CI;
typedef union SQ_WAVE_STATUS__VI               regSQ_WAVE_STATUS__VI;
typedef union SQ_WAVE_TBA_HI                   regSQ_WAVE_TBA_HI;
typedef union SQ_WAVE_TBA_LO                   regSQ_WAVE_TBA_LO;
typedef union SQ_WAVE_TMA_HI                   regSQ_WAVE_TMA_HI;
typedef union SQ_WAVE_TMA_LO                   regSQ_WAVE_TMA_LO;
typedef union SQ_WAVE_TRAPSTS                  regSQ_WAVE_TRAPSTS;
typedef union SQ_WAVE_TTMP0                    regSQ_WAVE_TTMP0;
typedef union SQ_WAVE_TTMP1                    regSQ_WAVE_TTMP1;
typedef union SQ_WAVE_TTMP10                   regSQ_WAVE_TTMP10;
typedef union SQ_WAVE_TTMP11                   regSQ_WAVE_TTMP11;
typedef union SQ_WAVE_TTMP2                    regSQ_WAVE_TTMP2;
typedef union SQ_WAVE_TTMP3                    regSQ_WAVE_TTMP3;
typedef union SQ_WAVE_TTMP4                    regSQ_WAVE_TTMP4;
typedef union SQ_WAVE_TTMP5                    regSQ_WAVE_TTMP5;
typedef union SQ_WAVE_TTMP6                    regSQ_WAVE_TTMP6;
typedef union SQ_WAVE_TTMP7                    regSQ_WAVE_TTMP7;
typedef union SQ_WAVE_TTMP8                    regSQ_WAVE_TTMP8;
typedef union SQ_WAVE_TTMP9                    regSQ_WAVE_TTMP9;
typedef union SRBM_CAM_DATA                    regSRBM_CAM_DATA;
typedef union SRBM_CAM_INDEX                   regSRBM_CAM_INDEX;
typedef union SRBM_CHIP_REVISION               regSRBM_CHIP_REVISION;
typedef union SRBM_CNTL                        regSRBM_CNTL;
typedef union SRBM_DEBUG_CNTL                  regSRBM_DEBUG_CNTL;
typedef union SRBM_DEBUG_DATA                  regSRBM_DEBUG_DATA;
typedef union SRBM_DEBUG_SNAPSHOT__SI__CI      regSRBM_DEBUG_SNAPSHOT__SI__CI;
typedef union SRBM_DEBUG_SNAPSHOT__VI          regSRBM_DEBUG_SNAPSHOT__VI;
typedef union SRBM_DEBUG__CI__VI               regSRBM_DEBUG__CI__VI;
typedef union SRBM_DEBUG__SI                   regSRBM_DEBUG__SI;
typedef union SRBM_GFX_CNTL__CI__VI            regSRBM_GFX_CNTL__CI__VI;
typedef union SRBM_GFX_CNTL__SI                regSRBM_GFX_CNTL__SI;
typedef union SRBM_INT_ACK                     regSRBM_INT_ACK;
typedef union SRBM_INT_CNTL                    regSRBM_INT_CNTL;
typedef union SRBM_INT_STATUS                  regSRBM_INT_STATUS;
typedef union SRBM_MC_CLKEN_CNTL__CI__VI       regSRBM_MC_CLKEN_CNTL__CI__VI;
typedef union SRBM_PERFCOUNTER0_HI             regSRBM_PERFCOUNTER0_HI;
typedef union SRBM_PERFCOUNTER0_LO             regSRBM_PERFCOUNTER0_LO;
typedef union SRBM_PERFCOUNTER0_SELECT         regSRBM_PERFCOUNTER0_SELECT;
typedef union SRBM_PERFCOUNTER1_HI             regSRBM_PERFCOUNTER1_HI;
typedef union SRBM_PERFCOUNTER1_LO             regSRBM_PERFCOUNTER1_LO;
typedef union SRBM_PERFCOUNTER1_SELECT         regSRBM_PERFCOUNTER1_SELECT;
typedef union SRBM_PERFMON_CNTL                regSRBM_PERFMON_CNTL;
typedef union SRBM_READ_ERROR__CI              regSRBM_READ_ERROR__CI;
typedef union SRBM_READ_ERROR__VI              regSRBM_READ_ERROR__VI;
typedef union SRBM_READ_ERROR__SI              regSRBM_READ_ERROR__SI;
typedef union SRBM_SAM_CLKEN_CNTL__CI__VI      regSRBM_SAM_CLKEN_CNTL__CI__VI;
typedef union SRBM_SDMA_CLKEN_CNTL__CI__VI     regSRBM_SDMA_CLKEN_CNTL__CI__VI;
typedef union SRBM_SOFT_RESET__CI              regSRBM_SOFT_RESET__CI;
typedef union SRBM_SOFT_RESET__VI              regSRBM_SOFT_RESET__VI;
typedef union SRBM_SOFT_RESET__SI              regSRBM_SOFT_RESET__SI;
typedef union SRBM_STATUS__SI__CI              regSRBM_STATUS__SI__CI;
typedef union SRBM_STATUS__VI                  regSRBM_STATUS__VI;
typedef union SRBM_STATUS2__CI                 regSRBM_STATUS2__CI;
typedef union SRBM_STATUS2__VI                 regSRBM_STATUS2__VI;
typedef union SRBM_STATUS2__SI                 regSRBM_STATUS2__SI;
typedef union SRBM_SYS_CLKEN_CNTL              regSRBM_SYS_CLKEN_CNTL;
typedef union SRBM_UVD_CLKEN_CNTL              regSRBM_UVD_CLKEN_CNTL;
typedef union SRBM_VCE_CLKEN_CNTL              regSRBM_VCE_CLKEN_CNTL;
typedef union STATE_CHANGE_STATUS__SI__VI      regSTATE_CHANGE_STATUS__SI__VI;
typedef union STATUS                           regSTATUS;
typedef union STREAM_SYNCHRONIZATION__SI       regSTREAM_SYNCHRONIZATION__SI;
typedef union STREAM_SYNCHRONIZATION__VI       regSTREAM_SYNCHRONIZATION__VI;
typedef union SUB_CLASS                        regSUB_CLASS;
typedef union SXIFCCG_DEBUG_REG0               regSXIFCCG_DEBUG_REG0;
typedef union SXIFCCG_DEBUG_REG1               regSXIFCCG_DEBUG_REG1;
typedef union SXIFCCG_DEBUG_REG2               regSXIFCCG_DEBUG_REG2;
typedef union SXIFCCG_DEBUG_REG3               regSXIFCCG_DEBUG_REG3;
typedef union SX_DEBUG_1__SI__CI               regSX_DEBUG_1__SI__CI;
typedef union SX_DEBUG_1__VI                   regSX_DEBUG_1__VI;
typedef union SX_DEBUG_BUSY                    regSX_DEBUG_BUSY;
typedef union SX_DEBUG_BUSY_2__CI__VI          regSX_DEBUG_BUSY_2__CI__VI;
typedef union SX_DEBUG_BUSY_2__SI              regSX_DEBUG_BUSY_2__SI;
typedef union SX_DEBUG_BUSY_3                  regSX_DEBUG_BUSY_3;
typedef union SX_DEBUG_BUSY_4                  regSX_DEBUG_BUSY_4;
typedef union SX_PERFCOUNTER0_HI               regSX_PERFCOUNTER0_HI;
typedef union SX_PERFCOUNTER0_LO               regSX_PERFCOUNTER0_LO;
typedef union SX_PERFCOUNTER0_SELECT           regSX_PERFCOUNTER0_SELECT;
typedef union SX_PERFCOUNTER0_SELECT1__CI__VI  regSX_PERFCOUNTER0_SELECT1__CI__VI;
typedef union SX_PERFCOUNTER1_HI               regSX_PERFCOUNTER1_HI;
typedef union SX_PERFCOUNTER1_LO               regSX_PERFCOUNTER1_LO;
typedef union SX_PERFCOUNTER1_SELECT           regSX_PERFCOUNTER1_SELECT;
typedef union SX_PERFCOUNTER1_SELECT1__CI__VI  regSX_PERFCOUNTER1_SELECT1__CI__VI;
typedef union SX_PERFCOUNTER2_HI               regSX_PERFCOUNTER2_HI;
typedef union SX_PERFCOUNTER2_LO               regSX_PERFCOUNTER2_LO;
typedef union SX_PERFCOUNTER2_SELECT           regSX_PERFCOUNTER2_SELECT;
typedef union SX_PERFCOUNTER3_HI               regSX_PERFCOUNTER3_HI;
typedef union SX_PERFCOUNTER3_LO               regSX_PERFCOUNTER3_LO;
typedef union SX_PERFCOUNTER3_SELECT           regSX_PERFCOUNTER3_SELECT;
typedef union TARGET_AND_CURRENT_PROFILE_INDEX_1 regTARGET_AND_CURRENT_PROFILE_INDEX_1;
typedef union TARGET_AND_CURRENT_PROFILE_INDEX__CI__VI regTARGET_AND_CURRENT_PROFILE_INDEX__CI__VI;
typedef union TARGET_AND_CURRENT_PROFILE_INDEX__SI regTARGET_AND_CURRENT_PROFILE_INDEX__SI;
typedef union TA_BC_BASE_ADDR                  regTA_BC_BASE_ADDR;
typedef union TA_BC_BASE_ADDR_HI__CI__VI       regTA_BC_BASE_ADDR_HI__CI__VI;
typedef union TA_CGTT_CTRL                     regTA_CGTT_CTRL;
typedef union TA_CNTL                          regTA_CNTL;
typedef union TA_CNTL_AUX                      regTA_CNTL_AUX;
typedef union TA_CS_BC_BASE_ADDR               regTA_CS_BC_BASE_ADDR;
typedef union TA_CS_BC_BASE_ADDR_HI__CI__VI    regTA_CS_BC_BASE_ADDR_HI__CI__VI;
typedef union TA_DEBUG_DATA                    regTA_DEBUG_DATA;
typedef union TA_DEBUG_INDEX                   regTA_DEBUG_INDEX;
typedef union TA_PERFCOUNTER0_HI               regTA_PERFCOUNTER0_HI;
typedef union TA_PERFCOUNTER0_LO               regTA_PERFCOUNTER0_LO;
typedef union TA_PERFCOUNTER0_SELECT           regTA_PERFCOUNTER0_SELECT;
typedef union TA_PERFCOUNTER0_SELECT1__CI__VI  regTA_PERFCOUNTER0_SELECT1__CI__VI;
typedef union TA_PERFCOUNTER1_HI               regTA_PERFCOUNTER1_HI;
typedef union TA_PERFCOUNTER1_LO               regTA_PERFCOUNTER1_LO;
typedef union TA_PERFCOUNTER1_SELECT           regTA_PERFCOUNTER1_SELECT;
typedef union TA_RESERVED_010C__CI__VI         regTA_RESERVED_010C__CI__VI;
typedef union TA_SCRATCH                       regTA_SCRATCH;
typedef union TA_STATUS                        regTA_STATUS;
typedef union TCA_CGTT_SCLK_CTRL               regTCA_CGTT_SCLK_CTRL;
typedef union TCA_CTRL                         regTCA_CTRL;
typedef union TCA_PERFCOUNTER0_HI              regTCA_PERFCOUNTER0_HI;
typedef union TCA_PERFCOUNTER0_LO              regTCA_PERFCOUNTER0_LO;
typedef union TCA_PERFCOUNTER0_SELECT1__CI__VI regTCA_PERFCOUNTER0_SELECT1__CI__VI;
typedef union TCA_PERFCOUNTER0_SELECT__CI__VI  regTCA_PERFCOUNTER0_SELECT__CI__VI;
typedef union TCA_PERFCOUNTER0_SELECT__SI      regTCA_PERFCOUNTER0_SELECT__SI;
typedef union TCA_PERFCOUNTER1_HI              regTCA_PERFCOUNTER1_HI;
typedef union TCA_PERFCOUNTER1_LO              regTCA_PERFCOUNTER1_LO;
typedef union TCA_PERFCOUNTER1_SELECT1__CI__VI regTCA_PERFCOUNTER1_SELECT1__CI__VI;
typedef union TCA_PERFCOUNTER1_SELECT__CI__VI  regTCA_PERFCOUNTER1_SELECT__CI__VI;
typedef union TCA_PERFCOUNTER1_SELECT__SI      regTCA_PERFCOUNTER1_SELECT__SI;
typedef union TCA_PERFCOUNTER2_HI              regTCA_PERFCOUNTER2_HI;
typedef union TCA_PERFCOUNTER2_LO              regTCA_PERFCOUNTER2_LO;
typedef union TCA_PERFCOUNTER2_SELECT__CI__VI  regTCA_PERFCOUNTER2_SELECT__CI__VI;
typedef union TCA_PERFCOUNTER2_SELECT__SI      regTCA_PERFCOUNTER2_SELECT__SI;
typedef union TCA_PERFCOUNTER3_HI              regTCA_PERFCOUNTER3_HI;
typedef union TCA_PERFCOUNTER3_LO              regTCA_PERFCOUNTER3_LO;
typedef union TCA_PERFCOUNTER3_SELECT__CI__VI  regTCA_PERFCOUNTER3_SELECT__CI__VI;
typedef union TCA_PERFCOUNTER3_SELECT__SI      regTCA_PERFCOUNTER3_SELECT__SI;
typedef union TCC_CGTT_SCLK_CTRL               regTCC_CGTT_SCLK_CTRL;
typedef union TCC_CTRL                         regTCC_CTRL;
typedef union TCC_EDC_COUNTER__SI__CI          regTCC_EDC_COUNTER__SI__CI;
typedef union TCC_PERFCOUNTER0_HI              regTCC_PERFCOUNTER0_HI;
typedef union TCC_PERFCOUNTER0_LO              regTCC_PERFCOUNTER0_LO;
typedef union TCC_PERFCOUNTER0_SELECT1__CI__VI regTCC_PERFCOUNTER0_SELECT1__CI__VI;
typedef union TCC_PERFCOUNTER0_SELECT__CI__VI  regTCC_PERFCOUNTER0_SELECT__CI__VI;
typedef union TCC_PERFCOUNTER0_SELECT__SI      regTCC_PERFCOUNTER0_SELECT__SI;
typedef union TCC_PERFCOUNTER1_HI              regTCC_PERFCOUNTER1_HI;
typedef union TCC_PERFCOUNTER1_LO              regTCC_PERFCOUNTER1_LO;
typedef union TCC_PERFCOUNTER1_SELECT1__CI__VI regTCC_PERFCOUNTER1_SELECT1__CI__VI;
typedef union TCC_PERFCOUNTER1_SELECT__CI__VI  regTCC_PERFCOUNTER1_SELECT__CI__VI;
typedef union TCC_PERFCOUNTER1_SELECT__SI      regTCC_PERFCOUNTER1_SELECT__SI;
typedef union TCC_PERFCOUNTER2_HI              regTCC_PERFCOUNTER2_HI;
typedef union TCC_PERFCOUNTER2_LO              regTCC_PERFCOUNTER2_LO;
typedef union TCC_PERFCOUNTER2_SELECT__CI__VI  regTCC_PERFCOUNTER2_SELECT__CI__VI;
typedef union TCC_PERFCOUNTER2_SELECT__SI      regTCC_PERFCOUNTER2_SELECT__SI;
typedef union TCC_PERFCOUNTER3_HI              regTCC_PERFCOUNTER3_HI;
typedef union TCC_PERFCOUNTER3_LO              regTCC_PERFCOUNTER3_LO;
typedef union TCC_PERFCOUNTER3_SELECT__CI__VI  regTCC_PERFCOUNTER3_SELECT__CI__VI;
typedef union TCC_PERFCOUNTER3_SELECT__SI      regTCC_PERFCOUNTER3_SELECT__SI;
typedef union TCC_REDUNDANCY__CI__VI           regTCC_REDUNDANCY__CI__VI;
typedef union TCI_CNTL_1                       regTCI_CNTL_1;
typedef union TCI_CNTL_2                       regTCI_CNTL_2;
typedef union TCI_STATUS                       regTCI_STATUS;
typedef union TCP_ADDR_CONFIG                  regTCP_ADDR_CONFIG;
typedef union TCP_BUFFER_ADDR_HASH_CNTL        regTCP_BUFFER_ADDR_HASH_CNTL;
typedef union TCP_CHAN_STEER_HI                regTCP_CHAN_STEER_HI;
typedef union TCP_CHAN_STEER_LO                regTCP_CHAN_STEER_LO;
typedef union TCP_CNTL                         regTCP_CNTL;
typedef union TCP_CREDIT                       regTCP_CREDIT;
typedef union TCP_EDC_COUNTER__SI__CI          regTCP_EDC_COUNTER__SI__CI;
typedef union TCP_INVALIDATE                   regTCP_INVALIDATE;
typedef union TCP_PERFCOUNTER0_HI              regTCP_PERFCOUNTER0_HI;
typedef union TCP_PERFCOUNTER0_LO              regTCP_PERFCOUNTER0_LO;
typedef union TCP_PERFCOUNTER0_SELECT1__CI__VI regTCP_PERFCOUNTER0_SELECT1__CI__VI;
typedef union TCP_PERFCOUNTER0_SELECT__CI__VI  regTCP_PERFCOUNTER0_SELECT__CI__VI;
typedef union TCP_PERFCOUNTER0_SELECT__SI      regTCP_PERFCOUNTER0_SELECT__SI;
typedef union TCP_PERFCOUNTER1_HI              regTCP_PERFCOUNTER1_HI;
typedef union TCP_PERFCOUNTER1_LO              regTCP_PERFCOUNTER1_LO;
typedef union TCP_PERFCOUNTER1_SELECT1__CI__VI regTCP_PERFCOUNTER1_SELECT1__CI__VI;
typedef union TCP_PERFCOUNTER1_SELECT__CI__VI  regTCP_PERFCOUNTER1_SELECT__CI__VI;
typedef union TCP_PERFCOUNTER1_SELECT__SI      regTCP_PERFCOUNTER1_SELECT__SI;
typedef union TCP_PERFCOUNTER2_HI              regTCP_PERFCOUNTER2_HI;
typedef union TCP_PERFCOUNTER2_LO              regTCP_PERFCOUNTER2_LO;
typedef union TCP_PERFCOUNTER2_SELECT__CI__VI  regTCP_PERFCOUNTER2_SELECT__CI__VI;
typedef union TCP_PERFCOUNTER2_SELECT__SI      regTCP_PERFCOUNTER2_SELECT__SI;
typedef union TCP_PERFCOUNTER3_HI              regTCP_PERFCOUNTER3_HI;
typedef union TCP_PERFCOUNTER3_LO              regTCP_PERFCOUNTER3_LO;
typedef union TCP_PERFCOUNTER3_SELECT__CI__VI  regTCP_PERFCOUNTER3_SELECT__CI__VI;
typedef union TCP_PERFCOUNTER3_SELECT__SI      regTCP_PERFCOUNTER3_SELECT__SI;
typedef union TCP_STATUS                       regTCP_STATUS;
typedef union TCP_WATCH0_ADDR_H__CI__VI        regTCP_WATCH0_ADDR_H__CI__VI;
typedef union TCP_WATCH0_ADDR_L__CI__VI        regTCP_WATCH0_ADDR_L__CI__VI;
typedef union TCP_WATCH0_CNTL__CI__VI          regTCP_WATCH0_CNTL__CI__VI;
typedef union TCP_WATCH1_ADDR_H__CI__VI        regTCP_WATCH1_ADDR_H__CI__VI;
typedef union TCP_WATCH1_ADDR_L__CI__VI        regTCP_WATCH1_ADDR_L__CI__VI;
typedef union TCP_WATCH1_CNTL__CI__VI          regTCP_WATCH1_CNTL__CI__VI;
typedef union TCP_WATCH2_ADDR_H__CI__VI        regTCP_WATCH2_ADDR_H__CI__VI;
typedef union TCP_WATCH2_ADDR_L__CI__VI        regTCP_WATCH2_ADDR_L__CI__VI;
typedef union TCP_WATCH2_CNTL__CI__VI          regTCP_WATCH2_CNTL__CI__VI;
typedef union TCP_WATCH3_ADDR_H__CI__VI        regTCP_WATCH3_ADDR_H__CI__VI;
typedef union TCP_WATCH3_ADDR_L__CI__VI        regTCP_WATCH3_ADDR_L__CI__VI;
typedef union TCP_WATCH3_CNTL__CI__VI          regTCP_WATCH3_CNTL__CI__VI;
typedef union TCS_CGTT_SCLK_CTRL__CI           regTCS_CGTT_SCLK_CTRL__CI;
typedef union TCS_CTRL__CI                     regTCS_CTRL__CI;
typedef union TCS_PERFCOUNTER0_HI__CI          regTCS_PERFCOUNTER0_HI__CI;
typedef union TCS_PERFCOUNTER0_LO__CI          regTCS_PERFCOUNTER0_LO__CI;
typedef union TCS_PERFCOUNTER0_SELECT1__CI     regTCS_PERFCOUNTER0_SELECT1__CI;
typedef union TCS_PERFCOUNTER0_SELECT__CI      regTCS_PERFCOUNTER0_SELECT__CI;
typedef union TCS_PERFCOUNTER1_HI__CI          regTCS_PERFCOUNTER1_HI__CI;
typedef union TCS_PERFCOUNTER1_LO__CI          regTCS_PERFCOUNTER1_LO__CI;
typedef union TCS_PERFCOUNTER1_SELECT__CI      regTCS_PERFCOUNTER1_SELECT__CI;
typedef union TCS_PERFCOUNTER2_HI__CI          regTCS_PERFCOUNTER2_HI__CI;
typedef union TCS_PERFCOUNTER2_LO__CI          regTCS_PERFCOUNTER2_LO__CI;
typedef union TCS_PERFCOUNTER2_SELECT__CI      regTCS_PERFCOUNTER2_SELECT__CI;
typedef union TCS_PERFCOUNTER3_HI__CI          regTCS_PERFCOUNTER3_HI__CI;
typedef union TCS_PERFCOUNTER3_LO__CI          regTCS_PERFCOUNTER3_LO__CI;
typedef union TCS_PERFCOUNTER3_SELECT__CI      regTCS_PERFCOUNTER3_SELECT__CI;
typedef union TC_CFG_L1_LOAD_POLICY0__CI__VI   regTC_CFG_L1_LOAD_POLICY0__CI__VI;
typedef union TC_CFG_L1_LOAD_POLICY1__CI__VI   regTC_CFG_L1_LOAD_POLICY1__CI__VI;
typedef union TC_CFG_L1_STORE_POLICY__CI__VI   regTC_CFG_L1_STORE_POLICY__CI__VI;
typedef union TC_CFG_L1_VOLATILE__CI__VI       regTC_CFG_L1_VOLATILE__CI__VI;
typedef union TC_CFG_L2_ATOMIC_POLICY__CI__VI  regTC_CFG_L2_ATOMIC_POLICY__CI__VI;
typedef union TC_CFG_L2_LOAD_POLICY0__CI__VI   regTC_CFG_L2_LOAD_POLICY0__CI__VI;
typedef union TC_CFG_L2_LOAD_POLICY1__CI__VI   regTC_CFG_L2_LOAD_POLICY1__CI__VI;
typedef union TC_CFG_L2_STORE_POLICY0__CI__VI  regTC_CFG_L2_STORE_POLICY0__CI__VI;
typedef union TC_CFG_L2_STORE_POLICY1__CI__VI  regTC_CFG_L2_STORE_POLICY1__CI__VI;
typedef union TC_CFG_L2_VOLATILE__CI__VI       regTC_CFG_L2_VOLATILE__CI__VI;
typedef union TD_CGTT_CTRL                     regTD_CGTT_CTRL;
typedef union TD_CNTL                          regTD_CNTL;
typedef union TD_DEBUG_DATA__CI__VI            regTD_DEBUG_DATA__CI__VI;
typedef union TD_DEBUG_DATA__SI                regTD_DEBUG_DATA__SI;
typedef union TD_DEBUG_INDEX                   regTD_DEBUG_INDEX;
typedef union TD_PERFCOUNTER0_HI               regTD_PERFCOUNTER0_HI;
typedef union TD_PERFCOUNTER0_LO               regTD_PERFCOUNTER0_LO;
typedef union TD_PERFCOUNTER0_SELECT           regTD_PERFCOUNTER0_SELECT;
typedef union TD_PERFCOUNTER0_SELECT1__CI__VI  regTD_PERFCOUNTER0_SELECT1__CI__VI;
typedef union TD_PERFCOUNTER1_HI__CI__VI       regTD_PERFCOUNTER1_HI__CI__VI;
typedef union TD_PERFCOUNTER1_LO__CI__VI       regTD_PERFCOUNTER1_LO__CI__VI;
typedef union TD_PERFCOUNTER1_SELECT__CI__VI   regTD_PERFCOUNTER1_SELECT__CI__VI;
typedef union TD_SCRATCH                       regTD_SCRATCH;
typedef union TD_STATUS                        regTD_STATUS;
typedef union THM_CLK_CNTL                     regTHM_CLK_CNTL;
typedef union THM_TMON0_DEBUG                  regTHM_TMON0_DEBUG;
typedef union THM_TMON0_INT_DATA               regTHM_TMON0_INT_DATA;
typedef union THM_TMON0_RDIL0_DATA             regTHM_TMON0_RDIL0_DATA;
typedef union THM_TMON0_RDIL10_DATA            regTHM_TMON0_RDIL10_DATA;
typedef union THM_TMON0_RDIL11_DATA            regTHM_TMON0_RDIL11_DATA;
typedef union THM_TMON0_RDIL12_DATA            regTHM_TMON0_RDIL12_DATA;
typedef union THM_TMON0_RDIL13_DATA            regTHM_TMON0_RDIL13_DATA;
typedef union THM_TMON0_RDIL14_DATA            regTHM_TMON0_RDIL14_DATA;
typedef union THM_TMON0_RDIL15_DATA            regTHM_TMON0_RDIL15_DATA;
typedef union THM_TMON0_RDIL1_DATA             regTHM_TMON0_RDIL1_DATA;
typedef union THM_TMON0_RDIL2_DATA             regTHM_TMON0_RDIL2_DATA;
typedef union THM_TMON0_RDIL3_DATA             regTHM_TMON0_RDIL3_DATA;
typedef union THM_TMON0_RDIL4_DATA             regTHM_TMON0_RDIL4_DATA;
typedef union THM_TMON0_RDIL5_DATA             regTHM_TMON0_RDIL5_DATA;
typedef union THM_TMON0_RDIL6_DATA             regTHM_TMON0_RDIL6_DATA;
typedef union THM_TMON0_RDIL7_DATA             regTHM_TMON0_RDIL7_DATA;
typedef union THM_TMON0_RDIL8_DATA             regTHM_TMON0_RDIL8_DATA;
typedef union THM_TMON0_RDIL9_DATA             regTHM_TMON0_RDIL9_DATA;
typedef union THM_TMON0_RDIR0_DATA             regTHM_TMON0_RDIR0_DATA;
typedef union THM_TMON0_RDIR10_DATA            regTHM_TMON0_RDIR10_DATA;
typedef union THM_TMON0_RDIR11_DATA            regTHM_TMON0_RDIR11_DATA;
typedef union THM_TMON0_RDIR12_DATA            regTHM_TMON0_RDIR12_DATA;
typedef union THM_TMON0_RDIR13_DATA            regTHM_TMON0_RDIR13_DATA;
typedef union THM_TMON0_RDIR14_DATA            regTHM_TMON0_RDIR14_DATA;
typedef union THM_TMON0_RDIR15_DATA            regTHM_TMON0_RDIR15_DATA;
typedef union THM_TMON0_RDIR1_DATA             regTHM_TMON0_RDIR1_DATA;
typedef union THM_TMON0_RDIR2_DATA             regTHM_TMON0_RDIR2_DATA;
typedef union THM_TMON0_RDIR3_DATA             regTHM_TMON0_RDIR3_DATA;
typedef union THM_TMON0_RDIR4_DATA             regTHM_TMON0_RDIR4_DATA;
typedef union THM_TMON0_RDIR5_DATA             regTHM_TMON0_RDIR5_DATA;
typedef union THM_TMON0_RDIR6_DATA             regTHM_TMON0_RDIR6_DATA;
typedef union THM_TMON0_RDIR7_DATA             regTHM_TMON0_RDIR7_DATA;
typedef union THM_TMON0_RDIR8_DATA             regTHM_TMON0_RDIR8_DATA;
typedef union THM_TMON0_RDIR9_DATA             regTHM_TMON0_RDIR9_DATA;
typedef union THM_TMON1_DEBUG                  regTHM_TMON1_DEBUG;
typedef union THM_TMON1_INT_DATA               regTHM_TMON1_INT_DATA;
typedef union THM_TMON1_RDIL0_DATA             regTHM_TMON1_RDIL0_DATA;
typedef union THM_TMON1_RDIL10_DATA            regTHM_TMON1_RDIL10_DATA;
typedef union THM_TMON1_RDIL11_DATA            regTHM_TMON1_RDIL11_DATA;
typedef union THM_TMON1_RDIL12_DATA            regTHM_TMON1_RDIL12_DATA;
typedef union THM_TMON1_RDIL13_DATA            regTHM_TMON1_RDIL13_DATA;
typedef union THM_TMON1_RDIL14_DATA            regTHM_TMON1_RDIL14_DATA;
typedef union THM_TMON1_RDIL15_DATA            regTHM_TMON1_RDIL15_DATA;
typedef union THM_TMON1_RDIL1_DATA             regTHM_TMON1_RDIL1_DATA;
typedef union THM_TMON1_RDIL2_DATA             regTHM_TMON1_RDIL2_DATA;
typedef union THM_TMON1_RDIL3_DATA             regTHM_TMON1_RDIL3_DATA;
typedef union THM_TMON1_RDIL4_DATA             regTHM_TMON1_RDIL4_DATA;
typedef union THM_TMON1_RDIL5_DATA             regTHM_TMON1_RDIL5_DATA;
typedef union THM_TMON1_RDIL6_DATA             regTHM_TMON1_RDIL6_DATA;
typedef union THM_TMON1_RDIL7_DATA             regTHM_TMON1_RDIL7_DATA;
typedef union THM_TMON1_RDIL8_DATA             regTHM_TMON1_RDIL8_DATA;
typedef union THM_TMON1_RDIL9_DATA             regTHM_TMON1_RDIL9_DATA;
typedef union THM_TMON1_RDIR0_DATA             regTHM_TMON1_RDIR0_DATA;
typedef union THM_TMON1_RDIR10_DATA            regTHM_TMON1_RDIR10_DATA;
typedef union THM_TMON1_RDIR11_DATA            regTHM_TMON1_RDIR11_DATA;
typedef union THM_TMON1_RDIR12_DATA            regTHM_TMON1_RDIR12_DATA;
typedef union THM_TMON1_RDIR13_DATA            regTHM_TMON1_RDIR13_DATA;
typedef union THM_TMON1_RDIR14_DATA            regTHM_TMON1_RDIR14_DATA;
typedef union THM_TMON1_RDIR15_DATA            regTHM_TMON1_RDIR15_DATA;
typedef union THM_TMON1_RDIR1_DATA             regTHM_TMON1_RDIR1_DATA;
typedef union THM_TMON1_RDIR2_DATA             regTHM_TMON1_RDIR2_DATA;
typedef union THM_TMON1_RDIR3_DATA             regTHM_TMON1_RDIR3_DATA;
typedef union THM_TMON1_RDIR4_DATA             regTHM_TMON1_RDIR4_DATA;
typedef union THM_TMON1_RDIR5_DATA             regTHM_TMON1_RDIR5_DATA;
typedef union THM_TMON1_RDIR6_DATA             regTHM_TMON1_RDIR6_DATA;
typedef union THM_TMON1_RDIR7_DATA             regTHM_TMON1_RDIR7_DATA;
typedef union THM_TMON1_RDIR8_DATA             regTHM_TMON1_RDIR8_DATA;
typedef union THM_TMON1_RDIR9_DATA             regTHM_TMON1_RDIR9_DATA;
typedef union TMDS_CNTL__SI__VI                regTMDS_CNTL__SI__VI;
typedef union TMDS_CONTROL0_FEEDBACK__SI__VI   regTMDS_CONTROL0_FEEDBACK__SI__VI;
typedef union TMDS_CONTROL_CHAR__SI__VI        regTMDS_CONTROL_CHAR__SI__VI;
typedef union TMDS_CTL0_1_GEN_CNTL__SI__VI     regTMDS_CTL0_1_GEN_CNTL__SI__VI;
typedef union TMDS_CTL2_3_GEN_CNTL__SI__VI     regTMDS_CTL2_3_GEN_CNTL__SI__VI;
typedef union TMDS_CTL_BITS__SI__VI            regTMDS_CTL_BITS__SI__VI;
typedef union TMDS_DCBALANCER_CONTROL__SI__VI  regTMDS_DCBALANCER_CONTROL__SI__VI;
typedef union TMDS_DEBUG__SI__VI               regTMDS_DEBUG__SI__VI;
typedef union TMDS_STEREOSYNC_CTL_SEL__SI__VI  regTMDS_STEREOSYNC_CTL_SEL__SI__VI;
typedef union TMDS_SYNC_CHAR_PATTERN_0_1__SI__VI regTMDS_SYNC_CHAR_PATTERN_0_1__SI__VI;
typedef union TMDS_SYNC_CHAR_PATTERN_2_3__SI__VI regTMDS_SYNC_CHAR_PATTERN_2_3__SI__VI;
typedef union UNIPHY_DATA_SYNCHRONIZATION__SI  regUNIPHY_DATA_SYNCHRONIZATION__SI;
typedef union UNIPHY_DATA_SYNCHRONIZATION__VI  regUNIPHY_DATA_SYNCHRONIZATION__VI;
typedef union UNIPHY_IMPCAL_LINKA__SI          regUNIPHY_IMPCAL_LINKA__SI;
typedef union UNIPHY_IMPCAL_LINKA__VI          regUNIPHY_IMPCAL_LINKA__VI;
typedef union UNIPHY_IMPCAL_LINKB__SI          regUNIPHY_IMPCAL_LINKB__SI;
typedef union UNIPHY_IMPCAL_LINKB__VI          regUNIPHY_IMPCAL_LINKB__VI;
typedef union UNIPHY_IMPCAL_LINKC__SI          regUNIPHY_IMPCAL_LINKC__SI;
typedef union UNIPHY_IMPCAL_LINKC__VI          regUNIPHY_IMPCAL_LINKC__VI;
typedef union UNIPHY_IMPCAL_LINKD__SI          regUNIPHY_IMPCAL_LINKD__SI;
typedef union UNIPHY_IMPCAL_LINKD__VI          regUNIPHY_IMPCAL_LINKD__VI;
typedef union UNIPHY_IMPCAL_LINKE__SI          regUNIPHY_IMPCAL_LINKE__SI;
typedef union UNIPHY_IMPCAL_LINKE__VI          regUNIPHY_IMPCAL_LINKE__VI;
typedef union UNIPHY_IMPCAL_LINKF__SI          regUNIPHY_IMPCAL_LINKF__SI;
typedef union UNIPHY_IMPCAL_LINKF__VI          regUNIPHY_IMPCAL_LINKF__VI;
typedef union UNIPHY_IMPCAL_PERIOD__SI__VI     regUNIPHY_IMPCAL_PERIOD__SI__VI;
typedef union UNIPHY_REG_TEST_OUTPUT__SI       regUNIPHY_REG_TEST_OUTPUT__SI;
typedef union UNIPHY_REG_TEST_OUTPUT__VI       regUNIPHY_REG_TEST_OUTPUT__VI;
typedef union USER_SQC_BANK_DISABLE            regUSER_SQC_BANK_DISABLE;
typedef union UVD_CGC_CTRL__SI                 regUVD_CGC_CTRL__SI;
typedef union UVD_CGC_CTRL__VI                 regUVD_CGC_CTRL__VI;
typedef union UVD_CGC_GATE__SI__VI             regUVD_CGC_GATE__SI__VI;
typedef union UVD_CGC_STATUS__SI__VI           regUVD_CGC_STATUS__SI__VI;
typedef union UVD_CONFIG                       regUVD_CONFIG;
typedef union UVD_CONTEXT_ID__SI__VI           regUVD_CONTEXT_ID__SI__VI;
typedef union UVD_CTX_DATA__SI__VI             regUVD_CTX_DATA__SI__VI;
typedef union UVD_CTX_INDEX__SI__VI            regUVD_CTX_INDEX__SI__VI;
typedef union UVD_ENGINE_CNTL__SI__VI          regUVD_ENGINE_CNTL__SI__VI;
typedef union UVD_GPCOM_VCPU_CMD__SI__VI       regUVD_GPCOM_VCPU_CMD__SI__VI;
typedef union UVD_GPCOM_VCPU_DATA0__SI__VI     regUVD_GPCOM_VCPU_DATA0__SI__VI;
typedef union UVD_GPCOM_VCPU_DATA1__SI__VI     regUVD_GPCOM_VCPU_DATA1__SI__VI;
typedef union UVD_LMI_ADDR_EXT__SI__VI         regUVD_LMI_ADDR_EXT__SI__VI;
typedef union UVD_LMI_CACHE_CTRL__SI__VI       regUVD_LMI_CACHE_CTRL__SI__VI;
typedef union UVD_LMI_CTRL2__SI__VI            regUVD_LMI_CTRL2__SI__VI;
typedef union UVD_LMI_CTRL__SI                 regUVD_LMI_CTRL__SI;
typedef union UVD_LMI_CTRL__VI                 regUVD_LMI_CTRL__VI;
typedef union UVD_LMI_EXT40_ADDR__SI__VI       regUVD_LMI_EXT40_ADDR__SI__VI;
typedef union UVD_LMI_STATUS__SI__VI           regUVD_LMI_STATUS__SI__VI;
typedef union UVD_LMI_SWAP_CNTL__SI__VI        regUVD_LMI_SWAP_CNTL__SI__VI;
typedef union UVD_MASTINT_EN__SI__VI           regUVD_MASTINT_EN__SI__VI;
typedef union UVD_MPC_CNTL__SI__VI             regUVD_MPC_CNTL__SI__VI;
typedef union UVD_MPC_SET_ALU__SI__VI          regUVD_MPC_SET_ALU__SI__VI;
typedef union UVD_MPC_SET_MUXA0__SI__VI        regUVD_MPC_SET_MUXA0__SI__VI;
typedef union UVD_MPC_SET_MUXA1__SI__VI        regUVD_MPC_SET_MUXA1__SI__VI;
typedef union UVD_MPC_SET_MUXB0__SI__VI        regUVD_MPC_SET_MUXB0__SI__VI;
typedef union UVD_MPC_SET_MUXB1__SI__VI        regUVD_MPC_SET_MUXB1__SI__VI;
typedef union UVD_MPC_SET_MUX__SI__VI          regUVD_MPC_SET_MUX__SI__VI;
typedef union UVD_MP_SWAP_CNTL__SI__VI         regUVD_MP_SWAP_CNTL__SI__VI;
typedef union UVD_RBC_IB_BASE__SI              regUVD_RBC_IB_BASE__SI;
typedef union UVD_RBC_IB_SIZE__SI__VI          regUVD_RBC_IB_SIZE__SI__VI;
typedef union UVD_RBC_RB_BASE__SI              regUVD_RBC_RB_BASE__SI;
typedef union UVD_RBC_RB_CNTL__SI__VI          regUVD_RBC_RB_CNTL__SI__VI;
typedef union UVD_RBC_RB_RPTR_ADDR__SI__VI     regUVD_RBC_RB_RPTR_ADDR__SI__VI;
typedef union UVD_RBC_RB_RPTR__SI__VI          regUVD_RBC_RB_RPTR__SI__VI;
typedef union UVD_RBC_RB_WPTR__SI__VI          regUVD_RBC_RB_WPTR__SI__VI;
typedef union UVD_SEMA_ADDR_HIGH__SI__VI       regUVD_SEMA_ADDR_HIGH__SI__VI;
typedef union UVD_SEMA_ADDR_LOW__SI__VI        regUVD_SEMA_ADDR_LOW__SI__VI;
typedef union UVD_SEMA_CMD__SI__VI             regUVD_SEMA_CMD__SI__VI;
typedef union UVD_SEMA_CNTL__SI__VI            regUVD_SEMA_CNTL__SI__VI;
typedef union UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI__VI regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SI__VI;
typedef union UVD_SEMA_TIMEOUT_STATUS__SI__VI  regUVD_SEMA_TIMEOUT_STATUS__SI__VI;
typedef union UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI__VI regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__SI__VI;
typedef union UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI__VI regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__SI__VI;
typedef union UVD_SOFT_RESET__SI               regUVD_SOFT_RESET__SI;
typedef union UVD_SOFT_RESET__VI               regUVD_SOFT_RESET__VI;
typedef union UVD_STATUS__SI__VI               regUVD_STATUS__SI__VI;
typedef union UVD_VCPU_CACHE_OFFSET0__SI__VI   regUVD_VCPU_CACHE_OFFSET0__SI__VI;
typedef union UVD_VCPU_CACHE_OFFSET1__SI__VI   regUVD_VCPU_CACHE_OFFSET1__SI__VI;
typedef union UVD_VCPU_CACHE_OFFSET2__SI__VI   regUVD_VCPU_CACHE_OFFSET2__SI__VI;
typedef union UVD_VCPU_CACHE_SIZE0__SI__VI     regUVD_VCPU_CACHE_SIZE0__SI__VI;
typedef union UVD_VCPU_CACHE_SIZE1__SI__VI     regUVD_VCPU_CACHE_SIZE1__SI__VI;
typedef union UVD_VCPU_CACHE_SIZE2__SI__VI     regUVD_VCPU_CACHE_SIZE2__SI__VI;
typedef union UVD_VCPU_CNTL__SI                regUVD_VCPU_CNTL__SI;
typedef union UVD_VCPU_CNTL__VI                regUVD_VCPU_CNTL__VI;
typedef union VCE_CONFIG__CI__VI               regVCE_CONFIG__CI__VI;
typedef union VENDOR_CAP_LIST__CI__VI          regVENDOR_CAP_LIST__CI__VI;
typedef union VENDOR_ID                        regVENDOR_ID;
typedef union VGA25_PPLL_FB_DIV__SI__VI        regVGA25_PPLL_FB_DIV__SI__VI;
typedef union VGA25_PPLL_POST_DIV__SI          regVGA25_PPLL_POST_DIV__SI;
typedef union VGA25_PPLL_POST_DIV__VI          regVGA25_PPLL_POST_DIV__VI;
typedef union VGA25_PPLL_REF_DIV__SI__VI       regVGA25_PPLL_REF_DIV__SI__VI;
typedef union VGA28_PPLL_FB_DIV__SI__VI        regVGA28_PPLL_FB_DIV__SI__VI;
typedef union VGA28_PPLL_POST_DIV__SI          regVGA28_PPLL_POST_DIV__SI;
typedef union VGA28_PPLL_POST_DIV__VI          regVGA28_PPLL_POST_DIV__VI;
typedef union VGA28_PPLL_REF_DIV__SI__VI       regVGA28_PPLL_REF_DIV__SI__VI;
typedef union VGA41_PPLL_FB_DIV__SI__VI        regVGA41_PPLL_FB_DIV__SI__VI;
typedef union VGA41_PPLL_POST_DIV__SI          regVGA41_PPLL_POST_DIV__SI;
typedef union VGA41_PPLL_POST_DIV__VI          regVGA41_PPLL_POST_DIV__VI;
typedef union VGA41_PPLL_REF_DIV__SI__VI       regVGA41_PPLL_REF_DIV__SI__VI;
typedef union VGADCC_DBG_DCCIF_C__SI__VI       regVGADCC_DBG_DCCIF_C__SI__VI;
typedef union VGA_CACHE_CONTROL__SI__VI        regVGA_CACHE_CONTROL__SI__VI;
typedef union VGA_DEBUG_READBACK_DATA__SI__VI  regVGA_DEBUG_READBACK_DATA__SI__VI;
typedef union VGA_DEBUG_READBACK_INDEX__SI__VI regVGA_DEBUG_READBACK_INDEX__SI__VI;
typedef union VGA_DISPBUF1_SURFACE_ADDR__SI__VI regVGA_DISPBUF1_SURFACE_ADDR__SI__VI;
typedef union VGA_DISPBUF2_SURFACE_ADDR__SI__VI regVGA_DISPBUF2_SURFACE_ADDR__SI__VI;
typedef union VGA_HDP_CONTROL__SI__VI          regVGA_HDP_CONTROL__SI__VI;
typedef union VGA_HDP__SI__VI                  regVGA_HDP__SI__VI;
typedef union VGA_HW_DEBUG__SI__VI             regVGA_HW_DEBUG__SI__VI;
typedef union VGA_INTERRUPT_CONTROL__SI__VI    regVGA_INTERRUPT_CONTROL__SI__VI;
typedef union VGA_INTERRUPT_STATUS__SI__VI     regVGA_INTERRUPT_STATUS__SI__VI;
typedef union VGA_MAIN_CONTROL__SI__VI         regVGA_MAIN_CONTROL__SI__VI;
typedef union VGA_MAIN__SI__VI                 regVGA_MAIN__SI__VI;
typedef union VGA_MEMORY_BASE_ADDRESS_HIGH__SI__VI regVGA_MEMORY_BASE_ADDRESS_HIGH__SI__VI;
typedef union VGA_MEMORY_BASE_ADDRESS__SI__VI  regVGA_MEMORY_BASE_ADDRESS__SI__VI;
typedef union VGA_MEM_READ_PAGE_ADDR__SI__VI   regVGA_MEM_READ_PAGE_ADDR__SI__VI;
typedef union VGA_MEM_WRITE_PAGE_ADDR__SI__VI  regVGA_MEM_WRITE_PAGE_ADDR__SI__VI;
typedef union VGA_MODE_CONTROL__SI__VI         regVGA_MODE_CONTROL__SI__VI;
typedef union VGA_RENDER_CONTROL__SI__VI       regVGA_RENDER_CONTROL__SI__VI;
typedef union VGA_SEQUENCER_RESET_CONTROL__SI__VI regVGA_SEQUENCER_RESET_CONTROL__SI__VI;
typedef union VGA_SOURCE_SELECT__SI__VI        regVGA_SOURCE_SELECT__SI__VI;
typedef union VGA_STATUS_CLEAR__SI__VI         regVGA_STATUS_CLEAR__SI__VI;
typedef union VGA_STATUS__SI__VI               regVGA_STATUS__SI__VI;
typedef union VGA_SURFACE_PITCH_SELECT__SI__VI regVGA_SURFACE_PITCH_SELECT__SI__VI;
typedef union VGA_TEST_CONTROL__SI__VI         regVGA_TEST_CONTROL__SI__VI;
typedef union VGA_TEST_DEBUG_DATA__SI__VI      regVGA_TEST_DEBUG_DATA__SI__VI;
typedef union VGA_TEST_DEBUG_INDEX__SI__VI     regVGA_TEST_DEBUG_INDEX__SI__VI;
typedef union VGT_CACHE_INVALIDATION           regVGT_CACHE_INVALIDATION;
typedef union VGT_CNTL_STATUS                  regVGT_CNTL_STATUS;
typedef union VGT_DEBUG_CNTL                   regVGT_DEBUG_CNTL;
typedef union VGT_DEBUG_DATA                   regVGT_DEBUG_DATA;
typedef union VGT_DEBUG_REG0                   regVGT_DEBUG_REG0;
typedef union VGT_DEBUG_REG1                   regVGT_DEBUG_REG1;
typedef union VGT_DEBUG_REG10__CI__VI          regVGT_DEBUG_REG10__CI__VI;
typedef union VGT_DEBUG_REG10__SI              regVGT_DEBUG_REG10__SI;
typedef union VGT_DEBUG_REG11__CI__VI          regVGT_DEBUG_REG11__CI__VI;
typedef union VGT_DEBUG_REG11__SI              regVGT_DEBUG_REG11__SI;
typedef union VGT_DEBUG_REG12                  regVGT_DEBUG_REG12;
typedef union VGT_DEBUG_REG13                  regVGT_DEBUG_REG13;
typedef union VGT_DEBUG_REG14                  regVGT_DEBUG_REG14;
typedef union VGT_DEBUG_REG15__CI__VI          regVGT_DEBUG_REG15__CI__VI;
typedef union VGT_DEBUG_REG15__SI              regVGT_DEBUG_REG15__SI;
typedef union VGT_DEBUG_REG16__CI__VI          regVGT_DEBUG_REG16__CI__VI;
typedef union VGT_DEBUG_REG16__SI              regVGT_DEBUG_REG16__SI;
typedef union VGT_DEBUG_REG17                  regVGT_DEBUG_REG17;
typedef union VGT_DEBUG_REG18__CI__VI          regVGT_DEBUG_REG18__CI__VI;
typedef union VGT_DEBUG_REG18__SI              regVGT_DEBUG_REG18__SI;
typedef union VGT_DEBUG_REG19__CI__VI          regVGT_DEBUG_REG19__CI__VI;
typedef union VGT_DEBUG_REG19__SI              regVGT_DEBUG_REG19__SI;
typedef union VGT_DEBUG_REG20                  regVGT_DEBUG_REG20;
typedef union VGT_DEBUG_REG21                  regVGT_DEBUG_REG21;
typedef union VGT_DEBUG_REG22                  regVGT_DEBUG_REG22;
typedef union VGT_DEBUG_REG23                  regVGT_DEBUG_REG23;
typedef union VGT_DEBUG_REG24                  regVGT_DEBUG_REG24;
typedef union VGT_DEBUG_REG25                  regVGT_DEBUG_REG25;
typedef union VGT_DEBUG_REG26__CI__VI          regVGT_DEBUG_REG26__CI__VI;
typedef union VGT_DEBUG_REG26__SI              regVGT_DEBUG_REG26__SI;
typedef union VGT_DEBUG_REG27                  regVGT_DEBUG_REG27;
typedef union VGT_DEBUG_REG28                  regVGT_DEBUG_REG28;
typedef union VGT_DEBUG_REG29                  regVGT_DEBUG_REG29;
typedef union VGT_DEBUG_REG2__CI__VI           regVGT_DEBUG_REG2__CI__VI;
typedef union VGT_DEBUG_REG2__SI               regVGT_DEBUG_REG2__SI;
typedef union VGT_DEBUG_REG30__CI              regVGT_DEBUG_REG30__CI;
typedef union VGT_DEBUG_REG30__SI              regVGT_DEBUG_REG30__SI;
typedef union VGT_DEBUG_REG31__CI__VI          regVGT_DEBUG_REG31__CI__VI;
typedef union VGT_DEBUG_REG31__SI              regVGT_DEBUG_REG31__SI;
typedef union VGT_DEBUG_REG32__CI__VI          regVGT_DEBUG_REG32__CI__VI;
typedef union VGT_DEBUG_REG32__SI              regVGT_DEBUG_REG32__SI;
typedef union VGT_DEBUG_REG33__CI__VI          regVGT_DEBUG_REG33__CI__VI;
typedef union VGT_DEBUG_REG33__SI              regVGT_DEBUG_REG33__SI;
typedef union VGT_DEBUG_REG34__CI__VI          regVGT_DEBUG_REG34__CI__VI;
typedef union VGT_DEBUG_REG34__SI              regVGT_DEBUG_REG34__SI;
typedef union VGT_DEBUG_REG35__CI              regVGT_DEBUG_REG35__CI;
typedef union VGT_DEBUG_REG35__SI              regVGT_DEBUG_REG35__SI;
typedef union VGT_DEBUG_REG36__SI              regVGT_DEBUG_REG36__SI;
typedef union VGT_DEBUG_REG36__VI              regVGT_DEBUG_REG36__VI;
typedef union VGT_DEBUG_REG3__CI__VI           regVGT_DEBUG_REG3__CI__VI;
typedef union VGT_DEBUG_REG3__SI               regVGT_DEBUG_REG3__SI;
typedef union VGT_DEBUG_REG4__CI__VI           regVGT_DEBUG_REG4__CI__VI;
typedef union VGT_DEBUG_REG4__SI               regVGT_DEBUG_REG4__SI;
typedef union VGT_DEBUG_REG5__CI__VI           regVGT_DEBUG_REG5__CI__VI;
typedef union VGT_DEBUG_REG5__SI               regVGT_DEBUG_REG5__SI;
typedef union VGT_DEBUG_REG6__CI__VI           regVGT_DEBUG_REG6__CI__VI;
typedef union VGT_DEBUG_REG6__SI               regVGT_DEBUG_REG6__SI;
typedef union VGT_DEBUG_REG7__CI__VI           regVGT_DEBUG_REG7__CI__VI;
typedef union VGT_DEBUG_REG7__SI               regVGT_DEBUG_REG7__SI;
typedef union VGT_DEBUG_REG8__CI__VI           regVGT_DEBUG_REG8__CI__VI;
typedef union VGT_DEBUG_REG8__SI               regVGT_DEBUG_REG8__SI;
typedef union VGT_DEBUG_REG9                   regVGT_DEBUG_REG9;
typedef union VGT_DMA_BASE                     regVGT_DMA_BASE;
typedef union VGT_DMA_BASE_HI                  regVGT_DMA_BASE_HI;
typedef union VGT_DMA_CONTROL__CI__VI          regVGT_DMA_CONTROL__CI__VI;
typedef union VGT_DMA_DATA_FIFO_DEPTH          regVGT_DMA_DATA_FIFO_DEPTH;
typedef union VGT_DMA_INDEX_TYPE__SI__CI       regVGT_DMA_INDEX_TYPE__SI__CI;
typedef union VGT_DMA_INDEX_TYPE__VI           regVGT_DMA_INDEX_TYPE__VI;
typedef union VGT_DMA_LS_HS_CONFIG__CI__VI     regVGT_DMA_LS_HS_CONFIG__CI__VI;
typedef union VGT_DMA_MAX_SIZE                 regVGT_DMA_MAX_SIZE;
typedef union VGT_DMA_NUM_INSTANCES            regVGT_DMA_NUM_INSTANCES;
typedef union VGT_DMA_PRIMITIVE_TYPE__CI__VI   regVGT_DMA_PRIMITIVE_TYPE__CI__VI;
typedef union VGT_DMA_REQ_FIFO_DEPTH           regVGT_DMA_REQ_FIFO_DEPTH;
typedef union VGT_DMA_SIZE                     regVGT_DMA_SIZE;
typedef union VGT_DRAW_INITIATOR               regVGT_DRAW_INITIATOR;
typedef union VGT_DRAW_INIT_FIFO_DEPTH         regVGT_DRAW_INIT_FIFO_DEPTH;
typedef union VGT_ENHANCE                      regVGT_ENHANCE;
typedef union VGT_ESGS_RING_ITEMSIZE           regVGT_ESGS_RING_ITEMSIZE;
typedef union VGT_ESGS_RING_SIZE               regVGT_ESGS_RING_SIZE;
typedef union VGT_ES_PER_GS                    regVGT_ES_PER_GS;
typedef union VGT_EVENT_ADDRESS_REG            regVGT_EVENT_ADDRESS_REG;
typedef union VGT_EVENT_INITIATOR              regVGT_EVENT_INITIATOR;
typedef union VGT_FIFO_DEPTHS                  regVGT_FIFO_DEPTHS;
typedef union VGT_GROUP_DECR                   regVGT_GROUP_DECR;
typedef union VGT_GROUP_FIRST_DECR             regVGT_GROUP_FIRST_DECR;
typedef union VGT_GROUP_PRIM_TYPE              regVGT_GROUP_PRIM_TYPE;
typedef union VGT_GROUP_VECT_0_CNTL            regVGT_GROUP_VECT_0_CNTL;
typedef union VGT_GROUP_VECT_0_FMT_CNTL        regVGT_GROUP_VECT_0_FMT_CNTL;
typedef union VGT_GROUP_VECT_1_CNTL            regVGT_GROUP_VECT_1_CNTL;
typedef union VGT_GROUP_VECT_1_FMT_CNTL        regVGT_GROUP_VECT_1_FMT_CNTL;
typedef union VGT_GSVS_RING_ITEMSIZE           regVGT_GSVS_RING_ITEMSIZE;
typedef union VGT_GSVS_RING_OFFSET_1           regVGT_GSVS_RING_OFFSET_1;
typedef union VGT_GSVS_RING_OFFSET_2           regVGT_GSVS_RING_OFFSET_2;
typedef union VGT_GSVS_RING_OFFSET_3           regVGT_GSVS_RING_OFFSET_3;
typedef union VGT_GSVS_RING_SIZE               regVGT_GSVS_RING_SIZE;
typedef union VGT_GS_INSTANCE_CNT              regVGT_GS_INSTANCE_CNT;
typedef union VGT_GS_MAX_VERT_OUT              regVGT_GS_MAX_VERT_OUT;
typedef union VGT_GS_MODE                      regVGT_GS_MODE;
typedef union VGT_GS_ONCHIP_CNTL__CI__VI       regVGT_GS_ONCHIP_CNTL__CI__VI;
typedef union VGT_GS_OUT_PRIM_TYPE             regVGT_GS_OUT_PRIM_TYPE;
typedef union VGT_GS_PER_ES                    regVGT_GS_PER_ES;
typedef union VGT_GS_PER_VS                    regVGT_GS_PER_VS;
typedef union VGT_GS_VERTEX_REUSE              regVGT_GS_VERTEX_REUSE;
typedef union VGT_GS_VERT_ITEMSIZE             regVGT_GS_VERT_ITEMSIZE;
typedef union VGT_GS_VERT_ITEMSIZE_1           regVGT_GS_VERT_ITEMSIZE_1;
typedef union VGT_GS_VERT_ITEMSIZE_2           regVGT_GS_VERT_ITEMSIZE_2;
typedef union VGT_GS_VERT_ITEMSIZE_3           regVGT_GS_VERT_ITEMSIZE_3;
typedef union VGT_HOS_CNTL                     regVGT_HOS_CNTL;
typedef union VGT_HOS_MAX_TESS_LEVEL           regVGT_HOS_MAX_TESS_LEVEL;
typedef union VGT_HOS_MIN_TESS_LEVEL           regVGT_HOS_MIN_TESS_LEVEL;
typedef union VGT_HOS_REUSE_DEPTH              regVGT_HOS_REUSE_DEPTH;
typedef union VGT_HS_OFFCHIP_PARAM             regVGT_HS_OFFCHIP_PARAM;
typedef union VGT_IMMED_DATA                   regVGT_IMMED_DATA;
typedef union VGT_INDEX_TYPE                   regVGT_INDEX_TYPE;
typedef union VGT_INDX_OFFSET                  regVGT_INDX_OFFSET;
typedef union VGT_INSTANCE_STEP_RATE_0         regVGT_INSTANCE_STEP_RATE_0;
typedef union VGT_INSTANCE_STEP_RATE_1         regVGT_INSTANCE_STEP_RATE_1;
typedef union VGT_LAST_COPY_STATE              regVGT_LAST_COPY_STATE;
typedef union VGT_LS_HS_CONFIG                 regVGT_LS_HS_CONFIG;
typedef union VGT_MAX_VTX_INDX                 regVGT_MAX_VTX_INDX;
typedef union VGT_MC_LAT_CNTL                  regVGT_MC_LAT_CNTL;
typedef union VGT_MIN_VTX_INDX                 regVGT_MIN_VTX_INDX;
typedef union VGT_MULTI_PRIM_IB_RESET_EN       regVGT_MULTI_PRIM_IB_RESET_EN;
typedef union VGT_MULTI_PRIM_IB_RESET_INDX     regVGT_MULTI_PRIM_IB_RESET_INDX;
typedef union VGT_NUM_INDICES                  regVGT_NUM_INDICES;
typedef union VGT_NUM_INSTANCES                regVGT_NUM_INSTANCES;
typedef union VGT_OUTPUT_PATH_CNTL             regVGT_OUTPUT_PATH_CNTL;
typedef union VGT_OUT_DEALLOC_CNTL             regVGT_OUT_DEALLOC_CNTL;
typedef union VGT_PERFCOUNTER0_HI              regVGT_PERFCOUNTER0_HI;
typedef union VGT_PERFCOUNTER0_LO              regVGT_PERFCOUNTER0_LO;
typedef union VGT_PERFCOUNTER0_SELECT1__CI__VI regVGT_PERFCOUNTER0_SELECT1__CI__VI;
typedef union VGT_PERFCOUNTER0_SELECT__CI__VI  regVGT_PERFCOUNTER0_SELECT__CI__VI;
typedef union VGT_PERFCOUNTER0_SELECT__SI      regVGT_PERFCOUNTER0_SELECT__SI;
typedef union VGT_PERFCOUNTER1_HI              regVGT_PERFCOUNTER1_HI;
typedef union VGT_PERFCOUNTER1_LO              regVGT_PERFCOUNTER1_LO;
typedef union VGT_PERFCOUNTER1_SELECT1__CI__VI regVGT_PERFCOUNTER1_SELECT1__CI__VI;
typedef union VGT_PERFCOUNTER1_SELECT__CI__VI  regVGT_PERFCOUNTER1_SELECT__CI__VI;
typedef union VGT_PERFCOUNTER1_SELECT__SI      regVGT_PERFCOUNTER1_SELECT__SI;
typedef union VGT_PERFCOUNTER2_HI              regVGT_PERFCOUNTER2_HI;
typedef union VGT_PERFCOUNTER2_LO              regVGT_PERFCOUNTER2_LO;
typedef union VGT_PERFCOUNTER2_SELECT          regVGT_PERFCOUNTER2_SELECT;
typedef union VGT_PERFCOUNTER3_HI              regVGT_PERFCOUNTER3_HI;
typedef union VGT_PERFCOUNTER3_LO              regVGT_PERFCOUNTER3_LO;
typedef union VGT_PERFCOUNTER3_SELECT          regVGT_PERFCOUNTER3_SELECT;
typedef union VGT_PERFCOUNTER_SEID_MASK        regVGT_PERFCOUNTER_SEID_MASK;
typedef union VGT_PRIMITIVEID_EN               regVGT_PRIMITIVEID_EN;
typedef union VGT_PRIMITIVEID_RESET            regVGT_PRIMITIVEID_RESET;
typedef union VGT_PRIMITIVE_TYPE               regVGT_PRIMITIVE_TYPE;
typedef union VGT_RESET_DEBUG__CI__VI          regVGT_RESET_DEBUG__CI__VI;
typedef union VGT_REUSE_OFF                    regVGT_REUSE_OFF;
typedef union VGT_SHADER_STAGES_EN             regVGT_SHADER_STAGES_EN;
typedef union VGT_STRMOUT_BUFFER_CONFIG        regVGT_STRMOUT_BUFFER_CONFIG;
typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_0 regVGT_STRMOUT_BUFFER_FILLED_SIZE_0;
typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_1 regVGT_STRMOUT_BUFFER_FILLED_SIZE_1;
typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_2 regVGT_STRMOUT_BUFFER_FILLED_SIZE_2;
typedef union VGT_STRMOUT_BUFFER_FILLED_SIZE_3 regVGT_STRMOUT_BUFFER_FILLED_SIZE_3;
typedef union VGT_STRMOUT_BUFFER_OFFSET_0      regVGT_STRMOUT_BUFFER_OFFSET_0;
typedef union VGT_STRMOUT_BUFFER_OFFSET_1      regVGT_STRMOUT_BUFFER_OFFSET_1;
typedef union VGT_STRMOUT_BUFFER_OFFSET_2      regVGT_STRMOUT_BUFFER_OFFSET_2;
typedef union VGT_STRMOUT_BUFFER_OFFSET_3      regVGT_STRMOUT_BUFFER_OFFSET_3;
typedef union VGT_STRMOUT_BUFFER_SIZE_0        regVGT_STRMOUT_BUFFER_SIZE_0;
typedef union VGT_STRMOUT_BUFFER_SIZE_1        regVGT_STRMOUT_BUFFER_SIZE_1;
typedef union VGT_STRMOUT_BUFFER_SIZE_2        regVGT_STRMOUT_BUFFER_SIZE_2;
typedef union VGT_STRMOUT_BUFFER_SIZE_3        regVGT_STRMOUT_BUFFER_SIZE_3;
typedef union VGT_STRMOUT_CONFIG               regVGT_STRMOUT_CONFIG;
typedef union VGT_STRMOUT_DELAY__CI__VI        regVGT_STRMOUT_DELAY__CI__VI;
typedef union VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE;
typedef union VGT_STRMOUT_DRAW_OPAQUE_OFFSET   regVGT_STRMOUT_DRAW_OPAQUE_OFFSET;
typedef union VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE;
typedef union VGT_STRMOUT_VTX_STRIDE_0         regVGT_STRMOUT_VTX_STRIDE_0;
typedef union VGT_STRMOUT_VTX_STRIDE_1         regVGT_STRMOUT_VTX_STRIDE_1;
typedef union VGT_STRMOUT_VTX_STRIDE_2         regVGT_STRMOUT_VTX_STRIDE_2;
typedef union VGT_STRMOUT_VTX_STRIDE_3         regVGT_STRMOUT_VTX_STRIDE_3;
typedef union VGT_SYS_CONFIG                   regVGT_SYS_CONFIG;
typedef union VGT_TF_MEMORY_BASE               regVGT_TF_MEMORY_BASE;
typedef union VGT_TF_PARAM                     regVGT_TF_PARAM;
typedef union VGT_TF_RING_SIZE                 regVGT_TF_RING_SIZE;
typedef union VGT_VERTEX_REUSE_BLOCK_CNTL      regVGT_VERTEX_REUSE_BLOCK_CNTL;
typedef union VGT_VS_MAX_WAVE_ID__CI__VI       regVGT_VS_MAX_WAVE_ID__CI__VI;
typedef union VGT_VTX_CNT_EN                   regVGT_VTX_CNT_EN;
typedef union VGT_VTX_VECT_EJECT_REG           regVGT_VTX_VECT_EJECT_REG;
typedef union VIEWPORT_SIZE__SI__VI            regVIEWPORT_SIZE__SI__VI;
typedef union VIEWPORT_START__SI__VI           regVIEWPORT_START__SI__VI;
typedef union VM_CONTEXT0_CNTL__SI__CI         regVM_CONTEXT0_CNTL__SI__CI;
typedef union VM_CONTEXT0_CNTL__VI             regVM_CONTEXT0_CNTL__VI;
typedef union VM_CONTEXT0_CNTL2                regVM_CONTEXT0_CNTL2;
typedef union VM_CONTEXT0_PAGE_TABLE_BASE_ADDR regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT0_PAGE_TABLE_END_ADDR  regVM_CONTEXT0_PAGE_TABLE_END_ADDR;
typedef union VM_CONTEXT0_PAGE_TABLE_START_ADDR regVM_CONTEXT0_PAGE_TABLE_START_ADDR;
typedef union VM_CONTEXT0_PROTECTION_FAULT_ADDR regVM_CONTEXT0_PROTECTION_FAULT_ADDR;
typedef union VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR regVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR;
typedef union VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI regVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__CI__VI;
typedef union VM_CONTEXT0_PROTECTION_FAULT_STATUS regVM_CONTEXT0_PROTECTION_FAULT_STATUS;
typedef union VM_CONTEXT10_PAGE_TABLE_BASE_ADDR regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT11_PAGE_TABLE_BASE_ADDR regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT12_PAGE_TABLE_BASE_ADDR regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT13_PAGE_TABLE_BASE_ADDR regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT14_PAGE_TABLE_BASE_ADDR regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT15_PAGE_TABLE_BASE_ADDR regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT1_CNTL__SI__CI         regVM_CONTEXT1_CNTL__SI__CI;
typedef union VM_CONTEXT1_CNTL__VI             regVM_CONTEXT1_CNTL__VI;
typedef union VM_CONTEXT1_CNTL2                regVM_CONTEXT1_CNTL2;
typedef union VM_CONTEXT1_PAGE_TABLE_BASE_ADDR regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT1_PAGE_TABLE_END_ADDR  regVM_CONTEXT1_PAGE_TABLE_END_ADDR;
typedef union VM_CONTEXT1_PAGE_TABLE_START_ADDR regVM_CONTEXT1_PAGE_TABLE_START_ADDR;
typedef union VM_CONTEXT1_PROTECTION_FAULT_ADDR regVM_CONTEXT1_PROTECTION_FAULT_ADDR;
typedef union VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR regVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR;
typedef union VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI regVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__CI__VI;
typedef union VM_CONTEXT1_PROTECTION_FAULT_STATUS regVM_CONTEXT1_PROTECTION_FAULT_STATUS;
typedef union VM_CONTEXT2_PAGE_TABLE_BASE_ADDR regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT3_PAGE_TABLE_BASE_ADDR regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT4_PAGE_TABLE_BASE_ADDR regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT5_PAGE_TABLE_BASE_ADDR regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT6_PAGE_TABLE_BASE_ADDR regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT7_PAGE_TABLE_BASE_ADDR regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT8_PAGE_TABLE_BASE_ADDR regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXT9_PAGE_TABLE_BASE_ADDR regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR;
typedef union VM_CONTEXTS_DISABLE              regVM_CONTEXTS_DISABLE;
typedef union VM_DEBUG                         regVM_DEBUG;
typedef union VM_DUMMY_PAGE_FAULT_ADDR         regVM_DUMMY_PAGE_FAULT_ADDR;
typedef union VM_DUMMY_PAGE_FAULT_CNTL         regVM_DUMMY_PAGE_FAULT_CNTL;
typedef union VM_FAULT_CLIENT_ID               regVM_FAULT_CLIENT_ID;
typedef union VM_INVALIDATE_REQUEST            regVM_INVALIDATE_REQUEST;
typedef union VM_INVALIDATE_RESPONSE           regVM_INVALIDATE_RESPONSE;
typedef union VM_L2_BANK_SELECT_MASKA          regVM_L2_BANK_SELECT_MASKA;
typedef union VM_L2_BANK_SELECT_MASKB          regVM_L2_BANK_SELECT_MASKB;
typedef union VM_L2_CG                         regVM_L2_CG;
typedef union VM_L2_CNTL2                      regVM_L2_CNTL2;
typedef union VM_L2_CNTL3                      regVM_L2_CNTL3;
typedef union VM_L2_CNTL__CI__VI               regVM_L2_CNTL__CI__VI;
typedef union VM_L2_CNTL__SI                   regVM_L2_CNTL__SI;
typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR;
typedef union VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR;
typedef union VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET;
typedef union VM_L2_STATUS                     regVM_L2_STATUS;
typedef union VM_PRT_APERTURE0_HIGH_ADDR       regVM_PRT_APERTURE0_HIGH_ADDR;
typedef union VM_PRT_APERTURE0_LOW_ADDR        regVM_PRT_APERTURE0_LOW_ADDR;
typedef union VM_PRT_APERTURE1_HIGH_ADDR       regVM_PRT_APERTURE1_HIGH_ADDR;
typedef union VM_PRT_APERTURE1_LOW_ADDR        regVM_PRT_APERTURE1_LOW_ADDR;
typedef union VM_PRT_APERTURE2_HIGH_ADDR       regVM_PRT_APERTURE2_HIGH_ADDR;
typedef union VM_PRT_APERTURE2_LOW_ADDR        regVM_PRT_APERTURE2_LOW_ADDR;
typedef union VM_PRT_APERTURE3_HIGH_ADDR       regVM_PRT_APERTURE3_HIGH_ADDR;
typedef union VM_PRT_APERTURE3_LOW_ADDR        regVM_PRT_APERTURE3_LOW_ADDR;
typedef union VM_PRT_CNTL__CI__VI              regVM_PRT_CNTL__CI__VI;
typedef union VM_PRT_CNTL__SI                  regVM_PRT_CNTL__SI;
typedef union WAKE_ENABLE__SI__VI              regWAKE_ENABLE__SI__VI;
typedef union WALL_CLOCK_COUNTER_ALIAS__SI__VI regWALL_CLOCK_COUNTER_ALIAS__SI__VI;
typedef union WALL_CLOCK_COUNTER__SI__VI       regWALL_CLOCK_COUNTER__SI__VI;
typedef union WD_CNTL_STATUS__CI__VI           regWD_CNTL_STATUS__CI__VI;
typedef union WD_DEBUG_CNTL__CI__VI            regWD_DEBUG_CNTL__CI__VI;
typedef union WD_DEBUG_DATA__CI__VI            regWD_DEBUG_DATA__CI__VI;
typedef union WD_DEBUG_REG0__CI__VI            regWD_DEBUG_REG0__CI__VI;
typedef union WD_DEBUG_REG1__CI__VI            regWD_DEBUG_REG1__CI__VI;
typedef union WD_DEBUG_REG2__CI__VI            regWD_DEBUG_REG2__CI__VI;
typedef union WD_DEBUG_REG3__CI__VI            regWD_DEBUG_REG3__CI__VI;
typedef union WD_DEBUG_REG4__CI__VI            regWD_DEBUG_REG4__CI__VI;
typedef union WD_DEBUG_REG5__CI__VI            regWD_DEBUG_REG5__CI__VI;
typedef union WD_ENHANCE__CI__VI               regWD_ENHANCE__CI__VI;
typedef union WD_PERFCOUNTER0_HI__CI__VI       regWD_PERFCOUNTER0_HI__CI__VI;
typedef union WD_PERFCOUNTER0_LO__CI__VI       regWD_PERFCOUNTER0_LO__CI__VI;
typedef union WD_PERFCOUNTER0_SELECT__CI__VI   regWD_PERFCOUNTER0_SELECT__CI__VI;
typedef union WD_PERFCOUNTER1_HI__CI__VI       regWD_PERFCOUNTER1_HI__CI__VI;
typedef union WD_PERFCOUNTER1_LO__CI__VI       regWD_PERFCOUNTER1_LO__CI__VI;
typedef union WD_PERFCOUNTER1_SELECT__CI__VI   regWD_PERFCOUNTER1_SELECT__CI__VI;
typedef union WD_PERFCOUNTER2_HI__CI__VI       regWD_PERFCOUNTER2_HI__CI__VI;
typedef union WD_PERFCOUNTER2_LO__CI__VI       regWD_PERFCOUNTER2_LO__CI__VI;
typedef union WD_PERFCOUNTER2_SELECT__CI__VI   regWD_PERFCOUNTER2_SELECT__CI__VI;
typedef union WD_PERFCOUNTER3_HI__CI__VI       regWD_PERFCOUNTER3_HI__CI__VI;
typedef union WD_PERFCOUNTER3_LO__CI__VI       regWD_PERFCOUNTER3_LO__CI__VI;
typedef union WD_PERFCOUNTER3_SELECT__CI__VI   regWD_PERFCOUNTER3_SELECT__CI__VI;
typedef union AFMT_AUDIO_DBG_DTO_CNTL__VI      regAFMT_AUDIO_DBG_DTO_CNTL__VI;
typedef union AFMT_AUDIO_SRC_CONTROL__VI       regAFMT_AUDIO_SRC_CONTROL__VI;
typedef union AFMT_GENERIC_0__VI               regAFMT_GENERIC_0__VI;
typedef union AFMT_GENERIC_1__VI               regAFMT_GENERIC_1__VI;
typedef union AFMT_GENERIC_2__VI               regAFMT_GENERIC_2__VI;
typedef union AFMT_GENERIC_3__VI               regAFMT_GENERIC_3__VI;
typedef union AFMT_GENERIC_4__VI               regAFMT_GENERIC_4__VI;
typedef union AFMT_GENERIC_5__VI               regAFMT_GENERIC_5__VI;
typedef union AFMT_GENERIC_6__VI               regAFMT_GENERIC_6__VI;
typedef union AFMT_GENERIC_7__VI               regAFMT_GENERIC_7__VI;
typedef union AFMT_GENERIC_HDR__VI             regAFMT_GENERIC_HDR__VI;
typedef union ALPHA_CONTROL__VI                regALPHA_CONTROL__VI;
typedef union ATC_ATS_FAULT_STATUS_INFO2__VI   regATC_ATS_FAULT_STATUS_INFO2__VI;
typedef union ATC_ATS_SMU_STATUS__VI           regATC_ATS_SMU_STATUS__VI;
typedef union ATC_ATS_VMID_STATUS__VI          regATC_ATS_VMID_STATUS__VI;
typedef union ATC_L1RD_DEBUG2_TLB__VI          regATC_L1RD_DEBUG2_TLB__VI;
typedef union ATC_L1WR_DEBUG2_TLB__VI          regATC_L1WR_DEBUG2_TLB__VI;
typedef union ATC_L2_CACHE_DATA0__VI           regATC_L2_CACHE_DATA0__VI;
typedef union ATC_L2_CACHE_DATA1__VI           regATC_L2_CACHE_DATA1__VI;
typedef union ATC_L2_CACHE_DATA2__VI           regATC_L2_CACHE_DATA2__VI;
typedef union ATC_L2_CNTL3__VI                 regATC_L2_CNTL3__VI;
typedef union ATC_L2_STATUS__VI                regATC_L2_STATUS__VI;
typedef union ATC_L2_STATUS2__VI               regATC_L2_STATUS2__VI;
typedef union AUX_GTC_SYNC_CONTROL__VI         regAUX_GTC_SYNC_CONTROL__VI;
typedef union AUX_GTC_SYNC_CONTROLLER_STATUS__VI regAUX_GTC_SYNC_CONTROLLER_STATUS__VI;
typedef union AUX_GTC_SYNC_DATA__VI            regAUX_GTC_SYNC_DATA__VI;
typedef union AUX_GTC_SYNC_ERROR_CONTROL__VI   regAUX_GTC_SYNC_ERROR_CONTROL__VI;
typedef union AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI regAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__VI;
typedef union AUX_GTC_SYNC_STATUS__VI          regAUX_GTC_SYNC_STATUS__VI;
typedef union AUX_TEST_DEBUG_DATA__VI          regAUX_TEST_DEBUG_DATA__VI;
typedef union AUX_TEST_DEBUG_INDEX__VI         regAUX_TEST_DEBUG_INDEX__VI;
typedef union AVSYNC_COUNTER_CONTROL__VI       regAVSYNC_COUNTER_CONTROL__VI;
typedef union AVSYNC_COUNTER_READ__VI          regAVSYNC_COUNTER_READ__VI;
typedef union AVSYNC_COUNTER_WRITE__VI         regAVSYNC_COUNTER_WRITE__VI;
typedef union AZALIA_CONTROLLER_CLOCK_GATING__VI regAZALIA_CONTROLLER_CLOCK_GATING__VI;
typedef union AZALIA_CONTROLLER_DEBUG__VI      regAZALIA_CONTROLLER_DEBUG__VI;
typedef union AZALIA_CRC0_CHANNEL0__VI         regAZALIA_CRC0_CHANNEL0__VI;
typedef union AZALIA_CRC0_CHANNEL1__VI         regAZALIA_CRC0_CHANNEL1__VI;
typedef union AZALIA_CRC0_CHANNEL2__VI         regAZALIA_CRC0_CHANNEL2__VI;
typedef union AZALIA_CRC0_CHANNEL3__VI         regAZALIA_CRC0_CHANNEL3__VI;
typedef union AZALIA_CRC0_CHANNEL4__VI         regAZALIA_CRC0_CHANNEL4__VI;
typedef union AZALIA_CRC0_CHANNEL5__VI         regAZALIA_CRC0_CHANNEL5__VI;
typedef union AZALIA_CRC0_CHANNEL6__VI         regAZALIA_CRC0_CHANNEL6__VI;
typedef union AZALIA_CRC0_CHANNEL7__VI         regAZALIA_CRC0_CHANNEL7__VI;
typedef union AZALIA_CRC0_CONTROL0__VI         regAZALIA_CRC0_CONTROL0__VI;
typedef union AZALIA_CRC0_CONTROL1__VI         regAZALIA_CRC0_CONTROL1__VI;
typedef union AZALIA_CRC0_CONTROL2__VI         regAZALIA_CRC0_CONTROL2__VI;
typedef union AZALIA_CRC0_CONTROL3__VI         regAZALIA_CRC0_CONTROL3__VI;
typedef union AZALIA_CRC0_RESULT__VI           regAZALIA_CRC0_RESULT__VI;
typedef union AZALIA_CRC1_CHANNEL0__VI         regAZALIA_CRC1_CHANNEL0__VI;
typedef union AZALIA_CRC1_CHANNEL1__VI         regAZALIA_CRC1_CHANNEL1__VI;
typedef union AZALIA_CRC1_CHANNEL2__VI         regAZALIA_CRC1_CHANNEL2__VI;
typedef union AZALIA_CRC1_CHANNEL3__VI         regAZALIA_CRC1_CHANNEL3__VI;
typedef union AZALIA_CRC1_CHANNEL4__VI         regAZALIA_CRC1_CHANNEL4__VI;
typedef union AZALIA_CRC1_CHANNEL5__VI         regAZALIA_CRC1_CHANNEL5__VI;
typedef union AZALIA_CRC1_CHANNEL6__VI         regAZALIA_CRC1_CHANNEL6__VI;
typedef union AZALIA_CRC1_CHANNEL7__VI         regAZALIA_CRC1_CHANNEL7__VI;
typedef union AZALIA_CRC1_CONTROL0__VI         regAZALIA_CRC1_CONTROL0__VI;
typedef union AZALIA_CRC1_CONTROL1__VI         regAZALIA_CRC1_CONTROL1__VI;
typedef union AZALIA_CRC1_CONTROL2__VI         regAZALIA_CRC1_CONTROL2__VI;
typedef union AZALIA_CRC1_CONTROL3__VI         regAZALIA_CRC1_CONTROL3__VI;
typedef union AZALIA_CRC1_RESULT__VI           regAZALIA_CRC1_RESULT__VI;
typedef union AZALIA_F0_AUDIO_DISABLED_INT_STATUS__VI regAZALIA_F0_AUDIO_DISABLED_INT_STATUS__VI;
typedef union AZALIA_F0_AUDIO_ENABLED_INT_STATUS__VI regAZALIA_F0_AUDIO_ENABLED_INT_STATUS__VI;
typedef union AZALIA_F0_AUDIO_ENABLE_STATUS__VI regAZALIA_F0_AUDIO_ENABLE_STATUS__VI;
typedef union AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__VI regAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__VI;
typedef union AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__VI regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI regAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI regAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI regAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__VI regAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI regAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__VI regAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__VI regAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__VI regAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI regAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI regAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__VI regAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__VI;
typedef union AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__VI regAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__VI;
typedef union AZALIA_F0_CODEC_DEBUG__VI        regAZALIA_F0_CODEC_DEBUG__VI;
typedef union AZALIA_F0_CODEC_ENDPOINT_DATA__VI regAZALIA_F0_CODEC_ENDPOINT_DATA__VI;
typedef union AZALIA_F0_CODEC_ENDPOINT_INDEX__VI regAZALIA_F0_CODEC_ENDPOINT_INDEX__VI;
typedef union AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI;
typedef union AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__VI regAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__VI;
typedef union AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI regAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__VI;
typedef union AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI regAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI regAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI regAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI;
typedef union AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__VI regAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__VI regAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__VI regAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__VI regAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI regAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI regAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__VI regAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_LPIB__VI regAZALIA_F0_CODEC_PIN_CONTROL_LPIB__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI regAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI regAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__VI regAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI regAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI regAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI regAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI regAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__VI regAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VI regAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI regAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__VI regAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI regAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__VI;
typedef union AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI regAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI;
typedef union AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VI regAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VI;
typedef union AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__VI regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET0__VI  regAZALIA_F0_GTC_GROUP_OFFSET0__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET1__VI  regAZALIA_F0_GTC_GROUP_OFFSET1__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET2__VI  regAZALIA_F0_GTC_GROUP_OFFSET2__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET3__VI  regAZALIA_F0_GTC_GROUP_OFFSET3__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET4__VI  regAZALIA_F0_GTC_GROUP_OFFSET4__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET5__VI  regAZALIA_F0_GTC_GROUP_OFFSET5__VI;
typedef union AZALIA_F0_GTC_GROUP_OFFSET6__VI  regAZALIA_F0_GTC_GROUP_OFFSET6__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI;
typedef union AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI regAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI regAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI regAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI regAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI;
typedef union AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__VI regAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__VI;
typedef union AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI regAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__VI;
typedef union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI regAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__VI;
typedef union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI regAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__VI;
typedef union AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI regAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VI;
typedef union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI regAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__VI;
typedef union AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI regAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI regAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI regAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VI;
typedef union AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__VI regAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__VI regAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__VI regAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__VI regAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__VI regAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__VI regAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__VI regAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI regAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__VI regAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI regAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_HBR__VI regAZALIA_F2_CODEC_PIN_CONTROL_HBR__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VI regAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_LPIB__VI regAZALIA_F2_CODEC_PIN_CONTROL_LPIB__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI regAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI regAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__VI regAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI regAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__VI regAZALIA_F2_CODEC_PIN_CONTROL_PORTID0__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__VI regAZALIA_F2_CODEC_PIN_CONTROL_PORTID1__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__VI regAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI regAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__VI regAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__VI regAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI regAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI regAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__VI;
typedef union AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI regAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__VI;
typedef union AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI regAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__VI;
typedef union AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VI regAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VI;
typedef union AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__VI regAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__VI;
typedef union AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI regAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__VI;
typedef union AZALIA_FIFO_SIZE_CONTROL__VI     regAZALIA_FIFO_SIZE_CONTROL__VI;
typedef union AZALIA_GLOBAL_CAPABILITIES__VI   regAZALIA_GLOBAL_CAPABILITIES__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL0__VI   regAZALIA_INPUT_CRC0_CHANNEL0__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL1__VI   regAZALIA_INPUT_CRC0_CHANNEL1__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL2__VI   regAZALIA_INPUT_CRC0_CHANNEL2__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL3__VI   regAZALIA_INPUT_CRC0_CHANNEL3__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL4__VI   regAZALIA_INPUT_CRC0_CHANNEL4__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL5__VI   regAZALIA_INPUT_CRC0_CHANNEL5__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL6__VI   regAZALIA_INPUT_CRC0_CHANNEL6__VI;
typedef union AZALIA_INPUT_CRC0_CHANNEL7__VI   regAZALIA_INPUT_CRC0_CHANNEL7__VI;
typedef union AZALIA_INPUT_CRC0_CONTROL0__VI   regAZALIA_INPUT_CRC0_CONTROL0__VI;
typedef union AZALIA_INPUT_CRC0_CONTROL1__VI   regAZALIA_INPUT_CRC0_CONTROL1__VI;
typedef union AZALIA_INPUT_CRC0_CONTROL2__VI   regAZALIA_INPUT_CRC0_CONTROL2__VI;
typedef union AZALIA_INPUT_CRC0_CONTROL3__VI   regAZALIA_INPUT_CRC0_CONTROL3__VI;
typedef union AZALIA_INPUT_CRC0_RESULT__VI     regAZALIA_INPUT_CRC0_RESULT__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL0__VI   regAZALIA_INPUT_CRC1_CHANNEL0__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL1__VI   regAZALIA_INPUT_CRC1_CHANNEL1__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL2__VI   regAZALIA_INPUT_CRC1_CHANNEL2__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL3__VI   regAZALIA_INPUT_CRC1_CHANNEL3__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL4__VI   regAZALIA_INPUT_CRC1_CHANNEL4__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL5__VI   regAZALIA_INPUT_CRC1_CHANNEL5__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL6__VI   regAZALIA_INPUT_CRC1_CHANNEL6__VI;
typedef union AZALIA_INPUT_CRC1_CHANNEL7__VI   regAZALIA_INPUT_CRC1_CHANNEL7__VI;
typedef union AZALIA_INPUT_CRC1_CONTROL0__VI   regAZALIA_INPUT_CRC1_CONTROL0__VI;
typedef union AZALIA_INPUT_CRC1_CONTROL1__VI   regAZALIA_INPUT_CRC1_CONTROL1__VI;
typedef union AZALIA_INPUT_CRC1_CONTROL2__VI   regAZALIA_INPUT_CRC1_CONTROL2__VI;
typedef union AZALIA_INPUT_CRC1_CONTROL3__VI   regAZALIA_INPUT_CRC1_CONTROL3__VI;
typedef union AZALIA_INPUT_CRC1_RESULT__VI     regAZALIA_INPUT_CRC1_RESULT__VI;
typedef union AZALIA_INPUT_PAYLOAD_CAPABILITY__VI regAZALIA_INPUT_PAYLOAD_CAPABILITY__VI;
typedef union AZALIA_MEM_PWR_CTRL__VI          regAZALIA_MEM_PWR_CTRL__VI;
typedef union AZALIA_MEM_PWR_STATUS__VI        regAZALIA_MEM_PWR_STATUS__VI;
typedef union AZALIA_OUTPUT_PAYLOAD_CAPABILITY__VI regAZALIA_OUTPUT_PAYLOAD_CAPABILITY__VI;
typedef union AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__VI regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL__VI;
typedef union AZALIA_SCLK_CONTROL__VI          regAZALIA_SCLK_CONTROL__VI;
typedef union AZALIA_STREAM_DATA__VI           regAZALIA_STREAM_DATA__VI;
typedef union AZALIA_STREAM_DEBUG__VI          regAZALIA_STREAM_DEBUG__VI;
typedef union AZALIA_STREAM_INDEX__VI          regAZALIA_STREAM_INDEX__VI;
typedef union AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__VI regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__VI;
typedef union AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__VI regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__VI;
typedef union AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI;
typedef union AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI;
typedef union AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__VI;
typedef union AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__VI;
typedef union BF_ANA_ISO_CNTL__VI              regBF_ANA_ISO_CNTL__VI;
typedef union BIF_ATOMIC_ERR_LOG__VI           regBIF_ATOMIC_ERR_LOG__VI;
typedef union BIF_BME_STATUS__VI               regBIF_BME_STATUS__VI;
typedef union BIF_CLK_CTRL__VI                 regBIF_CLK_CTRL__VI;
typedef union BIF_DOORBELL_APER_EN__VI         regBIF_DOORBELL_APER_EN__VI;
typedef union BIF_DOORBELL_GBLAPER1_LOWER__VI  regBIF_DOORBELL_GBLAPER1_LOWER__VI;
typedef union BIF_DOORBELL_GBLAPER1_UPPER__VI  regBIF_DOORBELL_GBLAPER1_UPPER__VI;
typedef union BIF_DOORBELL_GBLAPER2_LOWER__VI  regBIF_DOORBELL_GBLAPER2_LOWER__VI;
typedef union BIF_DOORBELL_GBLAPER2_UPPER__VI  regBIF_DOORBELL_GBLAPER2_UPPER__VI;
typedef union BIF_GPUIOV_FB_TOTAL_FB_INFO__VI  regBIF_GPUIOV_FB_TOTAL_FB_INFO__VI;
typedef union BIF_GPUIOV_RESET_NOTIFICATION__VI regBIF_GPUIOV_RESET_NOTIFICATION__VI;
typedef union BIF_GPUIOV_VM_INIT_STATUS__VI    regBIF_GPUIOV_VM_INIT_STATUS__VI;
typedef union BIF_IOV_FUNC_IDENTIFIER__VI      regBIF_IOV_FUNC_IDENTIFIER__VI;
typedef union BIF_MM_INDACCESS_CNTL__VI        regBIF_MM_INDACCESS_CNTL__VI;
typedef union BIF_MST_TRANS_PENDING__VI        regBIF_MST_TRANS_PENDING__VI;
typedef union BIF_RB_BASE__VI                  regBIF_RB_BASE__VI;
typedef union BIF_RB_CNTL__VI                  regBIF_RB_CNTL__VI;
typedef union BIF_RB_RPTR__VI                  regBIF_RB_RPTR__VI;
typedef union BIF_RB_WPTR__VI                  regBIF_RB_WPTR__VI;
typedef union BIF_RB_WPTR_ADDR_HI__VI          regBIF_RB_WPTR_ADDR_HI__VI;
typedef union BIF_RB_WPTR_ADDR_LO__VI          regBIF_RB_WPTR_ADDR_LO__VI;
typedef union BIF_RFE_MST_SMBUS_CMDSTATUS__VI  regBIF_RFE_MST_SMBUS_CMDSTATUS__VI;
typedef union BIF_RFE_WARMRST_CNTL__VI         regBIF_RFE_WARMRST_CNTL__VI;
typedef union BIF_RLC_INTR_CNTL__VI            regBIF_RLC_INTR_CNTL__VI;
typedef union BIF_SLV_TRANS_PENDING__VI        regBIF_SLV_TRANS_PENDING__VI;
typedef union BIF_SMU_DATA__VI                 regBIF_SMU_DATA__VI;
typedef union BIF_SMU_INDEX__VI                regBIF_SMU_INDEX__VI;
typedef union BIF_VDDGFX_FB_CMP__VI            regBIF_VDDGFX_FB_CMP__VI;
typedef union BIF_VDDGFX_GFX0_LOWER__VI        regBIF_VDDGFX_GFX0_LOWER__VI;
typedef union BIF_VDDGFX_GFX0_UPPER__VI        regBIF_VDDGFX_GFX0_UPPER__VI;
typedef union BIF_VDDGFX_GFX1_LOWER__VI        regBIF_VDDGFX_GFX1_LOWER__VI;
typedef union BIF_VDDGFX_GFX1_UPPER__VI        regBIF_VDDGFX_GFX1_UPPER__VI;
typedef union BIF_VDDGFX_GFX2_LOWER__VI        regBIF_VDDGFX_GFX2_LOWER__VI;
typedef union BIF_VDDGFX_GFX2_UPPER__VI        regBIF_VDDGFX_GFX2_UPPER__VI;
typedef union BIF_VDDGFX_GFX3_LOWER__VI        regBIF_VDDGFX_GFX3_LOWER__VI;
typedef union BIF_VDDGFX_GFX3_UPPER__VI        regBIF_VDDGFX_GFX3_UPPER__VI;
typedef union BIF_VDDGFX_GFX4_LOWER__VI        regBIF_VDDGFX_GFX4_LOWER__VI;
typedef union BIF_VDDGFX_GFX4_UPPER__VI        regBIF_VDDGFX_GFX4_UPPER__VI;
typedef union BIF_VDDGFX_GFX5_LOWER__VI        regBIF_VDDGFX_GFX5_LOWER__VI;
typedef union BIF_VDDGFX_GFX5_UPPER__VI        regBIF_VDDGFX_GFX5_UPPER__VI;
typedef union BIF_VDDGFX_RSV1_LOWER__VI        regBIF_VDDGFX_RSV1_LOWER__VI;
typedef union BIF_VDDGFX_RSV1_UPPER__VI        regBIF_VDDGFX_RSV1_UPPER__VI;
typedef union BIF_VDDGFX_RSV2_LOWER__VI        regBIF_VDDGFX_RSV2_LOWER__VI;
typedef union BIF_VDDGFX_RSV2_UPPER__VI        regBIF_VDDGFX_RSV2_UPPER__VI;
typedef union BIF_VDDGFX_RSV3_LOWER__VI        regBIF_VDDGFX_RSV3_LOWER__VI;
typedef union BIF_VDDGFX_RSV3_UPPER__VI        regBIF_VDDGFX_RSV3_UPPER__VI;
typedef union BIF_VDDGFX_RSV4_LOWER__VI        regBIF_VDDGFX_RSV4_LOWER__VI;
typedef union BIF_VDDGFX_RSV4_UPPER__VI        regBIF_VDDGFX_RSV4_UPPER__VI;
typedef union BIF_VIRT_RESET_REQ__VI           regBIF_VIRT_RESET_REQ__VI;
typedef union BLND_CONTROL__VI                 regBLND_CONTROL__VI;
typedef union BLND_CONTROL2__VI                regBLND_CONTROL2__VI;
typedef union BLND_DEBUG__VI                   regBLND_DEBUG__VI;
typedef union BLND_REG_UPDATE_STATUS__VI       regBLND_REG_UPDATE_STATUS__VI;
typedef union BLND_TEST_DEBUG_DATA__VI         regBLND_TEST_DEBUG_DATA__VI;
typedef union BLND_TEST_DEBUG_INDEX__VI        regBLND_TEST_DEBUG_INDEX__VI;
typedef union BLND_UNDERFLOW_INTERRUPT__VI     regBLND_UNDERFLOW_INTERRUPT__VI;
typedef union BLND_UPDATE__VI                  regBLND_UPDATE__VI;
typedef union BLND_V_UPDATE_LOCK__VI           regBLND_V_UPDATE_LOCK__VI;
typedef union BPHYC_DAC_AUTO_CALIB_CONTROL__VI regBPHYC_DAC_AUTO_CALIB_CONTROL__VI;
typedef union BPHYC_DAC_MACRO_CNTL__VI         regBPHYC_DAC_MACRO_CNTL__VI;
typedef union BX_RESET_CNTL__VI                regBX_RESET_CNTL__VI;
typedef union CB_COLOR0_DCC_BASE__VI           regCB_COLOR0_DCC_BASE__VI;
typedef union CB_COLOR0_DCC_CONTROL__VI        regCB_COLOR0_DCC_CONTROL__VI;
typedef union CB_COLOR1_DCC_BASE__VI           regCB_COLOR1_DCC_BASE__VI;
typedef union CB_COLOR1_DCC_CONTROL__VI        regCB_COLOR1_DCC_CONTROL__VI;
typedef union CB_COLOR2_DCC_BASE__VI           regCB_COLOR2_DCC_BASE__VI;
typedef union CB_COLOR2_DCC_CONTROL__VI        regCB_COLOR2_DCC_CONTROL__VI;
typedef union CB_COLOR3_DCC_BASE__VI           regCB_COLOR3_DCC_BASE__VI;
typedef union CB_COLOR3_DCC_CONTROL__VI        regCB_COLOR3_DCC_CONTROL__VI;
typedef union CB_COLOR4_DCC_BASE__VI           regCB_COLOR4_DCC_BASE__VI;
typedef union CB_COLOR4_DCC_CONTROL__VI        regCB_COLOR4_DCC_CONTROL__VI;
typedef union CB_COLOR5_DCC_BASE__VI           regCB_COLOR5_DCC_BASE__VI;
typedef union CB_COLOR5_DCC_CONTROL__VI        regCB_COLOR5_DCC_CONTROL__VI;
typedef union CB_COLOR6_DCC_BASE__VI           regCB_COLOR6_DCC_BASE__VI;
typedef union CB_COLOR6_DCC_CONTROL__VI        regCB_COLOR6_DCC_CONTROL__VI;
typedef union CB_COLOR7_DCC_BASE__VI           regCB_COLOR7_DCC_BASE__VI;
typedef union CB_COLOR7_DCC_CONTROL__VI        regCB_COLOR7_DCC_CONTROL__VI;
typedef union CB_DCC_CONFIG__VI                regCB_DCC_CONFIG__VI;
typedef union CB_DCC_CONTROL__VI               regCB_DCC_CONTROL__VI;
typedef union CB_DEBUG_BUS_19__VI              regCB_DEBUG_BUS_19__VI;
typedef union CB_DEBUG_BUS_20__VI              regCB_DEBUG_BUS_20__VI;
typedef union CB_DEBUG_BUS_21__VI              regCB_DEBUG_BUS_21__VI;
typedef union CB_DEBUG_BUS_22__VI              regCB_DEBUG_BUS_22__VI;
typedef union CC_DC_PIPE_DIS__VI               regCC_DC_PIPE_DIS__VI;
typedef union CC_FCTRL_FUSES__VI               regCC_FCTRL_FUSES__VI;
typedef union CC_GC_SHADER_RATE_CONFIG__VI     regCC_GC_SHADER_RATE_CONFIG__VI;
typedef union CC_HARVEST_FUSES__VI             regCC_HARVEST_FUSES__VI;
typedef union CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__VI regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__VI;
typedef union CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__VI regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY__VI;
typedef union CFG_LNC_WINDOW__VI               regCFG_LNC_WINDOW__VI;
typedef union CG_CLKPIN_CNTL_DC__VI            regCG_CLKPIN_CNTL_DC__VI;
typedef union CG_MCLK_CNTL__VI                 regCG_MCLK_CNTL__VI;
typedef union CG_MCLK_STATUS__VI               regCG_MCLK_STATUS__VI;
typedef union CG_SPLL_FUNC_CNTL_7__VI          regCG_SPLL_FUNC_CNTL_7__VI;
typedef union CLIENT0_OFFSET_HI__VI            regCLIENT0_OFFSET_HI__VI;
typedef union CLIENT1_OFFSET_HI__VI            regCLIENT1_OFFSET_HI__VI;
typedef union CLIENT2_OFFSET_HI__VI            regCLIENT2_OFFSET_HI__VI;
typedef union CLIENT3_BM__VI                   regCLIENT3_BM__VI;
typedef union CLIENT3_CD0__VI                  regCLIENT3_CD0__VI;
typedef union CLIENT3_CD1__VI                  regCLIENT3_CD1__VI;
typedef union CLIENT3_CD2__VI                  regCLIENT3_CD2__VI;
typedef union CLIENT3_CD3__VI                  regCLIENT3_CD3__VI;
typedef union CLIENT3_CK0__VI                  regCLIENT3_CK0__VI;
typedef union CLIENT3_CK1__VI                  regCLIENT3_CK1__VI;
typedef union CLIENT3_CK2__VI                  regCLIENT3_CK2__VI;
typedef union CLIENT3_CK3__VI                  regCLIENT3_CK3__VI;
typedef union CLIENT3_K0__VI                   regCLIENT3_K0__VI;
typedef union CLIENT3_K1__VI                   regCLIENT3_K1__VI;
typedef union CLIENT3_K2__VI                   regCLIENT3_K2__VI;
typedef union CLIENT3_K3__VI                   regCLIENT3_K3__VI;
typedef union CLIENT3_OFFSET__VI               regCLIENT3_OFFSET__VI;
typedef union CLIENT3_OFFSET_HI__VI            regCLIENT3_OFFSET_HI__VI;
typedef union CLIENT3_STATUS__VI               regCLIENT3_STATUS__VI;
typedef union CLIENT4_BM__VI                   regCLIENT4_BM__VI;
typedef union CLIENT4_CD0__VI                  regCLIENT4_CD0__VI;
typedef union CLIENT4_CD1__VI                  regCLIENT4_CD1__VI;
typedef union CLIENT4_CD2__VI                  regCLIENT4_CD2__VI;
typedef union CLIENT4_CD3__VI                  regCLIENT4_CD3__VI;
typedef union CLIENT4_CK0__VI                  regCLIENT4_CK0__VI;
typedef union CLIENT4_CK1__VI                  regCLIENT4_CK1__VI;
typedef union CLIENT4_CK2__VI                  regCLIENT4_CK2__VI;
typedef union CLIENT4_CK3__VI                  regCLIENT4_CK3__VI;
typedef union CLIENT4_K0__VI                   regCLIENT4_K0__VI;
typedef union CLIENT4_K1__VI                   regCLIENT4_K1__VI;
typedef union CLIENT4_K2__VI                   regCLIENT4_K2__VI;
typedef union CLIENT4_K3__VI                   regCLIENT4_K3__VI;
typedef union CLIENT4_OFFSET__VI               regCLIENT4_OFFSET__VI;
typedef union CLIENT4_OFFSET_HI__VI            regCLIENT4_OFFSET_HI__VI;
typedef union CLIENT4_STATUS__VI               regCLIENT4_STATUS__VI;
typedef union CLKREQB_PERF_COUNTER__VI         regCLKREQB_PERF_COUNTER__VI;
typedef union CNV_CSC_C11_C12__VI              regCNV_CSC_C11_C12__VI;
typedef union CNV_CSC_C13_C14__VI              regCNV_CSC_C13_C14__VI;
typedef union CNV_CSC_C21_C22__VI              regCNV_CSC_C21_C22__VI;
typedef union CNV_CSC_C23_C24__VI              regCNV_CSC_C23_C24__VI;
typedef union CNV_CSC_C31_C32__VI              regCNV_CSC_C31_C32__VI;
typedef union CNV_CSC_C33_C34__VI              regCNV_CSC_C33_C34__VI;
typedef union CNV_CSC_CLAMP_B__VI              regCNV_CSC_CLAMP_B__VI;
typedef union CNV_CSC_CLAMP_G__VI              regCNV_CSC_CLAMP_G__VI;
typedef union CNV_CSC_CLAMP_R__VI              regCNV_CSC_CLAMP_R__VI;
typedef union CNV_CSC_CONTROL__VI              regCNV_CSC_CONTROL__VI;
typedef union CNV_CSC_ROUND_OFFSET_B__VI       regCNV_CSC_ROUND_OFFSET_B__VI;
typedef union CNV_CSC_ROUND_OFFSET_G__VI       regCNV_CSC_ROUND_OFFSET_G__VI;
typedef union CNV_CSC_ROUND_OFFSET_R__VI       regCNV_CSC_ROUND_OFFSET_R__VI;
typedef union CNV_INPUT_SELECT__VI             regCNV_INPUT_SELECT__VI;
typedef union CNV_MODE__VI                     regCNV_MODE__VI;
typedef union CNV_SOURCE_SIZE__VI              regCNV_SOURCE_SIZE__VI;
typedef union CNV_TEST_CNTL__VI                regCNV_TEST_CNTL__VI;
typedef union CNV_TEST_CRC_BLUE__VI            regCNV_TEST_CRC_BLUE__VI;
typedef union CNV_TEST_CRC_GREEN__VI           regCNV_TEST_CRC_GREEN__VI;
typedef union CNV_TEST_CRC_RED__VI             regCNV_TEST_CRC_RED__VI;
typedef union CNV_TEST_DEBUG_DATA__VI          regCNV_TEST_DEBUG_DATA__VI;
typedef union CNV_TEST_DEBUG_INDEX__VI         regCNV_TEST_DEBUG_INDEX__VI;
typedef union CNV_UPDATE__VI                   regCNV_UPDATE__VI;
typedef union CNV_WINDOW_SIZE__VI              regCNV_WINDOW_SIZE__VI;
typedef union CNV_WINDOW_START__VI             regCNV_WINDOW_START__VI;
typedef union COL_MAN_DEBUG_CONTROL__VI        regCOL_MAN_DEBUG_CONTROL__VI;
typedef union COL_MAN_FP_CONVERTED_FIELD__VI   regCOL_MAN_FP_CONVERTED_FIELD__VI;
typedef union COL_MAN_INPUT_CSC_CONTROL__VI    regCOL_MAN_INPUT_CSC_CONTROL__VI;
typedef union COL_MAN_OUTPUT_CSC_CONTROL__VI   regCOL_MAN_OUTPUT_CSC_CONTROL__VI;
typedef union COL_MAN_TEST_DEBUG_DATA__VI      regCOL_MAN_TEST_DEBUG_DATA__VI;
typedef union COL_MAN_TEST_DEBUG_INDEX__VI     regCOL_MAN_TEST_DEBUG_INDEX__VI;
typedef union COL_MAN_UPDATE__VI               regCOL_MAN_UPDATE__VI;
typedef union COMM_MATRIXA_TRANS_C11_C12__VI   regCOMM_MATRIXA_TRANS_C11_C12__VI;
typedef union COMM_MATRIXA_TRANS_C13_C14__VI   regCOMM_MATRIXA_TRANS_C13_C14__VI;
typedef union COMM_MATRIXA_TRANS_C21_C22__VI   regCOMM_MATRIXA_TRANS_C21_C22__VI;
typedef union COMM_MATRIXA_TRANS_C23_C24__VI   regCOMM_MATRIXA_TRANS_C23_C24__VI;
typedef union COMM_MATRIXA_TRANS_C31_C32__VI   regCOMM_MATRIXA_TRANS_C31_C32__VI;
typedef union COMM_MATRIXA_TRANS_C33_C34__VI   regCOMM_MATRIXA_TRANS_C33_C34__VI;
typedef union COMM_MATRIXB_TRANS_C11_C12__VI   regCOMM_MATRIXB_TRANS_C11_C12__VI;
typedef union COMM_MATRIXB_TRANS_C13_C14__VI   regCOMM_MATRIXB_TRANS_C13_C14__VI;
typedef union COMM_MATRIXB_TRANS_C21_C22__VI   regCOMM_MATRIXB_TRANS_C21_C22__VI;
typedef union COMM_MATRIXB_TRANS_C23_C24__VI   regCOMM_MATRIXB_TRANS_C23_C24__VI;
typedef union COMM_MATRIXB_TRANS_C31_C32__VI   regCOMM_MATRIXB_TRANS_C31_C32__VI;
typedef union COMM_MATRIXB_TRANS_C33_C34__VI   regCOMM_MATRIXB_TRANS_C33_C34__VI;
typedef union COMPUTE_DISPATCH_ID__VI          regCOMPUTE_DISPATCH_ID__VI;
typedef union COMPUTE_NOWHERE__VI              regCOMPUTE_NOWHERE__VI;
typedef union COMPUTE_RELAUNCH__VI             regCOMPUTE_RELAUNCH__VI;
typedef union COMPUTE_THREADGROUP_ID__VI       regCOMPUTE_THREADGROUP_ID__VI;
typedef union COMPUTE_WAVE_RESTORE_ADDR_HI__VI regCOMPUTE_WAVE_RESTORE_ADDR_HI__VI;
typedef union COMPUTE_WAVE_RESTORE_ADDR_LO__VI regCOMPUTE_WAVE_RESTORE_ADDR_LO__VI;
typedef union COMPUTE_WAVE_RESTORE_CONTROL__VI regCOMPUTE_WAVE_RESTORE_CONTROL__VI;
typedef union CONFIG_RESERVED__VI              regCONFIG_RESERVED__VI;
typedef union CPLL_MACRO_CNTL_RESERVED0__VI    regCPLL_MACRO_CNTL_RESERVED0__VI;
typedef union CPLL_MACRO_CNTL_RESERVED1__VI    regCPLL_MACRO_CNTL_RESERVED1__VI;
typedef union CPLL_MACRO_CNTL_RESERVED10__VI   regCPLL_MACRO_CNTL_RESERVED10__VI;
typedef union CPLL_MACRO_CNTL_RESERVED11__VI   regCPLL_MACRO_CNTL_RESERVED11__VI;
typedef union CPLL_MACRO_CNTL_RESERVED2__VI    regCPLL_MACRO_CNTL_RESERVED2__VI;
typedef union CPLL_MACRO_CNTL_RESERVED3__VI    regCPLL_MACRO_CNTL_RESERVED3__VI;
typedef union CPLL_MACRO_CNTL_RESERVED4__VI    regCPLL_MACRO_CNTL_RESERVED4__VI;
typedef union CPLL_MACRO_CNTL_RESERVED5__VI    regCPLL_MACRO_CNTL_RESERVED5__VI;
typedef union CPLL_MACRO_CNTL_RESERVED6__VI    regCPLL_MACRO_CNTL_RESERVED6__VI;
typedef union CPLL_MACRO_CNTL_RESERVED7__VI    regCPLL_MACRO_CNTL_RESERVED7__VI;
typedef union CPLL_MACRO_CNTL_RESERVED8__VI    regCPLL_MACRO_CNTL_RESERVED8__VI;
typedef union CPLL_MACRO_CNTL_RESERVED9__VI    regCPLL_MACRO_CNTL_RESERVED9__VI;
typedef union CPM_CONTROL__VI                  regCPM_CONTROL__VI;
typedef union CP_CE_COMPLETION_STATUS__VI      regCP_CE_COMPLETION_STATUS__VI;
typedef union CP_CE_METADATA_BASE_ADDR__VI     regCP_CE_METADATA_BASE_ADDR__VI;
typedef union CP_CE_METADATA_BASE_ADDR_HI__VI  regCP_CE_METADATA_BASE_ADDR_HI__VI;
typedef union CP_CE_RB_OFFSET__VI              regCP_CE_RB_OFFSET__VI;
typedef union CP_CPC_IC_BASE_CNTL__VI          regCP_CPC_IC_BASE_CNTL__VI;
typedef union CP_CPC_IC_BASE_HI__VI            regCP_CPC_IC_BASE_HI__VI;
typedef union CP_CPC_IC_BASE_LO__VI            regCP_CPC_IC_BASE_LO__VI;
typedef union CP_CPC_IC_OP_CNTL__VI            regCP_CPC_IC_OP_CNTL__VI;
typedef union CP_CPC_MGCG_SYNC_CNTL__VI        regCP_CPC_MGCG_SYNC_CNTL__VI;
typedef union CP_DFY_CMD__VI                   regCP_DFY_CMD__VI;
typedef union CP_DISPATCH_INDR_ADDR__VI        regCP_DISPATCH_INDR_ADDR__VI;
typedef union CP_DISPATCH_INDR_ADDR_HI__VI     regCP_DISPATCH_INDR_ADDR_HI__VI;
typedef union CP_DRAW_INDX_INDR_ADDR__VI       regCP_DRAW_INDX_INDR_ADDR__VI;
typedef union CP_DRAW_INDX_INDR_ADDR_HI__VI    regCP_DRAW_INDX_INDR_ADDR_HI__VI;
typedef union CP_DRAW_OBJECT__VI               regCP_DRAW_OBJECT__VI;
typedef union CP_DRAW_OBJECT_COUNTER__VI       regCP_DRAW_OBJECT_COUNTER__VI;
typedef union CP_DRAW_WINDOW_CNTL__VI          regCP_DRAW_WINDOW_CNTL__VI;
typedef union CP_DRAW_WINDOW_HI__VI            regCP_DRAW_WINDOW_HI__VI;
typedef union CP_DRAW_WINDOW_LO__VI            regCP_DRAW_WINDOW_LO__VI;
typedef union CP_DRAW_WINDOW_MASK_HI__VI       regCP_DRAW_WINDOW_MASK_HI__VI;
typedef union CP_EOP_DONE_CNTX_ID__VI          regCP_EOP_DONE_CNTX_ID__VI;
typedef union CP_GDS_BKUP_ADDR__VI             regCP_GDS_BKUP_ADDR__VI;
typedef union CP_GDS_BKUP_ADDR_HI__VI          regCP_GDS_BKUP_ADDR_HI__VI;
typedef union CP_HPD_STATUS0__VI               regCP_HPD_STATUS0__VI;
typedef union CP_HQD_CNTL_STACK_OFFSET__VI     regCP_HQD_CNTL_STACK_OFFSET__VI;
typedef union CP_HQD_CNTL_STACK_SIZE__VI       regCP_HQD_CNTL_STACK_SIZE__VI;
typedef union CP_HQD_CTX_SAVE_BASE_ADDR_HI__VI regCP_HQD_CTX_SAVE_BASE_ADDR_HI__VI;
typedef union CP_HQD_CTX_SAVE_BASE_ADDR_LO__VI regCP_HQD_CTX_SAVE_BASE_ADDR_LO__VI;
typedef union CP_HQD_CTX_SAVE_CONTROL__VI      regCP_HQD_CTX_SAVE_CONTROL__VI;
typedef union CP_HQD_CTX_SAVE_SIZE__VI         regCP_HQD_CTX_SAVE_SIZE__VI;
typedef union CP_HQD_EOP_BASE_ADDR__VI         regCP_HQD_EOP_BASE_ADDR__VI;
typedef union CP_HQD_EOP_BASE_ADDR_HI__VI      regCP_HQD_EOP_BASE_ADDR_HI__VI;
typedef union CP_HQD_EOP_CONTROL__VI           regCP_HQD_EOP_CONTROL__VI;
typedef union CP_HQD_EOP_DONES__VI             regCP_HQD_EOP_DONES__VI;
typedef union CP_HQD_EOP_EVENTS__VI            regCP_HQD_EOP_EVENTS__VI;
typedef union CP_HQD_EOP_RPTR__VI              regCP_HQD_EOP_RPTR__VI;
typedef union CP_HQD_EOP_WPTR__VI              regCP_HQD_EOP_WPTR__VI;
typedef union CP_HQD_EOP_WPTR_MEM__VI          regCP_HQD_EOP_WPTR_MEM__VI;
typedef union CP_HQD_ERROR__VI                 regCP_HQD_ERROR__VI;
typedef union CP_HQD_GDS_RESOURCE_STATE__VI    regCP_HQD_GDS_RESOURCE_STATE__VI;
typedef union CP_HQD_HQ_CONTROL0__VI           regCP_HQD_HQ_CONTROL0__VI;
typedef union CP_HQD_HQ_CONTROL1__VI           regCP_HQD_HQ_CONTROL1__VI;
typedef union CP_HQD_HQ_STATUS0__VI            regCP_HQD_HQ_STATUS0__VI;
typedef union CP_HQD_HQ_STATUS1__VI            regCP_HQD_HQ_STATUS1__VI;
typedef union CP_HQD_OFFLOAD__VI               regCP_HQD_OFFLOAD__VI;
typedef union CP_HQD_WG_STATE_OFFSET__VI       regCP_HQD_WG_STATE_OFFSET__VI;
typedef union CP_INDEX_BASE_ADDR__VI           regCP_INDEX_BASE_ADDR__VI;
typedef union CP_INDEX_BASE_ADDR_HI__VI        regCP_INDEX_BASE_ADDR_HI__VI;
typedef union CP_INDEX_TYPE__VI                regCP_INDEX_TYPE__VI;
typedef union CP_MEC1_F32_INT_DIS__VI          regCP_MEC1_F32_INT_DIS__VI;
typedef union CP_MEC2_F32_INT_DIS__VI          regCP_MEC2_F32_INT_DIS__VI;
typedef union CP_MEC_DOORBELL_RANGE_LOWER__VI  regCP_MEC_DOORBELL_RANGE_LOWER__VI;
typedef union CP_MEC_DOORBELL_RANGE_UPPER__VI  regCP_MEC_DOORBELL_RANGE_UPPER__VI;
typedef union CP_PFP_COMPLETION_STATUS__VI     regCP_PFP_COMPLETION_STATUS__VI;
typedef union CP_PFP_METADATA_BASE_ADDR__VI    regCP_PFP_METADATA_BASE_ADDR__VI;
typedef union CP_PFP_METADATA_BASE_ADDR_HI__VI regCP_PFP_METADATA_BASE_ADDR_HI__VI;
typedef union CP_PIPE_STATS_CONTROL__VI        regCP_PIPE_STATS_CONTROL__VI;
typedef union CP_PQ_STATUS__VI                 regCP_PQ_STATUS__VI;
typedef union CP_PRED_NOT_VISIBLE__VI          regCP_PRED_NOT_VISIBLE__VI;
typedef union CP_RB_DOORBELL_CONTROL__VI       regCP_RB_DOORBELL_CONTROL__VI;
typedef union CP_RB_DOORBELL_RANGE_LOWER__VI   regCP_RB_DOORBELL_RANGE_LOWER__VI;
typedef union CP_RB_DOORBELL_RANGE_UPPER__VI   regCP_RB_DOORBELL_RANGE_UPPER__VI;
typedef union CP_SAMPLE_STATUS__VI             regCP_SAMPLE_STATUS__VI;
typedef union CP_STREAM_OUT_CONTROL__VI        regCP_STREAM_OUT_CONTROL__VI;
typedef union CP_VIRT_STATUS__VI               regCP_VIRT_STATUS__VI;
typedef union CP_VMID_STATUS__VI               regCP_VMID_STATUS__VI;
typedef union CRTC_3D_STRUCTURE_CONTROL__VI    regCRTC_3D_STRUCTURE_CONTROL__VI;
typedef union CRTC_AVSYNC_COUNTER__VI          regCRTC_AVSYNC_COUNTER__VI;
typedef union CRTC_BLACK_COLOR_EXT__VI         regCRTC_BLACK_COLOR_EXT__VI;
typedef union CRTC_BLANK_DATA_COLOR_EXT__VI    regCRTC_BLANK_DATA_COLOR_EXT__VI;
typedef union CRTC_CRC0_DATA_B__VI             regCRTC_CRC0_DATA_B__VI;
typedef union CRTC_CRC0_DATA_RG__VI            regCRTC_CRC0_DATA_RG__VI;
typedef union CRTC_CRC0_WINDOWA_X_CONTROL__VI  regCRTC_CRC0_WINDOWA_X_CONTROL__VI;
typedef union CRTC_CRC0_WINDOWA_Y_CONTROL__VI  regCRTC_CRC0_WINDOWA_Y_CONTROL__VI;
typedef union CRTC_CRC0_WINDOWB_X_CONTROL__VI  regCRTC_CRC0_WINDOWB_X_CONTROL__VI;
typedef union CRTC_CRC0_WINDOWB_Y_CONTROL__VI  regCRTC_CRC0_WINDOWB_Y_CONTROL__VI;
typedef union CRTC_CRC1_DATA_B__VI             regCRTC_CRC1_DATA_B__VI;
typedef union CRTC_CRC1_DATA_RG__VI            regCRTC_CRC1_DATA_RG__VI;
typedef union CRTC_CRC1_WINDOWA_X_CONTROL__VI  regCRTC_CRC1_WINDOWA_X_CONTROL__VI;
typedef union CRTC_CRC1_WINDOWA_Y_CONTROL__VI  regCRTC_CRC1_WINDOWA_Y_CONTROL__VI;
typedef union CRTC_CRC1_WINDOWB_X_CONTROL__VI  regCRTC_CRC1_WINDOWB_X_CONTROL__VI;
typedef union CRTC_CRC1_WINDOWB_Y_CONTROL__VI  regCRTC_CRC1_WINDOWB_Y_CONTROL__VI;
typedef union CRTC_CRC_CNTL__VI                regCRTC_CRC_CNTL__VI;
typedef union CRTC_DCFE_CLOCK_CONTROL__VI      regCRTC_DCFE_CLOCK_CONTROL__VI;
typedef union CRTC_EXT_TIMING_SYNC_CONTROL__VI regCRTC_EXT_TIMING_SYNC_CONTROL__VI;
typedef union CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI regCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__VI;
typedef union CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI regCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__VI;
typedef union CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI regCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__VI;
typedef union CRTC_EXT_TIMING_SYNC_WINDOW_END__VI regCRTC_EXT_TIMING_SYNC_WINDOW_END__VI;
typedef union CRTC_EXT_TIMING_SYNC_WINDOW_START__VI regCRTC_EXT_TIMING_SYNC_WINDOW_START__VI;
typedef union CRTC_FIELD_INDICATION_CONTROL__VI regCRTC_FIELD_INDICATION_CONTROL__VI;
typedef union CRTC_GSL_CONTROL__VI             regCRTC_GSL_CONTROL__VI;
typedef union CRTC_GSL_VSYNC_GAP__VI           regCRTC_GSL_VSYNC_GAP__VI;
typedef union CRTC_GSL_WINDOW__VI              regCRTC_GSL_WINDOW__VI;
typedef union CRTC_H_BLANK_EARLY_NUM__VI       regCRTC_H_BLANK_EARLY_NUM__VI;
typedef union CRTC_OVERSCAN_COLOR_EXT__VI      regCRTC_OVERSCAN_COLOR_EXT__VI;
typedef union CRTC_PIXEL_DATA_READBACK0__VI    regCRTC_PIXEL_DATA_READBACK0__VI;
typedef union CRTC_PIXEL_DATA_READBACK1__VI    regCRTC_PIXEL_DATA_READBACK1__VI;
typedef union CRTC_STATIC_SCREEN_CONTROL__VI   regCRTC_STATIC_SCREEN_CONTROL__VI;
typedef union CRTC_VERTICAL_INTERRUPT0_CONTROL__VI regCRTC_VERTICAL_INTERRUPT0_CONTROL__VI;
typedef union CRTC_VERTICAL_INTERRUPT0_POSITION__VI regCRTC_VERTICAL_INTERRUPT0_POSITION__VI;
typedef union CRTC_VERTICAL_INTERRUPT1_CONTROL__VI regCRTC_VERTICAL_INTERRUPT1_CONTROL__VI;
typedef union CRTC_VERTICAL_INTERRUPT1_POSITION__VI regCRTC_VERTICAL_INTERRUPT1_POSITION__VI;
typedef union CRTC_VERTICAL_INTERRUPT2_CONTROL__VI regCRTC_VERTICAL_INTERRUPT2_CONTROL__VI;
typedef union CRTC_VERTICAL_INTERRUPT2_POSITION__VI regCRTC_VERTICAL_INTERRUPT2_POSITION__VI;
typedef union CUR2_COLOR1__VI                  regCUR2_COLOR1__VI;
typedef union CUR2_COLOR2__VI                  regCUR2_COLOR2__VI;
typedef union CUR2_CONTROL__VI                 regCUR2_CONTROL__VI;
typedef union CUR2_HOT_SPOT__VI                regCUR2_HOT_SPOT__VI;
typedef union CUR2_POSITION__VI                regCUR2_POSITION__VI;
typedef union CUR2_SIZE__VI                    regCUR2_SIZE__VI;
typedef union CUR2_STEREO_CONTROL__VI          regCUR2_STEREO_CONTROL__VI;
typedef union CUR2_SURFACE_ADDRESS__VI         regCUR2_SURFACE_ADDRESS__VI;
typedef union CUR2_SURFACE_ADDRESS_HIGH__VI    regCUR2_SURFACE_ADDRESS_HIGH__VI;
typedef union CUR2_UPDATE__VI                  regCUR2_UPDATE__VI;
typedef union CUR_REQUEST_FILTER_CNTL__VI      regCUR_REQUEST_FILTER_CNTL__VI;
typedef union CUR_STEREO_CONTROL__VI           regCUR_STEREO_CONTROL__VI;
typedef union DAC_CLK_ENABLE__VI               regDAC_CLK_ENABLE__VI;
typedef union DAC_FIFO_STATUS__VI              regDAC_FIFO_STATUS__VI;
typedef union DAC_MACRO_CNTL_RESERVED0__VI     regDAC_MACRO_CNTL_RESERVED0__VI;
typedef union DAC_MACRO_CNTL_RESERVED1__VI     regDAC_MACRO_CNTL_RESERVED1__VI;
typedef union DAC_MACRO_CNTL_RESERVED2__VI     regDAC_MACRO_CNTL_RESERVED2__VI;
typedef union DAC_MACRO_CNTL_RESERVED3__VI     regDAC_MACRO_CNTL_RESERVED3__VI;
typedef union DAC_TEST_DEBUG_DATA__VI          regDAC_TEST_DEBUG_DATA__VI;
typedef union DAC_TEST_DEBUG_INDEX__VI         regDAC_TEST_DEBUG_INDEX__VI;
typedef union DBG_OUT_CNTL__VI                 regDBG_OUT_CNTL__VI;
typedef union DBG_SMB_BYPASS_SRBM_ACCESS__VI   regDBG_SMB_BYPASS_SRBM_ACCESS__VI;
typedef union DCCG_AUDIO_DTO1_MODULE__VI       regDCCG_AUDIO_DTO1_MODULE__VI;
typedef union DCCG_AUDIO_DTO1_PHASE__VI        regDCCG_AUDIO_DTO1_PHASE__VI;
typedef union DCCG_AUDIO_DTO_SOURCE__VI        regDCCG_AUDIO_DTO_SOURCE__VI;
typedef union DCCG_CAC_STATUS__VI              regDCCG_CAC_STATUS__VI;
typedef union DCCG_CBUS_WRCMD_DELAY__VI        regDCCG_CBUS_WRCMD_DELAY__VI;
typedef union DCCG_DISP_CNTL_REG__VI           regDCCG_DISP_CNTL_REG__VI;
typedef union DCCG_DS_CNTL__VI                 regDCCG_DS_CNTL__VI;
typedef union DCCG_DS_DEBUG_CNTL__VI           regDCCG_DS_DEBUG_CNTL__VI;
typedef union DCCG_DS_DTO_INCR__VI             regDCCG_DS_DTO_INCR__VI;
typedef union DCCG_DS_DTO_MODULO__VI           regDCCG_DS_DTO_MODULO__VI;
typedef union DCCG_DS_HW_CAL_INTERVAL__VI      regDCCG_DS_HW_CAL_INTERVAL__VI;
typedef union DCCG_GTC_CNTL__VI                regDCCG_GTC_CNTL__VI;
typedef union DCCG_GTC_CURRENT__VI             regDCCG_GTC_CURRENT__VI;
typedef union DCCG_GTC_DTO_INCR__VI            regDCCG_GTC_DTO_INCR__VI;
typedef union DCCG_GTC_DTO_MODULO__VI          regDCCG_GTC_DTO_MODULO__VI;
typedef union DCCG_PERFMON_CNTL__VI            regDCCG_PERFMON_CNTL__VI;
typedef union DCCG_PERFMON_CNTL2__VI           regDCCG_PERFMON_CNTL2__VI;
typedef union DCCG_SOFT_RESET__VI              regDCCG_SOFT_RESET__VI;
typedef union DCDEBUG_BUS_CLK5_SEL__VI         regDCDEBUG_BUS_CLK5_SEL__VI;
typedef union DCDEBUG_OUT_DATA__VI             regDCDEBUG_OUT_DATA__VI;
typedef union DCE_VCE_CONTROL__VI              regDCE_VCE_CONTROL__VI;
typedef union DCFEV0_CRTC_PIXEL_RATE_CNTL__VI  regDCFEV0_CRTC_PIXEL_RATE_CNTL__VI;
typedef union DCFEV0_PG_CONFIG__VI             regDCFEV0_PG_CONFIG__VI;
typedef union DCFEV0_PG_ENABLE__VI             regDCFEV0_PG_ENABLE__VI;
typedef union DCFEV0_PG_STATUS__VI             regDCFEV0_PG_STATUS__VI;
typedef union DCFEV_CLOCK_CONTROL__VI          regDCFEV_CLOCK_CONTROL__VI;
typedef union DCFEV_DBG_CONFIG__VI             regDCFEV_DBG_CONFIG__VI;
typedef union DCFEV_DMIFV_CLOCK_CONTROL__VI    regDCFEV_DMIFV_CLOCK_CONTROL__VI;
typedef union DCFEV_DMIFV_MEM_PWR_CTRL__VI     regDCFEV_DMIFV_MEM_PWR_CTRL__VI;
typedef union DCFEV_DMIFV_MEM_PWR_STATUS__VI   regDCFEV_DMIFV_MEM_PWR_STATUS__VI;
typedef union DCFEV_SOFT_RESET__VI             regDCFEV_SOFT_RESET__VI;
typedef union DCFE_CLOCK_CONTROL__VI           regDCFE_CLOCK_CONTROL__VI;
typedef union DCFE_DBG_CONFIG__VI              regDCFE_DBG_CONFIG__VI;
typedef union DCFE_DBG_SEL__VI                 regDCFE_DBG_SEL__VI;
typedef union DCFE_MEM_PWR_CTRL__VI            regDCFE_MEM_PWR_CTRL__VI;
typedef union DCFE_MEM_PWR_CTRL2__VI           regDCFE_MEM_PWR_CTRL2__VI;
typedef union DCFE_MEM_PWR_STATUS__VI          regDCFE_MEM_PWR_STATUS__VI;
typedef union DCFE_SOFT_RESET__VI              regDCFE_SOFT_RESET__VI;
typedef union DCIO_CLOCK_CNTL__VI              regDCIO_CLOCK_CNTL__VI;
typedef union DCIO_DEBUG10__VI                 regDCIO_DEBUG10__VI;
typedef union DCIO_DEBUG11__VI                 regDCIO_DEBUG11__VI;
typedef union DCIO_DEBUG12__VI                 regDCIO_DEBUG12__VI;
typedef union DCIO_DEBUG13__VI                 regDCIO_DEBUG13__VI;
typedef union DCIO_DEBUG14__VI                 regDCIO_DEBUG14__VI;
typedef union DCIO_DEBUG15__VI                 regDCIO_DEBUG15__VI;
typedef union DCIO_DEBUG16__VI                 regDCIO_DEBUG16__VI;
typedef union DCIO_DEBUG8__VI                  regDCIO_DEBUG8__VI;
typedef union DCIO_DEBUG9__VI                  regDCIO_DEBUG9__VI;
typedef union DCIO_DEBUGA__VI                  regDCIO_DEBUGA__VI;
typedef union DCIO_DEBUGB__VI                  regDCIO_DEBUGB__VI;
typedef union DCIO_DEBUGC__VI                  regDCIO_DEBUGC__VI;
typedef union DCIO_DEBUGD__VI                  regDCIO_DEBUGD__VI;
typedef union DCIO_DEBUGE__VI                  regDCIO_DEBUGE__VI;
typedef union DCIO_DEBUGF__VI                  regDCIO_DEBUGF__VI;
typedef union DCIO_DEBUG_CONFIG__VI            regDCIO_DEBUG_CONFIG__VI;
typedef union DCIO_DEBUG_ID__VI                regDCIO_DEBUG_ID__VI;
typedef union DCIO_DPHY_SEL__VI                regDCIO_DPHY_SEL__VI;
typedef union DCIO_GSL0_CNTL__VI               regDCIO_GSL0_CNTL__VI;
typedef union DCIO_GSL1_CNTL__VI               regDCIO_GSL1_CNTL__VI;
typedef union DCIO_GSL2_CNTL__VI               regDCIO_GSL2_CNTL__VI;
typedef union DCIO_GSL_GENLK_PAD_CNTL__VI      regDCIO_GSL_GENLK_PAD_CNTL__VI;
typedef union DCIO_GSL_SWAPLOCK_PAD_CNTL__VI   regDCIO_GSL_SWAPLOCK_PAD_CNTL__VI;
typedef union DCIO_IMPCAL_CNTL__VI             regDCIO_IMPCAL_CNTL__VI;
typedef union DCIO_SOFT_RESET__VI              regDCIO_SOFT_RESET__VI;
typedef union DCIO_TEST_DEBUG_DATA__VI         regDCIO_TEST_DEBUG_DATA__VI;
typedef union DCIO_TEST_DEBUG_INDEX__VI        regDCIO_TEST_DEBUG_INDEX__VI;
typedef union DCIO_WRCMD_DELAY__VI             regDCIO_WRCMD_DELAY__VI;
typedef union DCI_CLK_CNTL__VI                 regDCI_CLK_CNTL__VI;
typedef union DCI_CLK_RAMP_CNTL__VI            regDCI_CLK_RAMP_CNTL__VI;
typedef union DCI_DEBUG_CONFIG__VI             regDCI_DEBUG_CONFIG__VI;
typedef union DCI_MEM_PWR_CNTL__VI             regDCI_MEM_PWR_CNTL__VI;
typedef union DCI_MEM_PWR_CNTL2__VI            regDCI_MEM_PWR_CNTL2__VI;
typedef union DCI_MEM_PWR_CNTL3__VI            regDCI_MEM_PWR_CNTL3__VI;
typedef union DCI_MEM_PWR_STATUS__VI           regDCI_MEM_PWR_STATUS__VI;
typedef union DCI_MEM_PWR_STATUS2__VI          regDCI_MEM_PWR_STATUS2__VI;
typedef union DCI_PG_DEBUG_CONFIG__VI          regDCI_PG_DEBUG_CONFIG__VI;
typedef union DCI_SOFT_RESET__VI               regDCI_SOFT_RESET__VI;
typedef union DCO_CLK_CNTL__VI                 regDCO_CLK_CNTL__VI;
typedef union DCO_CLK_RAMP_CNTL__VI            regDCO_CLK_RAMP_CNTL__VI;
typedef union DCO_DCFE_EXT_VSYNC_CNTL__VI      regDCO_DCFE_EXT_VSYNC_CNTL__VI;
typedef union DCO_MEM_PWR_CTRL__VI             regDCO_MEM_PWR_CTRL__VI;
typedef union DCO_MEM_PWR_CTRL2__VI            regDCO_MEM_PWR_CTRL2__VI;
typedef union DCO_MEM_PWR_STATUS__VI           regDCO_MEM_PWR_STATUS__VI;
typedef union DCO_POWER_MANAGEMENT_CNTL__VI    regDCO_POWER_MANAGEMENT_CNTL__VI;
typedef union DCO_SCRATCH0__VI                 regDCO_SCRATCH0__VI;
typedef union DCO_SCRATCH1__VI                 regDCO_SCRATCH1__VI;
typedef union DCO_SCRATCH2__VI                 regDCO_SCRATCH2__VI;
typedef union DCO_SCRATCH3__VI                 regDCO_SCRATCH3__VI;
typedef union DCO_SCRATCH4__VI                 regDCO_SCRATCH4__VI;
typedef union DCO_SCRATCH5__VI                 regDCO_SCRATCH5__VI;
typedef union DCO_SCRATCH6__VI                 regDCO_SCRATCH6__VI;
typedef union DCO_SCRATCH7__VI                 regDCO_SCRATCH7__VI;
typedef union DCO_SOFT_RESET__VI               regDCO_SOFT_RESET__VI;
typedef union DCO_STEREOSYNC_SEL__VI           regDCO_STEREOSYNC_SEL__VI;
typedef union DCO_TEST_DEBUG_DATA__VI          regDCO_TEST_DEBUG_DATA__VI;
typedef union DCO_TEST_DEBUG_INDEX__VI         regDCO_TEST_DEBUG_INDEX__VI;
typedef union DCPG_TEST_DEBUG_DATA__VI         regDCPG_TEST_DEBUG_DATA__VI;
typedef union DCPG_TEST_DEBUG_INDEX__VI        regDCPG_TEST_DEBUG_INDEX__VI;
typedef union DCP_DEBUG2__VI                   regDCP_DEBUG2__VI;
typedef union DCP_FP_CONVERTED_FIELD__VI       regDCP_FP_CONVERTED_FIELD__VI;
typedef union DCP_GSL_CONTROL__VI              regDCP_GSL_CONTROL__VI;
typedef union DCP_RANDOM_SEEDS__VI             regDCP_RANDOM_SEEDS__VI;
typedef union DCP_SPATIAL_DITHER_CNTL__VI      regDCP_SPATIAL_DITHER_CNTL__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED0__VI regDCRX_PHY_MACRO_CNTL_RESERVED0__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED1__VI regDCRX_PHY_MACRO_CNTL_RESERVED1__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED10__VI regDCRX_PHY_MACRO_CNTL_RESERVED10__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED100__VI regDCRX_PHY_MACRO_CNTL_RESERVED100__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED101__VI regDCRX_PHY_MACRO_CNTL_RESERVED101__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED102__VI regDCRX_PHY_MACRO_CNTL_RESERVED102__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED103__VI regDCRX_PHY_MACRO_CNTL_RESERVED103__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED104__VI regDCRX_PHY_MACRO_CNTL_RESERVED104__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED105__VI regDCRX_PHY_MACRO_CNTL_RESERVED105__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED106__VI regDCRX_PHY_MACRO_CNTL_RESERVED106__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED107__VI regDCRX_PHY_MACRO_CNTL_RESERVED107__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED108__VI regDCRX_PHY_MACRO_CNTL_RESERVED108__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED109__VI regDCRX_PHY_MACRO_CNTL_RESERVED109__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED11__VI regDCRX_PHY_MACRO_CNTL_RESERVED11__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED110__VI regDCRX_PHY_MACRO_CNTL_RESERVED110__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED111__VI regDCRX_PHY_MACRO_CNTL_RESERVED111__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED112__VI regDCRX_PHY_MACRO_CNTL_RESERVED112__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED113__VI regDCRX_PHY_MACRO_CNTL_RESERVED113__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED114__VI regDCRX_PHY_MACRO_CNTL_RESERVED114__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED115__VI regDCRX_PHY_MACRO_CNTL_RESERVED115__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED116__VI regDCRX_PHY_MACRO_CNTL_RESERVED116__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED117__VI regDCRX_PHY_MACRO_CNTL_RESERVED117__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED118__VI regDCRX_PHY_MACRO_CNTL_RESERVED118__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED119__VI regDCRX_PHY_MACRO_CNTL_RESERVED119__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED12__VI regDCRX_PHY_MACRO_CNTL_RESERVED12__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED120__VI regDCRX_PHY_MACRO_CNTL_RESERVED120__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED121__VI regDCRX_PHY_MACRO_CNTL_RESERVED121__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED122__VI regDCRX_PHY_MACRO_CNTL_RESERVED122__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED123__VI regDCRX_PHY_MACRO_CNTL_RESERVED123__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED124__VI regDCRX_PHY_MACRO_CNTL_RESERVED124__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED125__VI regDCRX_PHY_MACRO_CNTL_RESERVED125__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED126__VI regDCRX_PHY_MACRO_CNTL_RESERVED126__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED127__VI regDCRX_PHY_MACRO_CNTL_RESERVED127__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED128__VI regDCRX_PHY_MACRO_CNTL_RESERVED128__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED129__VI regDCRX_PHY_MACRO_CNTL_RESERVED129__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED13__VI regDCRX_PHY_MACRO_CNTL_RESERVED13__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED130__VI regDCRX_PHY_MACRO_CNTL_RESERVED130__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED131__VI regDCRX_PHY_MACRO_CNTL_RESERVED131__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED132__VI regDCRX_PHY_MACRO_CNTL_RESERVED132__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED133__VI regDCRX_PHY_MACRO_CNTL_RESERVED133__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED134__VI regDCRX_PHY_MACRO_CNTL_RESERVED134__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED135__VI regDCRX_PHY_MACRO_CNTL_RESERVED135__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED136__VI regDCRX_PHY_MACRO_CNTL_RESERVED136__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED137__VI regDCRX_PHY_MACRO_CNTL_RESERVED137__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED138__VI regDCRX_PHY_MACRO_CNTL_RESERVED138__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED139__VI regDCRX_PHY_MACRO_CNTL_RESERVED139__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED14__VI regDCRX_PHY_MACRO_CNTL_RESERVED14__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED140__VI regDCRX_PHY_MACRO_CNTL_RESERVED140__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED141__VI regDCRX_PHY_MACRO_CNTL_RESERVED141__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED142__VI regDCRX_PHY_MACRO_CNTL_RESERVED142__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED143__VI regDCRX_PHY_MACRO_CNTL_RESERVED143__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED144__VI regDCRX_PHY_MACRO_CNTL_RESERVED144__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED145__VI regDCRX_PHY_MACRO_CNTL_RESERVED145__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED146__VI regDCRX_PHY_MACRO_CNTL_RESERVED146__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED147__VI regDCRX_PHY_MACRO_CNTL_RESERVED147__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED148__VI regDCRX_PHY_MACRO_CNTL_RESERVED148__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED149__VI regDCRX_PHY_MACRO_CNTL_RESERVED149__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED15__VI regDCRX_PHY_MACRO_CNTL_RESERVED15__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED150__VI regDCRX_PHY_MACRO_CNTL_RESERVED150__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED151__VI regDCRX_PHY_MACRO_CNTL_RESERVED151__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED152__VI regDCRX_PHY_MACRO_CNTL_RESERVED152__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED153__VI regDCRX_PHY_MACRO_CNTL_RESERVED153__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED154__VI regDCRX_PHY_MACRO_CNTL_RESERVED154__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED155__VI regDCRX_PHY_MACRO_CNTL_RESERVED155__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED156__VI regDCRX_PHY_MACRO_CNTL_RESERVED156__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED157__VI regDCRX_PHY_MACRO_CNTL_RESERVED157__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED158__VI regDCRX_PHY_MACRO_CNTL_RESERVED158__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED159__VI regDCRX_PHY_MACRO_CNTL_RESERVED159__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED16__VI regDCRX_PHY_MACRO_CNTL_RESERVED16__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED160__VI regDCRX_PHY_MACRO_CNTL_RESERVED160__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED161__VI regDCRX_PHY_MACRO_CNTL_RESERVED161__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED162__VI regDCRX_PHY_MACRO_CNTL_RESERVED162__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED163__VI regDCRX_PHY_MACRO_CNTL_RESERVED163__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED164__VI regDCRX_PHY_MACRO_CNTL_RESERVED164__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED165__VI regDCRX_PHY_MACRO_CNTL_RESERVED165__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED166__VI regDCRX_PHY_MACRO_CNTL_RESERVED166__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED167__VI regDCRX_PHY_MACRO_CNTL_RESERVED167__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED168__VI regDCRX_PHY_MACRO_CNTL_RESERVED168__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED169__VI regDCRX_PHY_MACRO_CNTL_RESERVED169__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED17__VI regDCRX_PHY_MACRO_CNTL_RESERVED17__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED170__VI regDCRX_PHY_MACRO_CNTL_RESERVED170__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED171__VI regDCRX_PHY_MACRO_CNTL_RESERVED171__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED172__VI regDCRX_PHY_MACRO_CNTL_RESERVED172__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED173__VI regDCRX_PHY_MACRO_CNTL_RESERVED173__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED174__VI regDCRX_PHY_MACRO_CNTL_RESERVED174__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED175__VI regDCRX_PHY_MACRO_CNTL_RESERVED175__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED176__VI regDCRX_PHY_MACRO_CNTL_RESERVED176__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED177__VI regDCRX_PHY_MACRO_CNTL_RESERVED177__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED178__VI regDCRX_PHY_MACRO_CNTL_RESERVED178__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED179__VI regDCRX_PHY_MACRO_CNTL_RESERVED179__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED18__VI regDCRX_PHY_MACRO_CNTL_RESERVED18__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED180__VI regDCRX_PHY_MACRO_CNTL_RESERVED180__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED181__VI regDCRX_PHY_MACRO_CNTL_RESERVED181__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED182__VI regDCRX_PHY_MACRO_CNTL_RESERVED182__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED183__VI regDCRX_PHY_MACRO_CNTL_RESERVED183__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED184__VI regDCRX_PHY_MACRO_CNTL_RESERVED184__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED185__VI regDCRX_PHY_MACRO_CNTL_RESERVED185__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED186__VI regDCRX_PHY_MACRO_CNTL_RESERVED186__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED187__VI regDCRX_PHY_MACRO_CNTL_RESERVED187__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED188__VI regDCRX_PHY_MACRO_CNTL_RESERVED188__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED189__VI regDCRX_PHY_MACRO_CNTL_RESERVED189__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED19__VI regDCRX_PHY_MACRO_CNTL_RESERVED19__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED190__VI regDCRX_PHY_MACRO_CNTL_RESERVED190__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED191__VI regDCRX_PHY_MACRO_CNTL_RESERVED191__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED192__VI regDCRX_PHY_MACRO_CNTL_RESERVED192__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED193__VI regDCRX_PHY_MACRO_CNTL_RESERVED193__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED194__VI regDCRX_PHY_MACRO_CNTL_RESERVED194__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED195__VI regDCRX_PHY_MACRO_CNTL_RESERVED195__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED196__VI regDCRX_PHY_MACRO_CNTL_RESERVED196__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED197__VI regDCRX_PHY_MACRO_CNTL_RESERVED197__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED198__VI regDCRX_PHY_MACRO_CNTL_RESERVED198__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED199__VI regDCRX_PHY_MACRO_CNTL_RESERVED199__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED2__VI regDCRX_PHY_MACRO_CNTL_RESERVED2__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED20__VI regDCRX_PHY_MACRO_CNTL_RESERVED20__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED200__VI regDCRX_PHY_MACRO_CNTL_RESERVED200__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED201__VI regDCRX_PHY_MACRO_CNTL_RESERVED201__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED202__VI regDCRX_PHY_MACRO_CNTL_RESERVED202__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED203__VI regDCRX_PHY_MACRO_CNTL_RESERVED203__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED204__VI regDCRX_PHY_MACRO_CNTL_RESERVED204__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED205__VI regDCRX_PHY_MACRO_CNTL_RESERVED205__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED206__VI regDCRX_PHY_MACRO_CNTL_RESERVED206__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED207__VI regDCRX_PHY_MACRO_CNTL_RESERVED207__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED208__VI regDCRX_PHY_MACRO_CNTL_RESERVED208__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED209__VI regDCRX_PHY_MACRO_CNTL_RESERVED209__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED21__VI regDCRX_PHY_MACRO_CNTL_RESERVED21__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED210__VI regDCRX_PHY_MACRO_CNTL_RESERVED210__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED211__VI regDCRX_PHY_MACRO_CNTL_RESERVED211__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED212__VI regDCRX_PHY_MACRO_CNTL_RESERVED212__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED213__VI regDCRX_PHY_MACRO_CNTL_RESERVED213__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED214__VI regDCRX_PHY_MACRO_CNTL_RESERVED214__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED215__VI regDCRX_PHY_MACRO_CNTL_RESERVED215__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED216__VI regDCRX_PHY_MACRO_CNTL_RESERVED216__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED217__VI regDCRX_PHY_MACRO_CNTL_RESERVED217__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED218__VI regDCRX_PHY_MACRO_CNTL_RESERVED218__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED219__VI regDCRX_PHY_MACRO_CNTL_RESERVED219__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED22__VI regDCRX_PHY_MACRO_CNTL_RESERVED22__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED220__VI regDCRX_PHY_MACRO_CNTL_RESERVED220__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED221__VI regDCRX_PHY_MACRO_CNTL_RESERVED221__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED222__VI regDCRX_PHY_MACRO_CNTL_RESERVED222__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED223__VI regDCRX_PHY_MACRO_CNTL_RESERVED223__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED224__VI regDCRX_PHY_MACRO_CNTL_RESERVED224__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED225__VI regDCRX_PHY_MACRO_CNTL_RESERVED225__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED226__VI regDCRX_PHY_MACRO_CNTL_RESERVED226__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED227__VI regDCRX_PHY_MACRO_CNTL_RESERVED227__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED228__VI regDCRX_PHY_MACRO_CNTL_RESERVED228__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED229__VI regDCRX_PHY_MACRO_CNTL_RESERVED229__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED23__VI regDCRX_PHY_MACRO_CNTL_RESERVED23__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED230__VI regDCRX_PHY_MACRO_CNTL_RESERVED230__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED231__VI regDCRX_PHY_MACRO_CNTL_RESERVED231__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED232__VI regDCRX_PHY_MACRO_CNTL_RESERVED232__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED233__VI regDCRX_PHY_MACRO_CNTL_RESERVED233__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED234__VI regDCRX_PHY_MACRO_CNTL_RESERVED234__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED235__VI regDCRX_PHY_MACRO_CNTL_RESERVED235__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED236__VI regDCRX_PHY_MACRO_CNTL_RESERVED236__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED237__VI regDCRX_PHY_MACRO_CNTL_RESERVED237__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED238__VI regDCRX_PHY_MACRO_CNTL_RESERVED238__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED239__VI regDCRX_PHY_MACRO_CNTL_RESERVED239__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED24__VI regDCRX_PHY_MACRO_CNTL_RESERVED24__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED240__VI regDCRX_PHY_MACRO_CNTL_RESERVED240__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED241__VI regDCRX_PHY_MACRO_CNTL_RESERVED241__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED242__VI regDCRX_PHY_MACRO_CNTL_RESERVED242__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED243__VI regDCRX_PHY_MACRO_CNTL_RESERVED243__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED244__VI regDCRX_PHY_MACRO_CNTL_RESERVED244__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED245__VI regDCRX_PHY_MACRO_CNTL_RESERVED245__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED246__VI regDCRX_PHY_MACRO_CNTL_RESERVED246__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED247__VI regDCRX_PHY_MACRO_CNTL_RESERVED247__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED248__VI regDCRX_PHY_MACRO_CNTL_RESERVED248__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED249__VI regDCRX_PHY_MACRO_CNTL_RESERVED249__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED25__VI regDCRX_PHY_MACRO_CNTL_RESERVED25__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED250__VI regDCRX_PHY_MACRO_CNTL_RESERVED250__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED251__VI regDCRX_PHY_MACRO_CNTL_RESERVED251__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED252__VI regDCRX_PHY_MACRO_CNTL_RESERVED252__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED253__VI regDCRX_PHY_MACRO_CNTL_RESERVED253__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED254__VI regDCRX_PHY_MACRO_CNTL_RESERVED254__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED255__VI regDCRX_PHY_MACRO_CNTL_RESERVED255__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED256__VI regDCRX_PHY_MACRO_CNTL_RESERVED256__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED257__VI regDCRX_PHY_MACRO_CNTL_RESERVED257__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED258__VI regDCRX_PHY_MACRO_CNTL_RESERVED258__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED259__VI regDCRX_PHY_MACRO_CNTL_RESERVED259__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED26__VI regDCRX_PHY_MACRO_CNTL_RESERVED26__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED260__VI regDCRX_PHY_MACRO_CNTL_RESERVED260__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED261__VI regDCRX_PHY_MACRO_CNTL_RESERVED261__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED262__VI regDCRX_PHY_MACRO_CNTL_RESERVED262__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED263__VI regDCRX_PHY_MACRO_CNTL_RESERVED263__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED264__VI regDCRX_PHY_MACRO_CNTL_RESERVED264__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED265__VI regDCRX_PHY_MACRO_CNTL_RESERVED265__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED266__VI regDCRX_PHY_MACRO_CNTL_RESERVED266__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED267__VI regDCRX_PHY_MACRO_CNTL_RESERVED267__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED268__VI regDCRX_PHY_MACRO_CNTL_RESERVED268__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED269__VI regDCRX_PHY_MACRO_CNTL_RESERVED269__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED27__VI regDCRX_PHY_MACRO_CNTL_RESERVED27__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED270__VI regDCRX_PHY_MACRO_CNTL_RESERVED270__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED271__VI regDCRX_PHY_MACRO_CNTL_RESERVED271__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED272__VI regDCRX_PHY_MACRO_CNTL_RESERVED272__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED273__VI regDCRX_PHY_MACRO_CNTL_RESERVED273__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED274__VI regDCRX_PHY_MACRO_CNTL_RESERVED274__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED275__VI regDCRX_PHY_MACRO_CNTL_RESERVED275__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED276__VI regDCRX_PHY_MACRO_CNTL_RESERVED276__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED277__VI regDCRX_PHY_MACRO_CNTL_RESERVED277__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED278__VI regDCRX_PHY_MACRO_CNTL_RESERVED278__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED279__VI regDCRX_PHY_MACRO_CNTL_RESERVED279__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED28__VI regDCRX_PHY_MACRO_CNTL_RESERVED28__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED280__VI regDCRX_PHY_MACRO_CNTL_RESERVED280__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED281__VI regDCRX_PHY_MACRO_CNTL_RESERVED281__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED282__VI regDCRX_PHY_MACRO_CNTL_RESERVED282__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED283__VI regDCRX_PHY_MACRO_CNTL_RESERVED283__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED284__VI regDCRX_PHY_MACRO_CNTL_RESERVED284__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED285__VI regDCRX_PHY_MACRO_CNTL_RESERVED285__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED286__VI regDCRX_PHY_MACRO_CNTL_RESERVED286__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED287__VI regDCRX_PHY_MACRO_CNTL_RESERVED287__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED288__VI regDCRX_PHY_MACRO_CNTL_RESERVED288__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED289__VI regDCRX_PHY_MACRO_CNTL_RESERVED289__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED29__VI regDCRX_PHY_MACRO_CNTL_RESERVED29__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED290__VI regDCRX_PHY_MACRO_CNTL_RESERVED290__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED291__VI regDCRX_PHY_MACRO_CNTL_RESERVED291__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED292__VI regDCRX_PHY_MACRO_CNTL_RESERVED292__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED293__VI regDCRX_PHY_MACRO_CNTL_RESERVED293__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED294__VI regDCRX_PHY_MACRO_CNTL_RESERVED294__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED295__VI regDCRX_PHY_MACRO_CNTL_RESERVED295__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED296__VI regDCRX_PHY_MACRO_CNTL_RESERVED296__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED297__VI regDCRX_PHY_MACRO_CNTL_RESERVED297__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED298__VI regDCRX_PHY_MACRO_CNTL_RESERVED298__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED299__VI regDCRX_PHY_MACRO_CNTL_RESERVED299__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED3__VI regDCRX_PHY_MACRO_CNTL_RESERVED3__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED30__VI regDCRX_PHY_MACRO_CNTL_RESERVED30__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED300__VI regDCRX_PHY_MACRO_CNTL_RESERVED300__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED301__VI regDCRX_PHY_MACRO_CNTL_RESERVED301__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED302__VI regDCRX_PHY_MACRO_CNTL_RESERVED302__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED303__VI regDCRX_PHY_MACRO_CNTL_RESERVED303__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED304__VI regDCRX_PHY_MACRO_CNTL_RESERVED304__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED305__VI regDCRX_PHY_MACRO_CNTL_RESERVED305__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED306__VI regDCRX_PHY_MACRO_CNTL_RESERVED306__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED307__VI regDCRX_PHY_MACRO_CNTL_RESERVED307__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED308__VI regDCRX_PHY_MACRO_CNTL_RESERVED308__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED309__VI regDCRX_PHY_MACRO_CNTL_RESERVED309__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED31__VI regDCRX_PHY_MACRO_CNTL_RESERVED31__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED310__VI regDCRX_PHY_MACRO_CNTL_RESERVED310__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED311__VI regDCRX_PHY_MACRO_CNTL_RESERVED311__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED312__VI regDCRX_PHY_MACRO_CNTL_RESERVED312__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED313__VI regDCRX_PHY_MACRO_CNTL_RESERVED313__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED314__VI regDCRX_PHY_MACRO_CNTL_RESERVED314__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED315__VI regDCRX_PHY_MACRO_CNTL_RESERVED315__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED316__VI regDCRX_PHY_MACRO_CNTL_RESERVED316__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED317__VI regDCRX_PHY_MACRO_CNTL_RESERVED317__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED318__VI regDCRX_PHY_MACRO_CNTL_RESERVED318__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED319__VI regDCRX_PHY_MACRO_CNTL_RESERVED319__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED32__VI regDCRX_PHY_MACRO_CNTL_RESERVED32__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED320__VI regDCRX_PHY_MACRO_CNTL_RESERVED320__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED321__VI regDCRX_PHY_MACRO_CNTL_RESERVED321__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED322__VI regDCRX_PHY_MACRO_CNTL_RESERVED322__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED323__VI regDCRX_PHY_MACRO_CNTL_RESERVED323__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED324__VI regDCRX_PHY_MACRO_CNTL_RESERVED324__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED325__VI regDCRX_PHY_MACRO_CNTL_RESERVED325__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED326__VI regDCRX_PHY_MACRO_CNTL_RESERVED326__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED327__VI regDCRX_PHY_MACRO_CNTL_RESERVED327__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED328__VI regDCRX_PHY_MACRO_CNTL_RESERVED328__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED329__VI regDCRX_PHY_MACRO_CNTL_RESERVED329__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED33__VI regDCRX_PHY_MACRO_CNTL_RESERVED33__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED330__VI regDCRX_PHY_MACRO_CNTL_RESERVED330__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED331__VI regDCRX_PHY_MACRO_CNTL_RESERVED331__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED332__VI regDCRX_PHY_MACRO_CNTL_RESERVED332__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED333__VI regDCRX_PHY_MACRO_CNTL_RESERVED333__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED334__VI regDCRX_PHY_MACRO_CNTL_RESERVED334__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED335__VI regDCRX_PHY_MACRO_CNTL_RESERVED335__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED336__VI regDCRX_PHY_MACRO_CNTL_RESERVED336__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED337__VI regDCRX_PHY_MACRO_CNTL_RESERVED337__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED338__VI regDCRX_PHY_MACRO_CNTL_RESERVED338__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED339__VI regDCRX_PHY_MACRO_CNTL_RESERVED339__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED34__VI regDCRX_PHY_MACRO_CNTL_RESERVED34__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED340__VI regDCRX_PHY_MACRO_CNTL_RESERVED340__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED341__VI regDCRX_PHY_MACRO_CNTL_RESERVED341__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED342__VI regDCRX_PHY_MACRO_CNTL_RESERVED342__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED343__VI regDCRX_PHY_MACRO_CNTL_RESERVED343__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED344__VI regDCRX_PHY_MACRO_CNTL_RESERVED344__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED345__VI regDCRX_PHY_MACRO_CNTL_RESERVED345__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED346__VI regDCRX_PHY_MACRO_CNTL_RESERVED346__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED347__VI regDCRX_PHY_MACRO_CNTL_RESERVED347__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED348__VI regDCRX_PHY_MACRO_CNTL_RESERVED348__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED349__VI regDCRX_PHY_MACRO_CNTL_RESERVED349__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED35__VI regDCRX_PHY_MACRO_CNTL_RESERVED35__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED350__VI regDCRX_PHY_MACRO_CNTL_RESERVED350__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED351__VI regDCRX_PHY_MACRO_CNTL_RESERVED351__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED352__VI regDCRX_PHY_MACRO_CNTL_RESERVED352__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED353__VI regDCRX_PHY_MACRO_CNTL_RESERVED353__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED354__VI regDCRX_PHY_MACRO_CNTL_RESERVED354__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED355__VI regDCRX_PHY_MACRO_CNTL_RESERVED355__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED356__VI regDCRX_PHY_MACRO_CNTL_RESERVED356__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED357__VI regDCRX_PHY_MACRO_CNTL_RESERVED357__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED358__VI regDCRX_PHY_MACRO_CNTL_RESERVED358__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED359__VI regDCRX_PHY_MACRO_CNTL_RESERVED359__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED36__VI regDCRX_PHY_MACRO_CNTL_RESERVED36__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED360__VI regDCRX_PHY_MACRO_CNTL_RESERVED360__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED361__VI regDCRX_PHY_MACRO_CNTL_RESERVED361__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED362__VI regDCRX_PHY_MACRO_CNTL_RESERVED362__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED363__VI regDCRX_PHY_MACRO_CNTL_RESERVED363__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED364__VI regDCRX_PHY_MACRO_CNTL_RESERVED364__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED365__VI regDCRX_PHY_MACRO_CNTL_RESERVED365__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED366__VI regDCRX_PHY_MACRO_CNTL_RESERVED366__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED367__VI regDCRX_PHY_MACRO_CNTL_RESERVED367__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED368__VI regDCRX_PHY_MACRO_CNTL_RESERVED368__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED369__VI regDCRX_PHY_MACRO_CNTL_RESERVED369__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED37__VI regDCRX_PHY_MACRO_CNTL_RESERVED37__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED370__VI regDCRX_PHY_MACRO_CNTL_RESERVED370__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED371__VI regDCRX_PHY_MACRO_CNTL_RESERVED371__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED372__VI regDCRX_PHY_MACRO_CNTL_RESERVED372__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED373__VI regDCRX_PHY_MACRO_CNTL_RESERVED373__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED374__VI regDCRX_PHY_MACRO_CNTL_RESERVED374__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED375__VI regDCRX_PHY_MACRO_CNTL_RESERVED375__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED376__VI regDCRX_PHY_MACRO_CNTL_RESERVED376__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED377__VI regDCRX_PHY_MACRO_CNTL_RESERVED377__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED378__VI regDCRX_PHY_MACRO_CNTL_RESERVED378__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED379__VI regDCRX_PHY_MACRO_CNTL_RESERVED379__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED38__VI regDCRX_PHY_MACRO_CNTL_RESERVED38__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED39__VI regDCRX_PHY_MACRO_CNTL_RESERVED39__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED4__VI regDCRX_PHY_MACRO_CNTL_RESERVED4__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED40__VI regDCRX_PHY_MACRO_CNTL_RESERVED40__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED41__VI regDCRX_PHY_MACRO_CNTL_RESERVED41__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED42__VI regDCRX_PHY_MACRO_CNTL_RESERVED42__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED43__VI regDCRX_PHY_MACRO_CNTL_RESERVED43__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED44__VI regDCRX_PHY_MACRO_CNTL_RESERVED44__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED45__VI regDCRX_PHY_MACRO_CNTL_RESERVED45__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED46__VI regDCRX_PHY_MACRO_CNTL_RESERVED46__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED47__VI regDCRX_PHY_MACRO_CNTL_RESERVED47__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED48__VI regDCRX_PHY_MACRO_CNTL_RESERVED48__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED49__VI regDCRX_PHY_MACRO_CNTL_RESERVED49__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED5__VI regDCRX_PHY_MACRO_CNTL_RESERVED5__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED50__VI regDCRX_PHY_MACRO_CNTL_RESERVED50__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED51__VI regDCRX_PHY_MACRO_CNTL_RESERVED51__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED52__VI regDCRX_PHY_MACRO_CNTL_RESERVED52__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED53__VI regDCRX_PHY_MACRO_CNTL_RESERVED53__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED54__VI regDCRX_PHY_MACRO_CNTL_RESERVED54__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED55__VI regDCRX_PHY_MACRO_CNTL_RESERVED55__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED56__VI regDCRX_PHY_MACRO_CNTL_RESERVED56__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED57__VI regDCRX_PHY_MACRO_CNTL_RESERVED57__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED58__VI regDCRX_PHY_MACRO_CNTL_RESERVED58__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED59__VI regDCRX_PHY_MACRO_CNTL_RESERVED59__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED6__VI regDCRX_PHY_MACRO_CNTL_RESERVED6__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED60__VI regDCRX_PHY_MACRO_CNTL_RESERVED60__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED61__VI regDCRX_PHY_MACRO_CNTL_RESERVED61__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED62__VI regDCRX_PHY_MACRO_CNTL_RESERVED62__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED63__VI regDCRX_PHY_MACRO_CNTL_RESERVED63__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED64__VI regDCRX_PHY_MACRO_CNTL_RESERVED64__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED65__VI regDCRX_PHY_MACRO_CNTL_RESERVED65__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED66__VI regDCRX_PHY_MACRO_CNTL_RESERVED66__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED67__VI regDCRX_PHY_MACRO_CNTL_RESERVED67__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED68__VI regDCRX_PHY_MACRO_CNTL_RESERVED68__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED69__VI regDCRX_PHY_MACRO_CNTL_RESERVED69__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED7__VI regDCRX_PHY_MACRO_CNTL_RESERVED7__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED70__VI regDCRX_PHY_MACRO_CNTL_RESERVED70__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED71__VI regDCRX_PHY_MACRO_CNTL_RESERVED71__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED72__VI regDCRX_PHY_MACRO_CNTL_RESERVED72__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED73__VI regDCRX_PHY_MACRO_CNTL_RESERVED73__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED74__VI regDCRX_PHY_MACRO_CNTL_RESERVED74__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED75__VI regDCRX_PHY_MACRO_CNTL_RESERVED75__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED76__VI regDCRX_PHY_MACRO_CNTL_RESERVED76__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED77__VI regDCRX_PHY_MACRO_CNTL_RESERVED77__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED78__VI regDCRX_PHY_MACRO_CNTL_RESERVED78__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED79__VI regDCRX_PHY_MACRO_CNTL_RESERVED79__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED8__VI regDCRX_PHY_MACRO_CNTL_RESERVED8__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED80__VI regDCRX_PHY_MACRO_CNTL_RESERVED80__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED81__VI regDCRX_PHY_MACRO_CNTL_RESERVED81__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED82__VI regDCRX_PHY_MACRO_CNTL_RESERVED82__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED83__VI regDCRX_PHY_MACRO_CNTL_RESERVED83__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED84__VI regDCRX_PHY_MACRO_CNTL_RESERVED84__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED85__VI regDCRX_PHY_MACRO_CNTL_RESERVED85__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED86__VI regDCRX_PHY_MACRO_CNTL_RESERVED86__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED87__VI regDCRX_PHY_MACRO_CNTL_RESERVED87__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED88__VI regDCRX_PHY_MACRO_CNTL_RESERVED88__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED89__VI regDCRX_PHY_MACRO_CNTL_RESERVED89__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED9__VI regDCRX_PHY_MACRO_CNTL_RESERVED9__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED90__VI regDCRX_PHY_MACRO_CNTL_RESERVED90__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED91__VI regDCRX_PHY_MACRO_CNTL_RESERVED91__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED92__VI regDCRX_PHY_MACRO_CNTL_RESERVED92__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED93__VI regDCRX_PHY_MACRO_CNTL_RESERVED93__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED94__VI regDCRX_PHY_MACRO_CNTL_RESERVED94__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED95__VI regDCRX_PHY_MACRO_CNTL_RESERVED95__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED96__VI regDCRX_PHY_MACRO_CNTL_RESERVED96__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED97__VI regDCRX_PHY_MACRO_CNTL_RESERVED97__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED98__VI regDCRX_PHY_MACRO_CNTL_RESERVED98__VI;
typedef union DCRX_PHY_MACRO_CNTL_RESERVED99__VI regDCRX_PHY_MACRO_CNTL_RESERVED99__VI;
typedef union DC_ABM1_OVERSCAN_PIXEL_VALUE__VI regDC_ABM1_OVERSCAN_PIXEL_VALUE__VI;
typedef union DC_DVODATA_CONFIG__VI            regDC_DVODATA_CONFIG__VI;
typedef union DC_GPIO_DDCVGA_A__VI             regDC_GPIO_DDCVGA_A__VI;
typedef union DC_GPIO_DDCVGA_EN__VI            regDC_GPIO_DDCVGA_EN__VI;
typedef union DC_GPIO_DDCVGA_MASK__VI          regDC_GPIO_DDCVGA_MASK__VI;
typedef union DC_GPIO_DDCVGA_Y__VI             regDC_GPIO_DDCVGA_Y__VI;
typedef union DC_GPIO_GENLK_A__VI              regDC_GPIO_GENLK_A__VI;
typedef union DC_GPIO_GENLK_EN__VI             regDC_GPIO_GENLK_EN__VI;
typedef union DC_GPIO_GENLK_MASK__VI           regDC_GPIO_GENLK_MASK__VI;
typedef union DC_GPIO_GENLK_Y__VI              regDC_GPIO_GENLK_Y__VI;
typedef union DC_GPIO_I2CPAD_A__VI             regDC_GPIO_I2CPAD_A__VI;
typedef union DC_GPIO_I2CPAD_EN__VI            regDC_GPIO_I2CPAD_EN__VI;
typedef union DC_GPIO_I2CPAD_MASK__VI          regDC_GPIO_I2CPAD_MASK__VI;
typedef union DC_GPIO_I2CPAD_STRENGTH__VI      regDC_GPIO_I2CPAD_STRENGTH__VI;
typedef union DC_GPIO_I2CPAD_Y__VI             regDC_GPIO_I2CPAD_Y__VI;
typedef union DC_GPU_TIMER_START_POSITION_P_FLIP__VI regDC_GPU_TIMER_START_POSITION_P_FLIP__VI;
typedef union DC_GPU_TIMER_START_POSITION_V_UPDATE__VI regDC_GPU_TIMER_START_POSITION_V_UPDATE__VI;
typedef union DC_HPD_CONTROL__VI               regDC_HPD_CONTROL__VI;
typedef union DC_HPD_FAST_TRAIN_CNTL__VI       regDC_HPD_FAST_TRAIN_CNTL__VI;
typedef union DC_HPD_INT_CONTROL__VI           regDC_HPD_INT_CONTROL__VI;
typedef union DC_HPD_INT_STATUS__VI            regDC_HPD_INT_STATUS__VI;
typedef union DC_HPD_TOGGLE_FILT_CNTL__VI      regDC_HPD_TOGGLE_FILT_CNTL__VI;
typedef union DC_I2C_DDCVGA_HW_STATUS__VI      regDC_I2C_DDCVGA_HW_STATUS__VI;
typedef union DC_I2C_DDCVGA_SETUP__VI          regDC_I2C_DDCVGA_SETUP__VI;
typedef union DC_I2C_DDCVGA_SPEED__VI          regDC_I2C_DDCVGA_SPEED__VI;
typedef union DC_I2C_EDID_DETECT_CTRL__VI      regDC_I2C_EDID_DETECT_CTRL__VI;
typedef union DC_IP_REQUEST_CNTL__VI           regDC_IP_REQUEST_CNTL__VI;
typedef union DC_LUT_VGA_ACCESS_ENABLE__VI     regDC_LUT_VGA_ACCESS_ENABLE__VI;
typedef union DC_MEM_GLOBAL_PWR_REQ_CNTL__VI   regDC_MEM_GLOBAL_PWR_REQ_CNTL__VI;
typedef union DC_PGCNTL_STATUS_REG__VI         regDC_PGCNTL_STATUS_REG__VI;
typedef union DC_PGFSM_CONFIG_REG__VI          regDC_PGFSM_CONFIG_REG__VI;
typedef union DC_PGFSM_WRITE_REG__VI           regDC_PGFSM_WRITE_REG__VI;
typedef union DEGAMMA_CONTROL__VI              regDEGAMMA_CONTROL__VI;
typedef union DENORM_CLAMP_CONTROL__VI         regDENORM_CLAMP_CONTROL__VI;
typedef union DENORM_CLAMP_RANGE_B_CB__VI      regDENORM_CLAMP_RANGE_B_CB__VI;
typedef union DENORM_CLAMP_RANGE_G_Y__VI       regDENORM_CLAMP_RANGE_G_Y__VI;
typedef union DENORM_CLAMP_RANGE_R_CR__VI      regDENORM_CLAMP_RANGE_R_CR__VI;
typedef union DENORM_CONTROL__VI               regDENORM_CONTROL__VI;
typedef union DIDT_DBR_CTRL0__VI               regDIDT_DBR_CTRL0__VI;
typedef union DIDT_DBR_CTRL1__VI               regDIDT_DBR_CTRL1__VI;
typedef union DIDT_DBR_CTRL2__VI               regDIDT_DBR_CTRL2__VI;
typedef union DIDT_DBR_CTRL_OCP__VI            regDIDT_DBR_CTRL_OCP__VI;
typedef union DIDT_DBR_WEIGHT0_3__VI           regDIDT_DBR_WEIGHT0_3__VI;
typedef union DIDT_DBR_WEIGHT4_7__VI           regDIDT_DBR_WEIGHT4_7__VI;
typedef union DIDT_DBR_WEIGHT8_11__VI          regDIDT_DBR_WEIGHT8_11__VI;
typedef union DIDT_DB_CTRL_OCP__VI             regDIDT_DB_CTRL_OCP__VI;
typedef union DIDT_SQ_CTRL_OCP__VI             regDIDT_SQ_CTRL_OCP__VI;
typedef union DIDT_TCP_CTRL_OCP__VI            regDIDT_TCP_CTRL_OCP__VI;
typedef union DIDT_TD_CTRL_OCP__VI             regDIDT_TD_CTRL_OCP__VI;
typedef union DIG_BE_CNTL__VI                  regDIG_BE_CNTL__VI;
typedef union DIG_BE_EN_CNTL__VI               regDIG_BE_EN_CNTL__VI;
typedef union DIG_DISPCLK_SWITCH_CNTL__VI      regDIG_DISPCLK_SWITCH_CNTL__VI;
typedef union DIG_DISPCLK_SWITCH_STATUS__VI    regDIG_DISPCLK_SWITCH_STATUS__VI;
typedef union DIG_FE_CNTL__VI                  regDIG_FE_CNTL__VI;
typedef union DIG_FE_TEST_DEBUG_DATA__VI       regDIG_FE_TEST_DEBUG_DATA__VI;
typedef union DIG_FE_TEST_DEBUG_INDEX__VI      regDIG_FE_TEST_DEBUG_INDEX__VI;
typedef union DIG_FIFO_STATUS__VI              regDIG_FIFO_STATUS__VI;
typedef union DIG_LANE_ENABLE__VI              regDIG_LANE_ENABLE__VI;
typedef union DIG_SOFT_RESET__VI               regDIG_SOFT_RESET__VI;
typedef union DIG_TEST_DEBUG_DATA__VI          regDIG_TEST_DEBUG_DATA__VI;
typedef union DIG_TEST_DEBUG_INDEX__VI         regDIG_TEST_DEBUG_INDEX__VI;
typedef union DISPCLK_FREQ_CHANGE_CNTL__VI     regDISPCLK_FREQ_CHANGE_CNTL__VI;
typedef union DISPPLL_BG_CNTL__VI              regDISPPLL_BG_CNTL__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE3__VI regDISP_INTERRUPT_STATUS_CONTINUE3__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE4__VI regDISP_INTERRUPT_STATUS_CONTINUE4__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE5__VI regDISP_INTERRUPT_STATUS_CONTINUE5__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE6__VI regDISP_INTERRUPT_STATUS_CONTINUE6__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE7__VI regDISP_INTERRUPT_STATUS_CONTINUE7__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE8__VI regDISP_INTERRUPT_STATUS_CONTINUE8__VI;
typedef union DISP_INTERRUPT_STATUS_CONTINUE9__VI regDISP_INTERRUPT_STATUS_CONTINUE9__VI;
typedef union DMCU_DPRX_INTERRUPT_STATUS1__VI  regDMCU_DPRX_INTERRUPT_STATUS1__VI;
typedef union DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__VI regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__VI;
typedef union DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI;
typedef union DMCU_PERFMON_INTERRUPT_STATUS1__VI regDMCU_PERFMON_INTERRUPT_STATUS1__VI;
typedef union DMCU_PERFMON_INTERRUPT_STATUS2__VI regDMCU_PERFMON_INTERRUPT_STATUS2__VI;
typedef union DMCU_PERFMON_INTERRUPT_STATUS3__VI regDMCU_PERFMON_INTERRUPT_STATUS3__VI;
typedef union DMCU_PERFMON_INTERRUPT_STATUS4__VI regDMCU_PERFMON_INTERRUPT_STATUS4__VI;
typedef union DMCU_PERFMON_INTERRUPT_STATUS5__VI regDMCU_PERFMON_INTERRUPT_STATUS5__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__VI regDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__VI regDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__VI regDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__VI regDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__VI regDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__VI regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__VI regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__VI regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__VI regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__VI regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__VI regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__VI regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__VI regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__VI;
typedef union DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__VI regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__VI;
typedef union DMCU_SMU_INTERRUPT_CNTL__VI      regDMCU_SMU_INTERRUPT_CNTL__VI;
typedef union DMCU_SS_INTERRUPT_CNTL_STATUS__VI regDMCU_SS_INTERRUPT_CNTL_STATUS__VI;
typedef union DMCU_UC_CLK_GATING_CNTL__VI      regDMCU_UC_CLK_GATING_CNTL__VI;
typedef union DMIF_ADDR_CALC__VI               regDMIF_ADDR_CALC__VI;
typedef union DMIF_ADDR_CONFIG__VI             regDMIF_ADDR_CONFIG__VI;
typedef union DMIF_DEBUG02_CORE0__VI           regDMIF_DEBUG02_CORE0__VI;
typedef union DMIF_DEBUG02_CORE1__VI           regDMIF_DEBUG02_CORE1__VI;
typedef union DMIF_P_VMID__VI                  regDMIF_P_VMID__VI;
typedef union DMIF_STATUS2__VI                 regDMIF_STATUS2__VI;
typedef union DMIF_URG_OVERRIDE__VI            regDMIF_URG_OVERRIDE__VI;
typedef union DPDBG_CLK_FORCE_CONTROL__VI      regDPDBG_CLK_FORCE_CONTROL__VI;
typedef union DPDBG_CNTL__VI                   regDPDBG_CNTL__VI;
typedef union DPDBG_INTERRUPT__VI              regDPDBG_INTERRUPT__VI;
typedef union DPG_HW_DEBUG_11__VI              regDPG_HW_DEBUG_11__VI;
typedef union DPG_HW_DEBUG_A__VI               regDPG_HW_DEBUG_A__VI;
typedef union DPG_HW_DEBUG_B__VI               regDPG_HW_DEBUG_B__VI;
typedef union DPG_PIPE_ARBITRATION_CONTROL1__VI regDPG_PIPE_ARBITRATION_CONTROL1__VI;
typedef union DPG_PIPE_ARBITRATION_CONTROL2__VI regDPG_PIPE_ARBITRATION_CONTROL2__VI;
typedef union DPG_PIPE_DPM_CONTROL__VI         regDPG_PIPE_DPM_CONTROL__VI;
typedef union DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI regDPG_PIPE_NB_PSTATE_CHANGE_CONTROL__VI;
typedef union DPG_PIPE_STUTTER_CONTROL__VI     regDPG_PIPE_STUTTER_CONTROL__VI;
typedef union DPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI regDPG_PIPE_STUTTER_CONTROL_NONLPTCH__VI;
typedef union DPG_PIPE_URGENCY_CONTROL__VI     regDPG_PIPE_URGENCY_CONTROL__VI;
typedef union DPG_REPEATER_PROGRAM__VI         regDPG_REPEATER_PROGRAM__VI;
typedef union DPG_TEST_DEBUG_DATA__VI          regDPG_TEST_DEBUG_DATA__VI;
typedef union DPG_TEST_DEBUG_INDEX__VI         regDPG_TEST_DEBUG_INDEX__VI;
typedef union DPG_WATERMARK_MASK_CONTROL__VI   regDPG_WATERMARK_MASK_CONTROL__VI;
typedef union DPHY_MACRO_CNTL_RESERVED0__VI    regDPHY_MACRO_CNTL_RESERVED0__VI;
typedef union DPHY_MACRO_CNTL_RESERVED1__VI    regDPHY_MACRO_CNTL_RESERVED1__VI;
typedef union DPHY_MACRO_CNTL_RESERVED10__VI   regDPHY_MACRO_CNTL_RESERVED10__VI;
typedef union DPHY_MACRO_CNTL_RESERVED11__VI   regDPHY_MACRO_CNTL_RESERVED11__VI;
typedef union DPHY_MACRO_CNTL_RESERVED12__VI   regDPHY_MACRO_CNTL_RESERVED12__VI;
typedef union DPHY_MACRO_CNTL_RESERVED13__VI   regDPHY_MACRO_CNTL_RESERVED13__VI;
typedef union DPHY_MACRO_CNTL_RESERVED14__VI   regDPHY_MACRO_CNTL_RESERVED14__VI;
typedef union DPHY_MACRO_CNTL_RESERVED15__VI   regDPHY_MACRO_CNTL_RESERVED15__VI;
typedef union DPHY_MACRO_CNTL_RESERVED16__VI   regDPHY_MACRO_CNTL_RESERVED16__VI;
typedef union DPHY_MACRO_CNTL_RESERVED17__VI   regDPHY_MACRO_CNTL_RESERVED17__VI;
typedef union DPHY_MACRO_CNTL_RESERVED18__VI   regDPHY_MACRO_CNTL_RESERVED18__VI;
typedef union DPHY_MACRO_CNTL_RESERVED19__VI   regDPHY_MACRO_CNTL_RESERVED19__VI;
typedef union DPHY_MACRO_CNTL_RESERVED2__VI    regDPHY_MACRO_CNTL_RESERVED2__VI;
typedef union DPHY_MACRO_CNTL_RESERVED20__VI   regDPHY_MACRO_CNTL_RESERVED20__VI;
typedef union DPHY_MACRO_CNTL_RESERVED21__VI   regDPHY_MACRO_CNTL_RESERVED21__VI;
typedef union DPHY_MACRO_CNTL_RESERVED22__VI   regDPHY_MACRO_CNTL_RESERVED22__VI;
typedef union DPHY_MACRO_CNTL_RESERVED23__VI   regDPHY_MACRO_CNTL_RESERVED23__VI;
typedef union DPHY_MACRO_CNTL_RESERVED24__VI   regDPHY_MACRO_CNTL_RESERVED24__VI;
typedef union DPHY_MACRO_CNTL_RESERVED25__VI   regDPHY_MACRO_CNTL_RESERVED25__VI;
typedef union DPHY_MACRO_CNTL_RESERVED26__VI   regDPHY_MACRO_CNTL_RESERVED26__VI;
typedef union DPHY_MACRO_CNTL_RESERVED27__VI   regDPHY_MACRO_CNTL_RESERVED27__VI;
typedef union DPHY_MACRO_CNTL_RESERVED28__VI   regDPHY_MACRO_CNTL_RESERVED28__VI;
typedef union DPHY_MACRO_CNTL_RESERVED29__VI   regDPHY_MACRO_CNTL_RESERVED29__VI;
typedef union DPHY_MACRO_CNTL_RESERVED3__VI    regDPHY_MACRO_CNTL_RESERVED3__VI;
typedef union DPHY_MACRO_CNTL_RESERVED30__VI   regDPHY_MACRO_CNTL_RESERVED30__VI;
typedef union DPHY_MACRO_CNTL_RESERVED31__VI   regDPHY_MACRO_CNTL_RESERVED31__VI;
typedef union DPHY_MACRO_CNTL_RESERVED32__VI   regDPHY_MACRO_CNTL_RESERVED32__VI;
typedef union DPHY_MACRO_CNTL_RESERVED33__VI   regDPHY_MACRO_CNTL_RESERVED33__VI;
typedef union DPHY_MACRO_CNTL_RESERVED34__VI   regDPHY_MACRO_CNTL_RESERVED34__VI;
typedef union DPHY_MACRO_CNTL_RESERVED35__VI   regDPHY_MACRO_CNTL_RESERVED35__VI;
typedef union DPHY_MACRO_CNTL_RESERVED36__VI   regDPHY_MACRO_CNTL_RESERVED36__VI;
typedef union DPHY_MACRO_CNTL_RESERVED37__VI   regDPHY_MACRO_CNTL_RESERVED37__VI;
typedef union DPHY_MACRO_CNTL_RESERVED38__VI   regDPHY_MACRO_CNTL_RESERVED38__VI;
typedef union DPHY_MACRO_CNTL_RESERVED39__VI   regDPHY_MACRO_CNTL_RESERVED39__VI;
typedef union DPHY_MACRO_CNTL_RESERVED4__VI    regDPHY_MACRO_CNTL_RESERVED4__VI;
typedef union DPHY_MACRO_CNTL_RESERVED40__VI   regDPHY_MACRO_CNTL_RESERVED40__VI;
typedef union DPHY_MACRO_CNTL_RESERVED41__VI   regDPHY_MACRO_CNTL_RESERVED41__VI;
typedef union DPHY_MACRO_CNTL_RESERVED42__VI   regDPHY_MACRO_CNTL_RESERVED42__VI;
typedef union DPHY_MACRO_CNTL_RESERVED43__VI   regDPHY_MACRO_CNTL_RESERVED43__VI;
typedef union DPHY_MACRO_CNTL_RESERVED44__VI   regDPHY_MACRO_CNTL_RESERVED44__VI;
typedef union DPHY_MACRO_CNTL_RESERVED45__VI   regDPHY_MACRO_CNTL_RESERVED45__VI;
typedef union DPHY_MACRO_CNTL_RESERVED46__VI   regDPHY_MACRO_CNTL_RESERVED46__VI;
typedef union DPHY_MACRO_CNTL_RESERVED47__VI   regDPHY_MACRO_CNTL_RESERVED47__VI;
typedef union DPHY_MACRO_CNTL_RESERVED48__VI   regDPHY_MACRO_CNTL_RESERVED48__VI;
typedef union DPHY_MACRO_CNTL_RESERVED49__VI   regDPHY_MACRO_CNTL_RESERVED49__VI;
typedef union DPHY_MACRO_CNTL_RESERVED5__VI    regDPHY_MACRO_CNTL_RESERVED5__VI;
typedef union DPHY_MACRO_CNTL_RESERVED50__VI   regDPHY_MACRO_CNTL_RESERVED50__VI;
typedef union DPHY_MACRO_CNTL_RESERVED51__VI   regDPHY_MACRO_CNTL_RESERVED51__VI;
typedef union DPHY_MACRO_CNTL_RESERVED52__VI   regDPHY_MACRO_CNTL_RESERVED52__VI;
typedef union DPHY_MACRO_CNTL_RESERVED53__VI   regDPHY_MACRO_CNTL_RESERVED53__VI;
typedef union DPHY_MACRO_CNTL_RESERVED54__VI   regDPHY_MACRO_CNTL_RESERVED54__VI;
typedef union DPHY_MACRO_CNTL_RESERVED55__VI   regDPHY_MACRO_CNTL_RESERVED55__VI;
typedef union DPHY_MACRO_CNTL_RESERVED56__VI   regDPHY_MACRO_CNTL_RESERVED56__VI;
typedef union DPHY_MACRO_CNTL_RESERVED57__VI   regDPHY_MACRO_CNTL_RESERVED57__VI;
typedef union DPHY_MACRO_CNTL_RESERVED58__VI   regDPHY_MACRO_CNTL_RESERVED58__VI;
typedef union DPHY_MACRO_CNTL_RESERVED59__VI   regDPHY_MACRO_CNTL_RESERVED59__VI;
typedef union DPHY_MACRO_CNTL_RESERVED6__VI    regDPHY_MACRO_CNTL_RESERVED6__VI;
typedef union DPHY_MACRO_CNTL_RESERVED60__VI   regDPHY_MACRO_CNTL_RESERVED60__VI;
typedef union DPHY_MACRO_CNTL_RESERVED61__VI   regDPHY_MACRO_CNTL_RESERVED61__VI;
typedef union DPHY_MACRO_CNTL_RESERVED62__VI   regDPHY_MACRO_CNTL_RESERVED62__VI;
typedef union DPHY_MACRO_CNTL_RESERVED63__VI   regDPHY_MACRO_CNTL_RESERVED63__VI;
typedef union DPHY_MACRO_CNTL_RESERVED7__VI    regDPHY_MACRO_CNTL_RESERVED7__VI;
typedef union DPHY_MACRO_CNTL_RESERVED8__VI    regDPHY_MACRO_CNTL_RESERVED8__VI;
typedef union DPHY_MACRO_CNTL_RESERVED9__VI    regDPHY_MACRO_CNTL_RESERVED9__VI;
typedef union DPM_TABLE_1__VI                  regDPM_TABLE_1__VI;
typedef union DPM_TABLE_10__VI                 regDPM_TABLE_10__VI;
typedef union DPM_TABLE_100__VI                regDPM_TABLE_100__VI;
typedef union DPM_TABLE_101__VI                regDPM_TABLE_101__VI;
typedef union DPM_TABLE_102__VI                regDPM_TABLE_102__VI;
typedef union DPM_TABLE_103__VI                regDPM_TABLE_103__VI;
typedef union DPM_TABLE_104__VI                regDPM_TABLE_104__VI;
typedef union DPM_TABLE_105__VI                regDPM_TABLE_105__VI;
typedef union DPM_TABLE_106__VI                regDPM_TABLE_106__VI;
typedef union DPM_TABLE_107__VI                regDPM_TABLE_107__VI;
typedef union DPM_TABLE_108__VI                regDPM_TABLE_108__VI;
typedef union DPM_TABLE_109__VI                regDPM_TABLE_109__VI;
typedef union DPM_TABLE_11__VI                 regDPM_TABLE_11__VI;
typedef union DPM_TABLE_110__VI                regDPM_TABLE_110__VI;
typedef union DPM_TABLE_111__VI                regDPM_TABLE_111__VI;
typedef union DPM_TABLE_112__VI                regDPM_TABLE_112__VI;
typedef union DPM_TABLE_113__VI                regDPM_TABLE_113__VI;
typedef union DPM_TABLE_114__VI                regDPM_TABLE_114__VI;
typedef union DPM_TABLE_115__VI                regDPM_TABLE_115__VI;
typedef union DPM_TABLE_116__VI                regDPM_TABLE_116__VI;
typedef union DPM_TABLE_117__VI                regDPM_TABLE_117__VI;
typedef union DPM_TABLE_118__VI                regDPM_TABLE_118__VI;
typedef union DPM_TABLE_119__VI                regDPM_TABLE_119__VI;
typedef union DPM_TABLE_12__VI                 regDPM_TABLE_12__VI;
typedef union DPM_TABLE_120__VI                regDPM_TABLE_120__VI;
typedef union DPM_TABLE_121__VI                regDPM_TABLE_121__VI;
typedef union DPM_TABLE_122__VI                regDPM_TABLE_122__VI;
typedef union DPM_TABLE_123__VI                regDPM_TABLE_123__VI;
typedef union DPM_TABLE_124__VI                regDPM_TABLE_124__VI;
typedef union DPM_TABLE_125__VI                regDPM_TABLE_125__VI;
typedef union DPM_TABLE_126__VI                regDPM_TABLE_126__VI;
typedef union DPM_TABLE_127__VI                regDPM_TABLE_127__VI;
typedef union DPM_TABLE_128__VI                regDPM_TABLE_128__VI;
typedef union DPM_TABLE_129__VI                regDPM_TABLE_129__VI;
typedef union DPM_TABLE_13__VI                 regDPM_TABLE_13__VI;
typedef union DPM_TABLE_130__VI                regDPM_TABLE_130__VI;
typedef union DPM_TABLE_131__VI                regDPM_TABLE_131__VI;
typedef union DPM_TABLE_132__VI                regDPM_TABLE_132__VI;
typedef union DPM_TABLE_133__VI                regDPM_TABLE_133__VI;
typedef union DPM_TABLE_134__VI                regDPM_TABLE_134__VI;
typedef union DPM_TABLE_135__VI                regDPM_TABLE_135__VI;
typedef union DPM_TABLE_136__VI                regDPM_TABLE_136__VI;
typedef union DPM_TABLE_137__VI                regDPM_TABLE_137__VI;
typedef union DPM_TABLE_138__VI                regDPM_TABLE_138__VI;
typedef union DPM_TABLE_139__VI                regDPM_TABLE_139__VI;
typedef union DPM_TABLE_14__VI                 regDPM_TABLE_14__VI;
typedef union DPM_TABLE_140__VI                regDPM_TABLE_140__VI;
typedef union DPM_TABLE_141__VI                regDPM_TABLE_141__VI;
typedef union DPM_TABLE_142__VI                regDPM_TABLE_142__VI;
typedef union DPM_TABLE_143__VI                regDPM_TABLE_143__VI;
typedef union DPM_TABLE_144__VI                regDPM_TABLE_144__VI;
typedef union DPM_TABLE_145__VI                regDPM_TABLE_145__VI;
typedef union DPM_TABLE_146__VI                regDPM_TABLE_146__VI;
typedef union DPM_TABLE_147__VI                regDPM_TABLE_147__VI;
typedef union DPM_TABLE_148__VI                regDPM_TABLE_148__VI;
typedef union DPM_TABLE_149__VI                regDPM_TABLE_149__VI;
typedef union DPM_TABLE_15__VI                 regDPM_TABLE_15__VI;
typedef union DPM_TABLE_150__VI                regDPM_TABLE_150__VI;
typedef union DPM_TABLE_151__VI                regDPM_TABLE_151__VI;
typedef union DPM_TABLE_152__VI                regDPM_TABLE_152__VI;
typedef union DPM_TABLE_153__VI                regDPM_TABLE_153__VI;
typedef union DPM_TABLE_154__VI                regDPM_TABLE_154__VI;
typedef union DPM_TABLE_155__VI                regDPM_TABLE_155__VI;
typedef union DPM_TABLE_156__VI                regDPM_TABLE_156__VI;
typedef union DPM_TABLE_157__VI                regDPM_TABLE_157__VI;
typedef union DPM_TABLE_158__VI                regDPM_TABLE_158__VI;
typedef union DPM_TABLE_159__VI                regDPM_TABLE_159__VI;
typedef union DPM_TABLE_16__VI                 regDPM_TABLE_16__VI;
typedef union DPM_TABLE_160__VI                regDPM_TABLE_160__VI;
typedef union DPM_TABLE_161__VI                regDPM_TABLE_161__VI;
typedef union DPM_TABLE_162__VI                regDPM_TABLE_162__VI;
typedef union DPM_TABLE_163__VI                regDPM_TABLE_163__VI;
typedef union DPM_TABLE_164__VI                regDPM_TABLE_164__VI;
typedef union DPM_TABLE_165__VI                regDPM_TABLE_165__VI;
typedef union DPM_TABLE_166__VI                regDPM_TABLE_166__VI;
typedef union DPM_TABLE_167__VI                regDPM_TABLE_167__VI;
typedef union DPM_TABLE_168__VI                regDPM_TABLE_168__VI;
typedef union DPM_TABLE_169__VI                regDPM_TABLE_169__VI;
typedef union DPM_TABLE_17__VI                 regDPM_TABLE_17__VI;
typedef union DPM_TABLE_170__VI                regDPM_TABLE_170__VI;
typedef union DPM_TABLE_171__VI                regDPM_TABLE_171__VI;
typedef union DPM_TABLE_172__VI                regDPM_TABLE_172__VI;
typedef union DPM_TABLE_173__VI                regDPM_TABLE_173__VI;
typedef union DPM_TABLE_174__VI                regDPM_TABLE_174__VI;
typedef union DPM_TABLE_175__VI                regDPM_TABLE_175__VI;
typedef union DPM_TABLE_176__VI                regDPM_TABLE_176__VI;
typedef union DPM_TABLE_177__VI                regDPM_TABLE_177__VI;
typedef union DPM_TABLE_178__VI                regDPM_TABLE_178__VI;
typedef union DPM_TABLE_179__VI                regDPM_TABLE_179__VI;
typedef union DPM_TABLE_18__VI                 regDPM_TABLE_18__VI;
typedef union DPM_TABLE_180__VI                regDPM_TABLE_180__VI;
typedef union DPM_TABLE_181__VI                regDPM_TABLE_181__VI;
typedef union DPM_TABLE_182__VI                regDPM_TABLE_182__VI;
typedef union DPM_TABLE_183__VI                regDPM_TABLE_183__VI;
typedef union DPM_TABLE_184__VI                regDPM_TABLE_184__VI;
typedef union DPM_TABLE_185__VI                regDPM_TABLE_185__VI;
typedef union DPM_TABLE_186__VI                regDPM_TABLE_186__VI;
typedef union DPM_TABLE_187__VI                regDPM_TABLE_187__VI;
typedef union DPM_TABLE_188__VI                regDPM_TABLE_188__VI;
typedef union DPM_TABLE_189__VI                regDPM_TABLE_189__VI;
typedef union DPM_TABLE_19__VI                 regDPM_TABLE_19__VI;
typedef union DPM_TABLE_190__VI                regDPM_TABLE_190__VI;
typedef union DPM_TABLE_191__VI                regDPM_TABLE_191__VI;
typedef union DPM_TABLE_192__VI                regDPM_TABLE_192__VI;
typedef union DPM_TABLE_193__VI                regDPM_TABLE_193__VI;
typedef union DPM_TABLE_194__VI                regDPM_TABLE_194__VI;
typedef union DPM_TABLE_195__VI                regDPM_TABLE_195__VI;
typedef union DPM_TABLE_196__VI                regDPM_TABLE_196__VI;
typedef union DPM_TABLE_197__VI                regDPM_TABLE_197__VI;
typedef union DPM_TABLE_198__VI                regDPM_TABLE_198__VI;
typedef union DPM_TABLE_199__VI                regDPM_TABLE_199__VI;
typedef union DPM_TABLE_2__VI                  regDPM_TABLE_2__VI;
typedef union DPM_TABLE_20__VI                 regDPM_TABLE_20__VI;
typedef union DPM_TABLE_200__VI                regDPM_TABLE_200__VI;
typedef union DPM_TABLE_201__VI                regDPM_TABLE_201__VI;
typedef union DPM_TABLE_202__VI                regDPM_TABLE_202__VI;
typedef union DPM_TABLE_203__VI                regDPM_TABLE_203__VI;
typedef union DPM_TABLE_204__VI                regDPM_TABLE_204__VI;
typedef union DPM_TABLE_205__VI                regDPM_TABLE_205__VI;
typedef union DPM_TABLE_206__VI                regDPM_TABLE_206__VI;
typedef union DPM_TABLE_207__VI                regDPM_TABLE_207__VI;
typedef union DPM_TABLE_208__VI                regDPM_TABLE_208__VI;
typedef union DPM_TABLE_209__VI                regDPM_TABLE_209__VI;
typedef union DPM_TABLE_21__VI                 regDPM_TABLE_21__VI;
typedef union DPM_TABLE_210__VI                regDPM_TABLE_210__VI;
typedef union DPM_TABLE_211__VI                regDPM_TABLE_211__VI;
typedef union DPM_TABLE_212__VI                regDPM_TABLE_212__VI;
typedef union DPM_TABLE_213__VI                regDPM_TABLE_213__VI;
typedef union DPM_TABLE_214__VI                regDPM_TABLE_214__VI;
typedef union DPM_TABLE_215__VI                regDPM_TABLE_215__VI;
typedef union DPM_TABLE_216__VI                regDPM_TABLE_216__VI;
typedef union DPM_TABLE_217__VI                regDPM_TABLE_217__VI;
typedef union DPM_TABLE_218__VI                regDPM_TABLE_218__VI;
typedef union DPM_TABLE_219__VI                regDPM_TABLE_219__VI;
typedef union DPM_TABLE_22__VI                 regDPM_TABLE_22__VI;
typedef union DPM_TABLE_220__VI                regDPM_TABLE_220__VI;
typedef union DPM_TABLE_221__VI                regDPM_TABLE_221__VI;
typedef union DPM_TABLE_222__VI                regDPM_TABLE_222__VI;
typedef union DPM_TABLE_223__VI                regDPM_TABLE_223__VI;
typedef union DPM_TABLE_224__VI                regDPM_TABLE_224__VI;
typedef union DPM_TABLE_225__VI                regDPM_TABLE_225__VI;
typedef union DPM_TABLE_226__VI                regDPM_TABLE_226__VI;
typedef union DPM_TABLE_227__VI                regDPM_TABLE_227__VI;
typedef union DPM_TABLE_228__VI                regDPM_TABLE_228__VI;
typedef union DPM_TABLE_229__VI                regDPM_TABLE_229__VI;
typedef union DPM_TABLE_23__VI                 regDPM_TABLE_23__VI;
typedef union DPM_TABLE_230__VI                regDPM_TABLE_230__VI;
typedef union DPM_TABLE_231__VI                regDPM_TABLE_231__VI;
typedef union DPM_TABLE_232__VI                regDPM_TABLE_232__VI;
typedef union DPM_TABLE_233__VI                regDPM_TABLE_233__VI;
typedef union DPM_TABLE_234__VI                regDPM_TABLE_234__VI;
typedef union DPM_TABLE_235__VI                regDPM_TABLE_235__VI;
typedef union DPM_TABLE_236__VI                regDPM_TABLE_236__VI;
typedef union DPM_TABLE_237__VI                regDPM_TABLE_237__VI;
typedef union DPM_TABLE_238__VI                regDPM_TABLE_238__VI;
typedef union DPM_TABLE_239__VI                regDPM_TABLE_239__VI;
typedef union DPM_TABLE_24__VI                 regDPM_TABLE_24__VI;
typedef union DPM_TABLE_240__VI                regDPM_TABLE_240__VI;
typedef union DPM_TABLE_241__VI                regDPM_TABLE_241__VI;
typedef union DPM_TABLE_242__VI                regDPM_TABLE_242__VI;
typedef union DPM_TABLE_243__VI                regDPM_TABLE_243__VI;
typedef union DPM_TABLE_244__VI                regDPM_TABLE_244__VI;
typedef union DPM_TABLE_245__VI                regDPM_TABLE_245__VI;
typedef union DPM_TABLE_246__VI                regDPM_TABLE_246__VI;
typedef union DPM_TABLE_247__VI                regDPM_TABLE_247__VI;
typedef union DPM_TABLE_248__VI                regDPM_TABLE_248__VI;
typedef union DPM_TABLE_249__VI                regDPM_TABLE_249__VI;
typedef union DPM_TABLE_25__VI                 regDPM_TABLE_25__VI;
typedef union DPM_TABLE_250__VI                regDPM_TABLE_250__VI;
typedef union DPM_TABLE_251__VI                regDPM_TABLE_251__VI;
typedef union DPM_TABLE_252__VI                regDPM_TABLE_252__VI;
typedef union DPM_TABLE_253__VI                regDPM_TABLE_253__VI;
typedef union DPM_TABLE_254__VI                regDPM_TABLE_254__VI;
typedef union DPM_TABLE_255__VI                regDPM_TABLE_255__VI;
typedef union DPM_TABLE_256__VI                regDPM_TABLE_256__VI;
typedef union DPM_TABLE_257__VI                regDPM_TABLE_257__VI;
typedef union DPM_TABLE_258__VI                regDPM_TABLE_258__VI;
typedef union DPM_TABLE_259__VI                regDPM_TABLE_259__VI;
typedef union DPM_TABLE_26__VI                 regDPM_TABLE_26__VI;
typedef union DPM_TABLE_260__VI                regDPM_TABLE_260__VI;
typedef union DPM_TABLE_261__VI                regDPM_TABLE_261__VI;
typedef union DPM_TABLE_262__VI                regDPM_TABLE_262__VI;
typedef union DPM_TABLE_263__VI                regDPM_TABLE_263__VI;
typedef union DPM_TABLE_264__VI                regDPM_TABLE_264__VI;
typedef union DPM_TABLE_265__VI                regDPM_TABLE_265__VI;
typedef union DPM_TABLE_266__VI                regDPM_TABLE_266__VI;
typedef union DPM_TABLE_267__VI                regDPM_TABLE_267__VI;
typedef union DPM_TABLE_268__VI                regDPM_TABLE_268__VI;
typedef union DPM_TABLE_269__VI                regDPM_TABLE_269__VI;
typedef union DPM_TABLE_27__VI                 regDPM_TABLE_27__VI;
typedef union DPM_TABLE_270__VI                regDPM_TABLE_270__VI;
typedef union DPM_TABLE_271__VI                regDPM_TABLE_271__VI;
typedef union DPM_TABLE_272__VI                regDPM_TABLE_272__VI;
typedef union DPM_TABLE_273__VI                regDPM_TABLE_273__VI;
typedef union DPM_TABLE_274__VI                regDPM_TABLE_274__VI;
typedef union DPM_TABLE_275__VI                regDPM_TABLE_275__VI;
typedef union DPM_TABLE_276__VI                regDPM_TABLE_276__VI;
typedef union DPM_TABLE_277__VI                regDPM_TABLE_277__VI;
typedef union DPM_TABLE_278__VI                regDPM_TABLE_278__VI;
typedef union DPM_TABLE_279__VI                regDPM_TABLE_279__VI;
typedef union DPM_TABLE_28__VI                 regDPM_TABLE_28__VI;
typedef union DPM_TABLE_280__VI                regDPM_TABLE_280__VI;
typedef union DPM_TABLE_281__VI                regDPM_TABLE_281__VI;
typedef union DPM_TABLE_282__VI                regDPM_TABLE_282__VI;
typedef union DPM_TABLE_283__VI                regDPM_TABLE_283__VI;
typedef union DPM_TABLE_284__VI                regDPM_TABLE_284__VI;
typedef union DPM_TABLE_285__VI                regDPM_TABLE_285__VI;
typedef union DPM_TABLE_286__VI                regDPM_TABLE_286__VI;
typedef union DPM_TABLE_287__VI                regDPM_TABLE_287__VI;
typedef union DPM_TABLE_288__VI                regDPM_TABLE_288__VI;
typedef union DPM_TABLE_289__VI                regDPM_TABLE_289__VI;
typedef union DPM_TABLE_29__VI                 regDPM_TABLE_29__VI;
typedef union DPM_TABLE_290__VI                regDPM_TABLE_290__VI;
typedef union DPM_TABLE_291__VI                regDPM_TABLE_291__VI;
typedef union DPM_TABLE_292__VI                regDPM_TABLE_292__VI;
typedef union DPM_TABLE_293__VI                regDPM_TABLE_293__VI;
typedef union DPM_TABLE_294__VI                regDPM_TABLE_294__VI;
typedef union DPM_TABLE_295__VI                regDPM_TABLE_295__VI;
typedef union DPM_TABLE_296__VI                regDPM_TABLE_296__VI;
typedef union DPM_TABLE_297__VI                regDPM_TABLE_297__VI;
typedef union DPM_TABLE_298__VI                regDPM_TABLE_298__VI;
typedef union DPM_TABLE_299__VI                regDPM_TABLE_299__VI;
typedef union DPM_TABLE_3__VI                  regDPM_TABLE_3__VI;
typedef union DPM_TABLE_30__VI                 regDPM_TABLE_30__VI;
typedef union DPM_TABLE_300__VI                regDPM_TABLE_300__VI;
typedef union DPM_TABLE_301__VI                regDPM_TABLE_301__VI;
typedef union DPM_TABLE_302__VI                regDPM_TABLE_302__VI;
typedef union DPM_TABLE_303__VI                regDPM_TABLE_303__VI;
typedef union DPM_TABLE_304__VI                regDPM_TABLE_304__VI;
typedef union DPM_TABLE_305__VI                regDPM_TABLE_305__VI;
typedef union DPM_TABLE_306__VI                regDPM_TABLE_306__VI;
typedef union DPM_TABLE_307__VI                regDPM_TABLE_307__VI;
typedef union DPM_TABLE_308__VI                regDPM_TABLE_308__VI;
typedef union DPM_TABLE_309__VI                regDPM_TABLE_309__VI;
typedef union DPM_TABLE_31__VI                 regDPM_TABLE_31__VI;
typedef union DPM_TABLE_310__VI                regDPM_TABLE_310__VI;
typedef union DPM_TABLE_311__VI                regDPM_TABLE_311__VI;
typedef union DPM_TABLE_312__VI                regDPM_TABLE_312__VI;
typedef union DPM_TABLE_313__VI                regDPM_TABLE_313__VI;
typedef union DPM_TABLE_314__VI                regDPM_TABLE_314__VI;
typedef union DPM_TABLE_315__VI                regDPM_TABLE_315__VI;
typedef union DPM_TABLE_316__VI                regDPM_TABLE_316__VI;
typedef union DPM_TABLE_317__VI                regDPM_TABLE_317__VI;
typedef union DPM_TABLE_318__VI                regDPM_TABLE_318__VI;
typedef union DPM_TABLE_319__VI                regDPM_TABLE_319__VI;
typedef union DPM_TABLE_32__VI                 regDPM_TABLE_32__VI;
typedef union DPM_TABLE_320__VI                regDPM_TABLE_320__VI;
typedef union DPM_TABLE_321__VI                regDPM_TABLE_321__VI;
typedef union DPM_TABLE_322__VI                regDPM_TABLE_322__VI;
typedef union DPM_TABLE_323__VI                regDPM_TABLE_323__VI;
typedef union DPM_TABLE_324__VI                regDPM_TABLE_324__VI;
typedef union DPM_TABLE_325__VI                regDPM_TABLE_325__VI;
typedef union DPM_TABLE_326__VI                regDPM_TABLE_326__VI;
typedef union DPM_TABLE_327__VI                regDPM_TABLE_327__VI;
typedef union DPM_TABLE_328__VI                regDPM_TABLE_328__VI;
typedef union DPM_TABLE_329__VI                regDPM_TABLE_329__VI;
typedef union DPM_TABLE_33__VI                 regDPM_TABLE_33__VI;
typedef union DPM_TABLE_330__VI                regDPM_TABLE_330__VI;
typedef union DPM_TABLE_331__VI                regDPM_TABLE_331__VI;
typedef union DPM_TABLE_332__VI                regDPM_TABLE_332__VI;
typedef union DPM_TABLE_333__VI                regDPM_TABLE_333__VI;
typedef union DPM_TABLE_334__VI                regDPM_TABLE_334__VI;
typedef union DPM_TABLE_335__VI                regDPM_TABLE_335__VI;
typedef union DPM_TABLE_336__VI                regDPM_TABLE_336__VI;
typedef union DPM_TABLE_337__VI                regDPM_TABLE_337__VI;
typedef union DPM_TABLE_338__VI                regDPM_TABLE_338__VI;
typedef union DPM_TABLE_339__VI                regDPM_TABLE_339__VI;
typedef union DPM_TABLE_34__VI                 regDPM_TABLE_34__VI;
typedef union DPM_TABLE_340__VI                regDPM_TABLE_340__VI;
typedef union DPM_TABLE_341__VI                regDPM_TABLE_341__VI;
typedef union DPM_TABLE_342__VI                regDPM_TABLE_342__VI;
typedef union DPM_TABLE_343__VI                regDPM_TABLE_343__VI;
typedef union DPM_TABLE_344__VI                regDPM_TABLE_344__VI;
typedef union DPM_TABLE_345__VI                regDPM_TABLE_345__VI;
typedef union DPM_TABLE_346__VI                regDPM_TABLE_346__VI;
typedef union DPM_TABLE_347__VI                regDPM_TABLE_347__VI;
typedef union DPM_TABLE_348__VI                regDPM_TABLE_348__VI;
typedef union DPM_TABLE_349__VI                regDPM_TABLE_349__VI;
typedef union DPM_TABLE_35__VI                 regDPM_TABLE_35__VI;
typedef union DPM_TABLE_350__VI                regDPM_TABLE_350__VI;
typedef union DPM_TABLE_351__VI                regDPM_TABLE_351__VI;
typedef union DPM_TABLE_352__VI                regDPM_TABLE_352__VI;
typedef union DPM_TABLE_353__VI                regDPM_TABLE_353__VI;
typedef union DPM_TABLE_354__VI                regDPM_TABLE_354__VI;
typedef union DPM_TABLE_355__VI                regDPM_TABLE_355__VI;
typedef union DPM_TABLE_356__VI                regDPM_TABLE_356__VI;
typedef union DPM_TABLE_357__VI                regDPM_TABLE_357__VI;
typedef union DPM_TABLE_358__VI                regDPM_TABLE_358__VI;
typedef union DPM_TABLE_359__VI                regDPM_TABLE_359__VI;
typedef union DPM_TABLE_36__VI                 regDPM_TABLE_36__VI;
typedef union DPM_TABLE_360__VI                regDPM_TABLE_360__VI;
typedef union DPM_TABLE_361__VI                regDPM_TABLE_361__VI;
typedef union DPM_TABLE_362__VI                regDPM_TABLE_362__VI;
typedef union DPM_TABLE_363__VI                regDPM_TABLE_363__VI;
typedef union DPM_TABLE_364__VI                regDPM_TABLE_364__VI;
typedef union DPM_TABLE_365__VI                regDPM_TABLE_365__VI;
typedef union DPM_TABLE_366__VI                regDPM_TABLE_366__VI;
typedef union DPM_TABLE_367__VI                regDPM_TABLE_367__VI;
typedef union DPM_TABLE_368__VI                regDPM_TABLE_368__VI;
typedef union DPM_TABLE_369__VI                regDPM_TABLE_369__VI;
typedef union DPM_TABLE_37__VI                 regDPM_TABLE_37__VI;
typedef union DPM_TABLE_370__VI                regDPM_TABLE_370__VI;
typedef union DPM_TABLE_371__VI                regDPM_TABLE_371__VI;
typedef union DPM_TABLE_372__VI                regDPM_TABLE_372__VI;
typedef union DPM_TABLE_373__VI                regDPM_TABLE_373__VI;
typedef union DPM_TABLE_374__VI                regDPM_TABLE_374__VI;
typedef union DPM_TABLE_375__VI                regDPM_TABLE_375__VI;
typedef union DPM_TABLE_376__VI                regDPM_TABLE_376__VI;
typedef union DPM_TABLE_377__VI                regDPM_TABLE_377__VI;
typedef union DPM_TABLE_378__VI                regDPM_TABLE_378__VI;
typedef union DPM_TABLE_379__VI                regDPM_TABLE_379__VI;
typedef union DPM_TABLE_38__VI                 regDPM_TABLE_38__VI;
typedef union DPM_TABLE_380__VI                regDPM_TABLE_380__VI;
typedef union DPM_TABLE_381__VI                regDPM_TABLE_381__VI;
typedef union DPM_TABLE_382__VI                regDPM_TABLE_382__VI;
typedef union DPM_TABLE_383__VI                regDPM_TABLE_383__VI;
typedef union DPM_TABLE_384__VI                regDPM_TABLE_384__VI;
typedef union DPM_TABLE_385__VI                regDPM_TABLE_385__VI;
typedef union DPM_TABLE_386__VI                regDPM_TABLE_386__VI;
typedef union DPM_TABLE_387__VI                regDPM_TABLE_387__VI;
typedef union DPM_TABLE_388__VI                regDPM_TABLE_388__VI;
typedef union DPM_TABLE_389__VI                regDPM_TABLE_389__VI;
typedef union DPM_TABLE_39__VI                 regDPM_TABLE_39__VI;
typedef union DPM_TABLE_390__VI                regDPM_TABLE_390__VI;
typedef union DPM_TABLE_391__VI                regDPM_TABLE_391__VI;
typedef union DPM_TABLE_392__VI                regDPM_TABLE_392__VI;
typedef union DPM_TABLE_393__VI                regDPM_TABLE_393__VI;
typedef union DPM_TABLE_394__VI                regDPM_TABLE_394__VI;
typedef union DPM_TABLE_395__VI                regDPM_TABLE_395__VI;
typedef union DPM_TABLE_396__VI                regDPM_TABLE_396__VI;
typedef union DPM_TABLE_397__VI                regDPM_TABLE_397__VI;
typedef union DPM_TABLE_398__VI                regDPM_TABLE_398__VI;
typedef union DPM_TABLE_399__VI                regDPM_TABLE_399__VI;
typedef union DPM_TABLE_4__VI                  regDPM_TABLE_4__VI;
typedef union DPM_TABLE_40__VI                 regDPM_TABLE_40__VI;
typedef union DPM_TABLE_400__VI                regDPM_TABLE_400__VI;
typedef union DPM_TABLE_401__VI                regDPM_TABLE_401__VI;
typedef union DPM_TABLE_402__VI                regDPM_TABLE_402__VI;
typedef union DPM_TABLE_403__VI                regDPM_TABLE_403__VI;
typedef union DPM_TABLE_404__VI                regDPM_TABLE_404__VI;
typedef union DPM_TABLE_405__VI                regDPM_TABLE_405__VI;
typedef union DPM_TABLE_406__VI                regDPM_TABLE_406__VI;
typedef union DPM_TABLE_407__VI                regDPM_TABLE_407__VI;
typedef union DPM_TABLE_408__VI                regDPM_TABLE_408__VI;
typedef union DPM_TABLE_409__VI                regDPM_TABLE_409__VI;
typedef union DPM_TABLE_41__VI                 regDPM_TABLE_41__VI;
typedef union DPM_TABLE_410__VI                regDPM_TABLE_410__VI;
typedef union DPM_TABLE_411__VI                regDPM_TABLE_411__VI;
typedef union DPM_TABLE_412__VI                regDPM_TABLE_412__VI;
typedef union DPM_TABLE_413__VI                regDPM_TABLE_413__VI;
typedef union DPM_TABLE_414__VI                regDPM_TABLE_414__VI;
typedef union DPM_TABLE_415__VI                regDPM_TABLE_415__VI;
typedef union DPM_TABLE_416__VI                regDPM_TABLE_416__VI;
typedef union DPM_TABLE_417__VI                regDPM_TABLE_417__VI;
typedef union DPM_TABLE_418__VI                regDPM_TABLE_418__VI;
typedef union DPM_TABLE_419__VI                regDPM_TABLE_419__VI;
typedef union DPM_TABLE_42__VI                 regDPM_TABLE_42__VI;
typedef union DPM_TABLE_420__VI                regDPM_TABLE_420__VI;
typedef union DPM_TABLE_421__VI                regDPM_TABLE_421__VI;
typedef union DPM_TABLE_422__VI                regDPM_TABLE_422__VI;
typedef union DPM_TABLE_423__VI                regDPM_TABLE_423__VI;
typedef union DPM_TABLE_424__VI                regDPM_TABLE_424__VI;
typedef union DPM_TABLE_425__VI                regDPM_TABLE_425__VI;
typedef union DPM_TABLE_426__VI                regDPM_TABLE_426__VI;
typedef union DPM_TABLE_427__VI                regDPM_TABLE_427__VI;
typedef union DPM_TABLE_428__VI                regDPM_TABLE_428__VI;
typedef union DPM_TABLE_429__VI                regDPM_TABLE_429__VI;
typedef union DPM_TABLE_43__VI                 regDPM_TABLE_43__VI;
typedef union DPM_TABLE_430__VI                regDPM_TABLE_430__VI;
typedef union DPM_TABLE_431__VI                regDPM_TABLE_431__VI;
typedef union DPM_TABLE_432__VI                regDPM_TABLE_432__VI;
typedef union DPM_TABLE_433__VI                regDPM_TABLE_433__VI;
typedef union DPM_TABLE_434__VI                regDPM_TABLE_434__VI;
typedef union DPM_TABLE_435__VI                regDPM_TABLE_435__VI;
typedef union DPM_TABLE_436__VI                regDPM_TABLE_436__VI;
typedef union DPM_TABLE_437__VI                regDPM_TABLE_437__VI;
typedef union DPM_TABLE_438__VI                regDPM_TABLE_438__VI;
typedef union DPM_TABLE_439__VI                regDPM_TABLE_439__VI;
typedef union DPM_TABLE_44__VI                 regDPM_TABLE_44__VI;
typedef union DPM_TABLE_440__VI                regDPM_TABLE_440__VI;
typedef union DPM_TABLE_45__VI                 regDPM_TABLE_45__VI;
typedef union DPM_TABLE_46__VI                 regDPM_TABLE_46__VI;
typedef union DPM_TABLE_47__VI                 regDPM_TABLE_47__VI;
typedef union DPM_TABLE_48__VI                 regDPM_TABLE_48__VI;
typedef union DPM_TABLE_49__VI                 regDPM_TABLE_49__VI;
typedef union DPM_TABLE_5__VI                  regDPM_TABLE_5__VI;
typedef union DPM_TABLE_50__VI                 regDPM_TABLE_50__VI;
typedef union DPM_TABLE_51__VI                 regDPM_TABLE_51__VI;
typedef union DPM_TABLE_52__VI                 regDPM_TABLE_52__VI;
typedef union DPM_TABLE_53__VI                 regDPM_TABLE_53__VI;
typedef union DPM_TABLE_54__VI                 regDPM_TABLE_54__VI;
typedef union DPM_TABLE_55__VI                 regDPM_TABLE_55__VI;
typedef union DPM_TABLE_56__VI                 regDPM_TABLE_56__VI;
typedef union DPM_TABLE_57__VI                 regDPM_TABLE_57__VI;
typedef union DPM_TABLE_58__VI                 regDPM_TABLE_58__VI;
typedef union DPM_TABLE_59__VI                 regDPM_TABLE_59__VI;
typedef union DPM_TABLE_6__VI                  regDPM_TABLE_6__VI;
typedef union DPM_TABLE_60__VI                 regDPM_TABLE_60__VI;
typedef union DPM_TABLE_61__VI                 regDPM_TABLE_61__VI;
typedef union DPM_TABLE_62__VI                 regDPM_TABLE_62__VI;
typedef union DPM_TABLE_63__VI                 regDPM_TABLE_63__VI;
typedef union DPM_TABLE_64__VI                 regDPM_TABLE_64__VI;
typedef union DPM_TABLE_65__VI                 regDPM_TABLE_65__VI;
typedef union DPM_TABLE_66__VI                 regDPM_TABLE_66__VI;
typedef union DPM_TABLE_67__VI                 regDPM_TABLE_67__VI;
typedef union DPM_TABLE_68__VI                 regDPM_TABLE_68__VI;
typedef union DPM_TABLE_69__VI                 regDPM_TABLE_69__VI;
typedef union DPM_TABLE_7__VI                  regDPM_TABLE_7__VI;
typedef union DPM_TABLE_70__VI                 regDPM_TABLE_70__VI;
typedef union DPM_TABLE_71__VI                 regDPM_TABLE_71__VI;
typedef union DPM_TABLE_72__VI                 regDPM_TABLE_72__VI;
typedef union DPM_TABLE_73__VI                 regDPM_TABLE_73__VI;
typedef union DPM_TABLE_74__VI                 regDPM_TABLE_74__VI;
typedef union DPM_TABLE_75__VI                 regDPM_TABLE_75__VI;
typedef union DPM_TABLE_76__VI                 regDPM_TABLE_76__VI;
typedef union DPM_TABLE_77__VI                 regDPM_TABLE_77__VI;
typedef union DPM_TABLE_78__VI                 regDPM_TABLE_78__VI;
typedef union DPM_TABLE_79__VI                 regDPM_TABLE_79__VI;
typedef union DPM_TABLE_8__VI                  regDPM_TABLE_8__VI;
typedef union DPM_TABLE_80__VI                 regDPM_TABLE_80__VI;
typedef union DPM_TABLE_81__VI                 regDPM_TABLE_81__VI;
typedef union DPM_TABLE_82__VI                 regDPM_TABLE_82__VI;
typedef union DPM_TABLE_83__VI                 regDPM_TABLE_83__VI;
typedef union DPM_TABLE_84__VI                 regDPM_TABLE_84__VI;
typedef union DPM_TABLE_85__VI                 regDPM_TABLE_85__VI;
typedef union DPM_TABLE_86__VI                 regDPM_TABLE_86__VI;
typedef union DPM_TABLE_87__VI                 regDPM_TABLE_87__VI;
typedef union DPM_TABLE_88__VI                 regDPM_TABLE_88__VI;
typedef union DPM_TABLE_89__VI                 regDPM_TABLE_89__VI;
typedef union DPM_TABLE_9__VI                  regDPM_TABLE_9__VI;
typedef union DPM_TABLE_90__VI                 regDPM_TABLE_90__VI;
typedef union DPM_TABLE_91__VI                 regDPM_TABLE_91__VI;
typedef union DPM_TABLE_92__VI                 regDPM_TABLE_92__VI;
typedef union DPM_TABLE_93__VI                 regDPM_TABLE_93__VI;
typedef union DPM_TABLE_94__VI                 regDPM_TABLE_94__VI;
typedef union DPM_TABLE_95__VI                 regDPM_TABLE_95__VI;
typedef union DPM_TABLE_96__VI                 regDPM_TABLE_96__VI;
typedef union DPM_TABLE_97__VI                 regDPM_TABLE_97__VI;
typedef union DPM_TABLE_98__VI                 regDPM_TABLE_98__VI;
typedef union DPM_TABLE_99__VI                 regDPM_TABLE_99__VI;
typedef union DPREFCLK_CGTT_BLK_CTRL_REG__VI   regDPREFCLK_CGTT_BLK_CTRL_REG__VI;
typedef union DPREFCLK_CNTL__VI                regDPREFCLK_CNTL__VI;
typedef union DP_AUX_DEBUG_A__VI               regDP_AUX_DEBUG_A__VI;
typedef union DP_AUX_DEBUG_B__VI               regDP_AUX_DEBUG_B__VI;
typedef union DP_AUX_DEBUG_C__VI               regDP_AUX_DEBUG_C__VI;
typedef union DP_AUX_DEBUG_D__VI               regDP_AUX_DEBUG_D__VI;
typedef union DP_AUX_DEBUG_E__VI               regDP_AUX_DEBUG_E__VI;
typedef union DP_AUX_DEBUG_F__VI               regDP_AUX_DEBUG_F__VI;
typedef union DP_AUX_DEBUG_G__VI               regDP_AUX_DEBUG_G__VI;
typedef union DP_AUX_DEBUG_H__VI               regDP_AUX_DEBUG_H__VI;
typedef union DP_AUX_DEBUG_I__VI               regDP_AUX_DEBUG_I__VI;
typedef union DP_AUX_DEBUG_J__VI               regDP_AUX_DEBUG_J__VI;
typedef union DP_AUX_DEBUG_K__VI               regDP_AUX_DEBUG_K__VI;
typedef union DP_AUX_DEBUG_L__VI               regDP_AUX_DEBUG_L__VI;
typedef union DP_AUX_DEBUG_M__VI               regDP_AUX_DEBUG_M__VI;
typedef union DP_AUX_DEBUG_N__VI               regDP_AUX_DEBUG_N__VI;
typedef union DP_AUX_DEBUG_O__VI               regDP_AUX_DEBUG_O__VI;
typedef union DP_AUX_DEBUG_P__VI               regDP_AUX_DEBUG_P__VI;
typedef union DP_AUX_DEBUG_Q__VI               regDP_AUX_DEBUG_Q__VI;
typedef union DP_DPHY_CRC_MST_CNTL__VI         regDP_DPHY_CRC_MST_CNTL__VI;
typedef union DP_DPHY_CRC_MST_STATUS__VI       regDP_DPHY_CRC_MST_STATUS__VI;
typedef union DP_DPHY_FAST_TRAINING_STATUS__VI regDP_DPHY_FAST_TRAINING_STATUS__VI;
typedef union DP_DPHY_SYM0__VI                 regDP_DPHY_SYM0__VI;
typedef union DP_DPHY_SYM1__VI                 regDP_DPHY_SYM1__VI;
typedef union DP_DPHY_SYM2__VI                 regDP_DPHY_SYM2__VI;
typedef union DP_FE_TEST_DEBUG_DATA__VI        regDP_FE_TEST_DEBUG_DATA__VI;
typedef union DP_FE_TEST_DEBUG_INDEX__VI       regDP_FE_TEST_DEBUG_INDEX__VI;
typedef union DP_HBR2_EYE_PATTERN__VI          regDP_HBR2_EYE_PATTERN__VI;
typedef union DP_LINK_FRAMING_CNTL__VI         regDP_LINK_FRAMING_CNTL__VI;
typedef union DP_MSA_COLORIMETRY__VI           regDP_MSA_COLORIMETRY__VI;
typedef union DP_MSA_MISC__VI                  regDP_MSA_MISC__VI;
typedef union DP_MSA_V_TIMING_OVERRIDE1__VI    regDP_MSA_V_TIMING_OVERRIDE1__VI;
typedef union DP_MSA_V_TIMING_OVERRIDE2__VI    regDP_MSA_V_TIMING_OVERRIDE2__VI;
typedef union DP_MSE_LINK_TIMING__VI           regDP_MSE_LINK_TIMING__VI;
typedef union DP_MSE_MISC_CNTL__VI             regDP_MSE_MISC_CNTL__VI;
typedef union DP_MSE_RATE_CNTL__VI             regDP_MSE_RATE_CNTL__VI;
typedef union DP_MSE_RATE_UPDATE__VI           regDP_MSE_RATE_UPDATE__VI;
typedef union DP_MSE_SAT0__VI                  regDP_MSE_SAT0__VI;
typedef union DP_MSE_SAT1__VI                  regDP_MSE_SAT1__VI;
typedef union DP_MSE_SAT2__VI                  regDP_MSE_SAT2__VI;
typedef union DP_MSE_SAT_UPDATE__VI            regDP_MSE_SAT_UPDATE__VI;
typedef union DP_SEC_CNTL1__VI                 regDP_SEC_CNTL1__VI;
typedef union DVO_CLK_ENABLE__VI               regDVO_CLK_ENABLE__VI;
typedef union DVO_FIFO_ERROR_STATUS__VI        regDVO_FIFO_ERROR_STATUS__VI;
typedef union DVO_SKEW_ADJUST__VI              regDVO_SKEW_ADJUST__VI;
typedef union DVO_TEST_DEBUG_DATA__VI          regDVO_TEST_DEBUG_DATA__VI;
typedef union DVO_TEST_DEBUG_INDEX__VI         regDVO_TEST_DEBUG_INDEX__VI;
typedef union DVO_VREF_CONTROL__VI             regDVO_VREF_CONTROL__VI;
typedef union ENTITY_TEMPERATURES_1__VI        regENTITY_TEMPERATURES_1__VI;
typedef union FBC_DEBUG_CSR_RDATA_HI__VI       regFBC_DEBUG_CSR_RDATA_HI__VI;
typedef union FBC_DEBUG_CSR_WDATA_HI__VI       regFBC_DEBUG_CSR_WDATA_HI__VI;
typedef union FBC_STATUS__VI                   regFBC_STATUS__VI;
typedef union FEATURE_STATUS__VI               regFEATURE_STATUS__VI;
typedef union FMT_CLAMP_COMPONENT_B__VI        regFMT_CLAMP_COMPONENT_B__VI;
typedef union FMT_CLAMP_COMPONENT_G__VI        regFMT_CLAMP_COMPONENT_G__VI;
typedef union FMT_CLAMP_COMPONENT_R__VI        regFMT_CLAMP_COMPONENT_R__VI;
typedef union FMT_DEBUG0__VI                   regFMT_DEBUG0__VI;
typedef union FMT_DEBUG1__VI                   regFMT_DEBUG1__VI;
typedef union FMT_DEBUG2__VI                   regFMT_DEBUG2__VI;
typedef union FMT_DEBUG_ID__VI                 regFMT_DEBUG_ID__VI;
typedef union FMT_TEST_DEBUG_DATA__VI          regFMT_TEST_DEBUG_DATA__VI;
typedef union FMT_TEST_DEBUG_INDEX__VI         regFMT_TEST_DEBUG_INDEX__VI;
typedef union GAMMA_CORR_CNTLA_END_CNTL1__VI   regGAMMA_CORR_CNTLA_END_CNTL1__VI;
typedef union GAMMA_CORR_CNTLA_END_CNTL2__VI   regGAMMA_CORR_CNTLA_END_CNTL2__VI;
typedef union GAMMA_CORR_CNTLA_REGION_0_1__VI  regGAMMA_CORR_CNTLA_REGION_0_1__VI;
typedef union GAMMA_CORR_CNTLA_REGION_10_11__VI regGAMMA_CORR_CNTLA_REGION_10_11__VI;
typedef union GAMMA_CORR_CNTLA_REGION_12_13__VI regGAMMA_CORR_CNTLA_REGION_12_13__VI;
typedef union GAMMA_CORR_CNTLA_REGION_14_15__VI regGAMMA_CORR_CNTLA_REGION_14_15__VI;
typedef union GAMMA_CORR_CNTLA_REGION_2_3__VI  regGAMMA_CORR_CNTLA_REGION_2_3__VI;
typedef union GAMMA_CORR_CNTLA_REGION_4_5__VI  regGAMMA_CORR_CNTLA_REGION_4_5__VI;
typedef union GAMMA_CORR_CNTLA_REGION_6_7__VI  regGAMMA_CORR_CNTLA_REGION_6_7__VI;
typedef union GAMMA_CORR_CNTLA_REGION_8_9__VI  regGAMMA_CORR_CNTLA_REGION_8_9__VI;
typedef union GAMMA_CORR_CNTLA_SLOPE_CNTL__VI  regGAMMA_CORR_CNTLA_SLOPE_CNTL__VI;
typedef union GAMMA_CORR_CNTLA_START_CNTL__VI  regGAMMA_CORR_CNTLA_START_CNTL__VI;
typedef union GAMMA_CORR_CNTLB_END_CNTL1__VI   regGAMMA_CORR_CNTLB_END_CNTL1__VI;
typedef union GAMMA_CORR_CNTLB_END_CNTL2__VI   regGAMMA_CORR_CNTLB_END_CNTL2__VI;
typedef union GAMMA_CORR_CNTLB_REGION_0_1__VI  regGAMMA_CORR_CNTLB_REGION_0_1__VI;
typedef union GAMMA_CORR_CNTLB_REGION_10_11__VI regGAMMA_CORR_CNTLB_REGION_10_11__VI;
typedef union GAMMA_CORR_CNTLB_REGION_12_13__VI regGAMMA_CORR_CNTLB_REGION_12_13__VI;
typedef union GAMMA_CORR_CNTLB_REGION_14_15__VI regGAMMA_CORR_CNTLB_REGION_14_15__VI;
typedef union GAMMA_CORR_CNTLB_REGION_2_3__VI  regGAMMA_CORR_CNTLB_REGION_2_3__VI;
typedef union GAMMA_CORR_CNTLB_REGION_4_5__VI  regGAMMA_CORR_CNTLB_REGION_4_5__VI;
typedef union GAMMA_CORR_CNTLB_REGION_6_7__VI  regGAMMA_CORR_CNTLB_REGION_6_7__VI;
typedef union GAMMA_CORR_CNTLB_REGION_8_9__VI  regGAMMA_CORR_CNTLB_REGION_8_9__VI;
typedef union GAMMA_CORR_CNTLB_SLOPE_CNTL__VI  regGAMMA_CORR_CNTLB_SLOPE_CNTL__VI;
typedef union GAMMA_CORR_CNTLB_START_CNTL__VI  regGAMMA_CORR_CNTLB_START_CNTL__VI;
typedef union GAMMA_CORR_CONTROL__VI           regGAMMA_CORR_CONTROL__VI;
typedef union GAMMA_CORR_LUT_DATA__VI          regGAMMA_CORR_LUT_DATA__VI;
typedef union GAMMA_CORR_LUT_INDEX__VI         regGAMMA_CORR_LUT_INDEX__VI;
typedef union GAMMA_CORR_LUT_WRITE_EN_MASK__VI regGAMMA_CORR_LUT_WRITE_EN_MASK__VI;
typedef union GAMUT_REMAP_C11_C12__VI          regGAMUT_REMAP_C11_C12__VI;
typedef union GAMUT_REMAP_C13_C14__VI          regGAMUT_REMAP_C13_C14__VI;
typedef union GAMUT_REMAP_C21_C22__VI          regGAMUT_REMAP_C21_C22__VI;
typedef union GAMUT_REMAP_C23_C24__VI          regGAMUT_REMAP_C23_C24__VI;
typedef union GAMUT_REMAP_C31_C32__VI          regGAMUT_REMAP_C31_C32__VI;
typedef union GAMUT_REMAP_C33_C34__VI          regGAMUT_REMAP_C33_C34__VI;
typedef union GAMUT_REMAP_CONTROL__VI          regGAMUT_REMAP_CONTROL__VI;
typedef union GARLIC_COHE_CP_DMA_ME_COMMAND__VI regGARLIC_COHE_CP_DMA_ME_COMMAND__VI;
typedef union GARLIC_COHE_CP_DMA_PFP_COMMAND__VI regGARLIC_COHE_CP_DMA_PFP_COMMAND__VI;
typedef union GARLIC_COHE_CP_DMA_PIO_COMMAND__VI regGARLIC_COHE_CP_DMA_PIO_COMMAND__VI;
typedef union GARLIC_COHE_CP_RB0_WPTR__VI      regGARLIC_COHE_CP_RB0_WPTR__VI;
typedef union GARLIC_COHE_CP_RB1_WPTR__VI      regGARLIC_COHE_CP_RB1_WPTR__VI;
typedef union GARLIC_COHE_CP_RB2_WPTR__VI      regGARLIC_COHE_CP_RB2_WPTR__VI;
typedef union GARLIC_COHE_GARLIC_FLUSH_REQ__VI regGARLIC_COHE_GARLIC_FLUSH_REQ__VI;
typedef union GARLIC_COHE_SAM_SAB_RBI_WPTR__VI regGARLIC_COHE_SAM_SAB_RBI_WPTR__VI;
typedef union GARLIC_COHE_SAM_SAB_RBO_WPTR__VI regGARLIC_COHE_SAM_SAB_RBO_WPTR__VI;
typedef union GARLIC_COHE_SDMA0_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA0_GFX_RB_WPTR__VI;
typedef union GARLIC_COHE_SDMA1_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA1_GFX_RB_WPTR__VI;
typedef union GARLIC_COHE_SDMA2_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA2_GFX_RB_WPTR__VI;
typedef union GARLIC_COHE_SDMA3_GFX_RB_WPTR__VI regGARLIC_COHE_SDMA3_GFX_RB_WPTR__VI;
typedef union GARLIC_COHE_UVD_RBC_RB_WPTR__VI  regGARLIC_COHE_UVD_RBC_RB_WPTR__VI;
typedef union GARLIC_COHE_VCE_OUT_RB_WPTR__VI  regGARLIC_COHE_VCE_OUT_RB_WPTR__VI;
typedef union GARLIC_COHE_VCE_RB_WPTR__VI      regGARLIC_COHE_VCE_RB_WPTR__VI;
typedef union GARLIC_COHE_VCE_RB_WPTR2__VI     regGARLIC_COHE_VCE_RB_WPTR2__VI;
typedef union GCK_ADFS_CLK_BYPASS_CNTL1__VI    regGCK_ADFS_CLK_BYPASS_CNTL1__VI;
typedef union GCK_DFS_BYPASS_CNTL__VI          regGCK_DFS_BYPASS_CNTL__VI;
typedef union GCK_MCLK_FUSES__VI               regGCK_MCLK_FUSES__VI;
typedef union GCK_PLL_TEST_CNTL_2__VI          regGCK_PLL_TEST_CNTL_2__VI;
typedef union GC_CAC_ACC_CU0__VI               regGC_CAC_ACC_CU0__VI;
typedef union GC_CAC_ACC_CU1__VI               regGC_CAC_ACC_CU1__VI;
typedef union GC_CAC_ACC_CU10__VI              regGC_CAC_ACC_CU10__VI;
typedef union GC_CAC_ACC_CU11__VI              regGC_CAC_ACC_CU11__VI;
typedef union GC_CAC_ACC_CU12__VI              regGC_CAC_ACC_CU12__VI;
typedef union GC_CAC_ACC_CU13__VI              regGC_CAC_ACC_CU13__VI;
typedef union GC_CAC_ACC_CU14__VI              regGC_CAC_ACC_CU14__VI;
typedef union GC_CAC_ACC_CU15__VI              regGC_CAC_ACC_CU15__VI;
typedef union GC_CAC_ACC_CU2__VI               regGC_CAC_ACC_CU2__VI;
typedef union GC_CAC_ACC_CU3__VI               regGC_CAC_ACC_CU3__VI;
typedef union GC_CAC_ACC_CU4__VI               regGC_CAC_ACC_CU4__VI;
typedef union GC_CAC_ACC_CU5__VI               regGC_CAC_ACC_CU5__VI;
typedef union GC_CAC_ACC_CU6__VI               regGC_CAC_ACC_CU6__VI;
typedef union GC_CAC_ACC_CU7__VI               regGC_CAC_ACC_CU7__VI;
typedef union GC_CAC_ACC_CU8__VI               regGC_CAC_ACC_CU8__VI;
typedef union GC_CAC_ACC_CU9__VI               regGC_CAC_ACC_CU9__VI;
typedef union GC_CAC_CGTT_CLK_CTRL__VI         regGC_CAC_CGTT_CLK_CTRL__VI;
typedef union GC_CAC_LKG_AGGR_LOWER__VI        regGC_CAC_LKG_AGGR_LOWER__VI;
typedef union GC_CAC_LKG_AGGR_UPPER__VI        regGC_CAC_LKG_AGGR_UPPER__VI;
typedef union GC_CAC_OVRD_CU__VI               regGC_CAC_OVRD_CU__VI;
typedef union GC_CAC_WEIGHT_CU_0__VI           regGC_CAC_WEIGHT_CU_0__VI;
typedef union GC_CAC_WEIGHT_CU_1__VI           regGC_CAC_WEIGHT_CU_1__VI;
typedef union GC_CAC_WEIGHT_CU_2__VI           regGC_CAC_WEIGHT_CU_2__VI;
typedef union GC_CAC_WEIGHT_CU_3__VI           regGC_CAC_WEIGHT_CU_3__VI;
typedef union GC_CAC_WEIGHT_CU_4__VI           regGC_CAC_WEIGHT_CU_4__VI;
typedef union GC_CAC_WEIGHT_CU_5__VI           regGC_CAC_WEIGHT_CU_5__VI;
typedef union GC_CAC_WEIGHT_CU_6__VI           regGC_CAC_WEIGHT_CU_6__VI;
typedef union GC_CAC_WEIGHT_CU_7__VI           regGC_CAC_WEIGHT_CU_7__VI;
typedef union GC_USER_SHADER_RATE_CONFIG__VI   regGC_USER_SHADER_RATE_CONFIG__VI;
typedef union GDS_CS_CTXSW_CNT0__VI            regGDS_CS_CTXSW_CNT0__VI;
typedef union GDS_CS_CTXSW_CNT1__VI            regGDS_CS_CTXSW_CNT1__VI;
typedef union GDS_CS_CTXSW_CNT2__VI            regGDS_CS_CTXSW_CNT2__VI;
typedef union GDS_CS_CTXSW_CNT3__VI            regGDS_CS_CTXSW_CNT3__VI;
typedef union GDS_CS_CTXSW_STATUS__VI          regGDS_CS_CTXSW_STATUS__VI;
typedef union GDS_DSM_CNTL__VI                 regGDS_DSM_CNTL__VI;
typedef union GDS_EDC_CNT__VI                  regGDS_EDC_CNT__VI;
typedef union GDS_EDC_GRBM_CNT__VI             regGDS_EDC_GRBM_CNT__VI;
typedef union GDS_EDC_OA_DED__VI               regGDS_EDC_OA_DED__VI;
typedef union GDS_GFX_CTXSW_STATUS__VI         regGDS_GFX_CTXSW_STATUS__VI;
typedef union GDS_PS0_CTXSW_CNT0__VI           regGDS_PS0_CTXSW_CNT0__VI;
typedef union GDS_PS0_CTXSW_CNT1__VI           regGDS_PS0_CTXSW_CNT1__VI;
typedef union GDS_PS0_CTXSW_CNT2__VI           regGDS_PS0_CTXSW_CNT2__VI;
typedef union GDS_PS0_CTXSW_CNT3__VI           regGDS_PS0_CTXSW_CNT3__VI;
typedef union GDS_PS1_CTXSW_CNT0__VI           regGDS_PS1_CTXSW_CNT0__VI;
typedef union GDS_PS1_CTXSW_CNT1__VI           regGDS_PS1_CTXSW_CNT1__VI;
typedef union GDS_PS1_CTXSW_CNT2__VI           regGDS_PS1_CTXSW_CNT2__VI;
typedef union GDS_PS1_CTXSW_CNT3__VI           regGDS_PS1_CTXSW_CNT3__VI;
typedef union GDS_PS2_CTXSW_CNT0__VI           regGDS_PS2_CTXSW_CNT0__VI;
typedef union GDS_PS2_CTXSW_CNT1__VI           regGDS_PS2_CTXSW_CNT1__VI;
typedef union GDS_PS2_CTXSW_CNT2__VI           regGDS_PS2_CTXSW_CNT2__VI;
typedef union GDS_PS2_CTXSW_CNT3__VI           regGDS_PS2_CTXSW_CNT3__VI;
typedef union GDS_PS3_CTXSW_CNT0__VI           regGDS_PS3_CTXSW_CNT0__VI;
typedef union GDS_PS3_CTXSW_CNT1__VI           regGDS_PS3_CTXSW_CNT1__VI;
typedef union GDS_PS3_CTXSW_CNT2__VI           regGDS_PS3_CTXSW_CNT2__VI;
typedef union GDS_PS3_CTXSW_CNT3__VI           regGDS_PS3_CTXSW_CNT3__VI;
typedef union GDS_PS4_CTXSW_CNT0__VI           regGDS_PS4_CTXSW_CNT0__VI;
typedef union GDS_PS4_CTXSW_CNT1__VI           regGDS_PS4_CTXSW_CNT1__VI;
typedef union GDS_PS4_CTXSW_CNT2__VI           regGDS_PS4_CTXSW_CNT2__VI;
typedef union GDS_PS4_CTXSW_CNT3__VI           regGDS_PS4_CTXSW_CNT3__VI;
typedef union GDS_PS5_CTXSW_CNT0__VI           regGDS_PS5_CTXSW_CNT0__VI;
typedef union GDS_PS5_CTXSW_CNT1__VI           regGDS_PS5_CTXSW_CNT1__VI;
typedef union GDS_PS5_CTXSW_CNT2__VI           regGDS_PS5_CTXSW_CNT2__VI;
typedef union GDS_PS5_CTXSW_CNT3__VI           regGDS_PS5_CTXSW_CNT3__VI;
typedef union GDS_PS6_CTXSW_CNT0__VI           regGDS_PS6_CTXSW_CNT0__VI;
typedef union GDS_PS6_CTXSW_CNT1__VI           regGDS_PS6_CTXSW_CNT1__VI;
typedef union GDS_PS6_CTXSW_CNT2__VI           regGDS_PS6_CTXSW_CNT2__VI;
typedef union GDS_PS6_CTXSW_CNT3__VI           regGDS_PS6_CTXSW_CNT3__VI;
typedef union GDS_PS7_CTXSW_CNT0__VI           regGDS_PS7_CTXSW_CNT0__VI;
typedef union GDS_PS7_CTXSW_CNT1__VI           regGDS_PS7_CTXSW_CNT1__VI;
typedef union GDS_PS7_CTXSW_CNT2__VI           regGDS_PS7_CTXSW_CNT2__VI;
typedef union GDS_PS7_CTXSW_CNT3__VI           regGDS_PS7_CTXSW_CNT3__VI;
typedef union GDS_VS_CTXSW_CNT0__VI            regGDS_VS_CTXSW_CNT0__VI;
typedef union GDS_VS_CTXSW_CNT1__VI            regGDS_VS_CTXSW_CNT1__VI;
typedef union GDS_VS_CTXSW_CNT2__VI            regGDS_VS_CTXSW_CNT2__VI;
typedef union GDS_VS_CTXSW_CNT3__VI            regGDS_VS_CTXSW_CNT3__VI;
typedef union GMCON_LPT_TARGET__VI             regGMCON_LPT_TARGET__VI;
typedef union GPU_BIST_CONTROL__VI             regGPU_BIST_CONTROL__VI;
typedef union GRBM_DSM_BYPASS__VI              regGRBM_DSM_BYPASS__VI;
typedef union GRBM_HYP_CAM_DATA__VI            regGRBM_HYP_CAM_DATA__VI;
typedef union GRBM_HYP_CAM_INDEX__VI           regGRBM_HYP_CAM_INDEX__VI;
typedef union GRBM_TRAP_ADDR__VI               regGRBM_TRAP_ADDR__VI;
typedef union GRBM_TRAP_ADDR_MSK__VI           regGRBM_TRAP_ADDR_MSK__VI;
typedef union GRBM_TRAP_OP__VI                 regGRBM_TRAP_OP__VI;
typedef union GRBM_TRAP_WD__VI                 regGRBM_TRAP_WD__VI;
typedef union GRBM_TRAP_WD_MSK__VI             regGRBM_TRAP_WD_MSK__VI;
typedef union GRBM_WRITE_ERROR__VI             regGRBM_WRITE_ERROR__VI;
typedef union GRPH_FLIP_RATE_CNTL__VI          regGRPH_FLIP_RATE_CNTL__VI;
typedef union GRPH_STEREOSYNC_FLIP__VI         regGRPH_STEREOSYNC_FLIP__VI;
typedef union GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI regGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__VI;
typedef union GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI regGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__VI;
typedef union GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI regGRPH_XDMA_RECOVERY_SURFACE_ADDRESS__VI;
typedef union GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI regGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__VI;
typedef union GSKT_CONTROL__VI                 regGSKT_CONTROL__VI;
typedef union HDMI_GENERIC_PACKET_CONTROL0__VI regHDMI_GENERIC_PACKET_CONTROL0__VI;
typedef union HDMI_GENERIC_PACKET_CONTROL1__VI regHDMI_GENERIC_PACKET_CONTROL1__VI;
typedef union HDP_ADDR_CONFIG__VI              regHDP_ADDR_CONFIG__VI;
typedef union HDP_MEMIO_ADDR__VI               regHDP_MEMIO_ADDR__VI;
typedef union HDP_MEMIO_CNTL__VI               regHDP_MEMIO_CNTL__VI;
typedef union HDP_MEMIO_RD_DATA__VI            regHDP_MEMIO_RD_DATA__VI;
typedef union HDP_MEMIO_STATUS__VI             regHDP_MEMIO_STATUS__VI;
typedef union HDP_MEMIO_WR_DATA__VI            regHDP_MEMIO_WR_DATA__VI;
typedef union HDP_MEM_POWER_LS__VI             regHDP_MEM_POWER_LS__VI;
typedef union HDP_MISC_CNTL__VI                regHDP_MISC_CNTL__VI;
typedef union HDP_NONSURFACE_PREFETCH__VI      regHDP_NONSURFACE_PREFETCH__VI;
typedef union HDP_VF_ENABLE__VI                regHDP_VF_ENABLE__VI;
typedef union HDP_XDP_BARS_ADDR_39_36__VI      regHDP_XDP_BARS_ADDR_39_36__VI;
typedef union HW_ROTATION__VI                  regHW_ROTATION__VI;
typedef union IH_ACTIVE_FCN_ID__VI             regIH_ACTIVE_FCN_ID__VI;
typedef union IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VI regIH_CLIENT_MAY_SEND_INCOMPLETE_INT__VI;
typedef union IH_DEBUG__VI                     regIH_DEBUG__VI;
typedef union IH_DOORBELL_RPTR__VI             regIH_DOORBELL_RPTR__VI;
typedef union IH_DSM_MATCH_DATA_CONTROL__VI    regIH_DSM_MATCH_DATA_CONTROL__VI;
typedef union IH_DSM_MATCH_FIELD_CONTROL__VI   regIH_DSM_MATCH_FIELD_CONTROL__VI;
typedef union IH_DSM_MATCH_VALUE_BIT_31_0__VI  regIH_DSM_MATCH_VALUE_BIT_31_0__VI;
typedef union IH_DSM_MATCH_VALUE_BIT_63_32__VI regIH_DSM_MATCH_VALUE_BIT_63_32__VI;
typedef union IH_DSM_MATCH_VALUE_BIT_95_64__VI regIH_DSM_MATCH_VALUE_BIT_95_64__VI;
typedef union IH_LEVEL_INTR_MASK__VI           regIH_LEVEL_INTR_MASK__VI;
typedef union IH_RESET_INCOMPLETE_INT_CNTL__VI regIH_RESET_INCOMPLETE_INT_CNTL__VI;
typedef union IH_VERSION__VI                   regIH_VERSION__VI;
typedef union IH_VF_ENABLE__VI                 regIH_VF_ENABLE__VI;
typedef union IH_VF_RB_BIF_STATUS__VI          regIH_VF_RB_BIF_STATUS__VI;
typedef union IH_VF_RB_STATUS__VI              regIH_VF_RB_STATUS__VI;
typedef union IH_VIRT_RESET_REQ__VI            regIH_VIRT_RESET_REQ__VI;
typedef union INPUT_CSC_C11_C12__VI            regINPUT_CSC_C11_C12__VI;
typedef union INPUT_CSC_C11_C12_A__VI          regINPUT_CSC_C11_C12_A__VI;
typedef union INPUT_CSC_C11_C12_B__VI          regINPUT_CSC_C11_C12_B__VI;
typedef union INPUT_CSC_C13_C14__VI            regINPUT_CSC_C13_C14__VI;
typedef union INPUT_CSC_C13_C14_A__VI          regINPUT_CSC_C13_C14_A__VI;
typedef union INPUT_CSC_C13_C14_B__VI          regINPUT_CSC_C13_C14_B__VI;
typedef union INPUT_CSC_C21_C22__VI            regINPUT_CSC_C21_C22__VI;
typedef union INPUT_CSC_C21_C22_A__VI          regINPUT_CSC_C21_C22_A__VI;
typedef union INPUT_CSC_C21_C22_B__VI          regINPUT_CSC_C21_C22_B__VI;
typedef union INPUT_CSC_C23_C24__VI            regINPUT_CSC_C23_C24__VI;
typedef union INPUT_CSC_C23_C24_A__VI          regINPUT_CSC_C23_C24_A__VI;
typedef union INPUT_CSC_C23_C24_B__VI          regINPUT_CSC_C23_C24_B__VI;
typedef union INPUT_CSC_C31_C32__VI            regINPUT_CSC_C31_C32__VI;
typedef union INPUT_CSC_C31_C32_A__VI          regINPUT_CSC_C31_C32_A__VI;
typedef union INPUT_CSC_C31_C32_B__VI          regINPUT_CSC_C31_C32_B__VI;
typedef union INPUT_CSC_C33_C34__VI            regINPUT_CSC_C33_C34__VI;
typedef union INPUT_CSC_C33_C34_A__VI          regINPUT_CSC_C33_C34_A__VI;
typedef union INPUT_CSC_C33_C34_B__VI          regINPUT_CSC_C33_C34_B__VI;
typedef union INPUT_CSC_CONTROL__VI            regINPUT_CSC_CONTROL__VI;
typedef union INPUT_GAMMA_CONTROL__VI          regINPUT_GAMMA_CONTROL__VI;
typedef union INPUT_STREAM_PAYLOAD_CAPABILITY__VI regINPUT_STREAM_PAYLOAD_CAPABILITY__VI;
typedef union KEY_CONTROL__VI                  regKEY_CONTROL__VI;
typedef union KEY_RANGE_ALPHA__VI              regKEY_RANGE_ALPHA__VI;
typedef union KEY_RANGE_BLUE__VI               regKEY_RANGE_BLUE__VI;
typedef union KEY_RANGE_GREEN__VI              regKEY_RANGE_GREEN__VI;
typedef union KEY_RANGE_RED__VI                regKEY_RANGE_RED__VI;
typedef union LBV_BLACK_KEYER_B_CB__VI         regLBV_BLACK_KEYER_B_CB__VI;
typedef union LBV_BLACK_KEYER_G_Y__VI          regLBV_BLACK_KEYER_G_Y__VI;
typedef union LBV_BLACK_KEYER_R_CR__VI         regLBV_BLACK_KEYER_R_CR__VI;
typedef union LBV_BUFFER_LEVEL_STATUS__VI      regLBV_BUFFER_LEVEL_STATUS__VI;
typedef union LBV_BUFFER_STATUS__VI            regLBV_BUFFER_STATUS__VI;
typedef union LBV_BUFFER_URGENCY_CTRL__VI      regLBV_BUFFER_URGENCY_CTRL__VI;
typedef union LBV_BUFFER_URGENCY_STATUS__VI    regLBV_BUFFER_URGENCY_STATUS__VI;
typedef union LBV_DATA_FORMAT__VI              regLBV_DATA_FORMAT__VI;
typedef union LBV_DEBUG__VI                    regLBV_DEBUG__VI;
typedef union LBV_DEBUG2__VI                   regLBV_DEBUG2__VI;
typedef union LBV_DEBUG3__VI                   regLBV_DEBUG3__VI;
typedef union LBV_DESKTOP_HEIGHT__VI           regLBV_DESKTOP_HEIGHT__VI;
typedef union LBV_INTERRUPT_MASK__VI           regLBV_INTERRUPT_MASK__VI;
typedef union LBV_KEYER_COLOR_B_CB__VI         regLBV_KEYER_COLOR_B_CB__VI;
typedef union LBV_KEYER_COLOR_CTRL__VI         regLBV_KEYER_COLOR_CTRL__VI;
typedef union LBV_KEYER_COLOR_G_Y__VI          regLBV_KEYER_COLOR_G_Y__VI;
typedef union LBV_KEYER_COLOR_REP_B_CB__VI     regLBV_KEYER_COLOR_REP_B_CB__VI;
typedef union LBV_KEYER_COLOR_REP_G_Y__VI      regLBV_KEYER_COLOR_REP_G_Y__VI;
typedef union LBV_KEYER_COLOR_REP_R_CR__VI     regLBV_KEYER_COLOR_REP_R_CR__VI;
typedef union LBV_KEYER_COLOR_R_CR__VI         regLBV_KEYER_COLOR_R_CR__VI;
typedef union LBV_MEMORY_CTRL__VI              regLBV_MEMORY_CTRL__VI;
typedef union LBV_MEMORY_SIZE_STATUS__VI       regLBV_MEMORY_SIZE_STATUS__VI;
typedef union LBV_NO_OUTSTANDING_REQ_STATUS__VI regLBV_NO_OUTSTANDING_REQ_STATUS__VI;
typedef union LBV_SNAPSHOT_V_COUNTER__VI       regLBV_SNAPSHOT_V_COUNTER__VI;
typedef union LBV_SNAPSHOT_V_COUNTER_CHROMA__VI regLBV_SNAPSHOT_V_COUNTER_CHROMA__VI;
typedef union LBV_SYNC_RESET_SEL__VI           regLBV_SYNC_RESET_SEL__VI;
typedef union LBV_TEST_DEBUG_DATA__VI          regLBV_TEST_DEBUG_DATA__VI;
typedef union LBV_TEST_DEBUG_INDEX__VI         regLBV_TEST_DEBUG_INDEX__VI;
typedef union LBV_VBLANK_STATUS__VI            regLBV_VBLANK_STATUS__VI;
typedef union LBV_VLINE2_START_END__VI         regLBV_VLINE2_START_END__VI;
typedef union LBV_VLINE2_STATUS__VI            regLBV_VLINE2_STATUS__VI;
typedef union LBV_VLINE_START_END__VI          regLBV_VLINE_START_END__VI;
typedef union LBV_VLINE_STATUS__VI             regLBV_VLINE_STATUS__VI;
typedef union LBV_V_COUNTER__VI                regLBV_V_COUNTER__VI;
typedef union LBV_V_COUNTER_CHROMA__VI         regLBV_V_COUNTER_CHROMA__VI;
typedef union LB_BLACK_KEYER_B_CB__VI          regLB_BLACK_KEYER_B_CB__VI;
typedef union LB_BLACK_KEYER_G_Y__VI           regLB_BLACK_KEYER_G_Y__VI;
typedef union LB_BLACK_KEYER_R_CR__VI          regLB_BLACK_KEYER_R_CR__VI;
typedef union LB_BUFFER_LEVEL_STATUS__VI       regLB_BUFFER_LEVEL_STATUS__VI;
typedef union LB_BUFFER_STATUS__VI             regLB_BUFFER_STATUS__VI;
typedef union LB_BUFFER_URGENCY_CTRL__VI       regLB_BUFFER_URGENCY_CTRL__VI;
typedef union LB_BUFFER_URGENCY_STATUS__VI     regLB_BUFFER_URGENCY_STATUS__VI;
typedef union LB_DATA_FORMAT__VI               regLB_DATA_FORMAT__VI;
typedef union LB_DEBUG2__VI                    regLB_DEBUG2__VI;
typedef union LB_DEBUG3__VI                    regLB_DEBUG3__VI;
typedef union LB_DESKTOP_HEIGHT__VI            regLB_DESKTOP_HEIGHT__VI;
typedef union LB_INTERRUPT_MASK__VI            regLB_INTERRUPT_MASK__VI;
typedef union LB_KEYER_COLOR_B_CB__VI          regLB_KEYER_COLOR_B_CB__VI;
typedef union LB_KEYER_COLOR_CTRL__VI          regLB_KEYER_COLOR_CTRL__VI;
typedef union LB_KEYER_COLOR_G_Y__VI           regLB_KEYER_COLOR_G_Y__VI;
typedef union LB_KEYER_COLOR_REP_B_CB__VI      regLB_KEYER_COLOR_REP_B_CB__VI;
typedef union LB_KEYER_COLOR_REP_G_Y__VI       regLB_KEYER_COLOR_REP_G_Y__VI;
typedef union LB_KEYER_COLOR_REP_R_CR__VI      regLB_KEYER_COLOR_REP_R_CR__VI;
typedef union LB_KEYER_COLOR_R_CR__VI          regLB_KEYER_COLOR_R_CR__VI;
typedef union LB_MEMORY_CTRL__VI               regLB_MEMORY_CTRL__VI;
typedef union LB_MEMORY_SIZE_STATUS__VI        regLB_MEMORY_SIZE_STATUS__VI;
typedef union LB_NO_OUTSTANDING_REQ_STATUS__VI regLB_NO_OUTSTANDING_REQ_STATUS__VI;
typedef union LB_SNAPSHOT_V_COUNTER__VI        regLB_SNAPSHOT_V_COUNTER__VI;
typedef union LB_VBLANK_STATUS__VI             regLB_VBLANK_STATUS__VI;
typedef union LB_VLINE2_START_END__VI          regLB_VLINE2_START_END__VI;
typedef union LB_VLINE2_STATUS__VI             regLB_VLINE2_STATUS__VI;
typedef union LB_VLINE_START_END__VI           regLB_VLINE_START_END__VI;
typedef union LB_VLINE_STATUS__VI              regLB_VLINE_STATUS__VI;
typedef union LB_V_COUNTER__VI                 regLB_V_COUNTER__VI;
typedef union LCAC_MC6_CNTL__VI                regLCAC_MC6_CNTL__VI;
typedef union LCAC_MC6_OVR_SEL__VI             regLCAC_MC6_OVR_SEL__VI;
typedef union LCAC_MC6_OVR_VAL__VI             regLCAC_MC6_OVR_VAL__VI;
typedef union LCAC_MC7_CNTL__VI                regLCAC_MC7_CNTL__VI;
typedef union LCAC_MC7_OVR_SEL__VI             regLCAC_MC7_OVR_SEL__VI;
typedef union LCAC_MC7_OVR_VAL__VI             regLCAC_MC7_OVR_VAL__VI;
typedef union LM_CONTROL__VI                   regLM_CONTROL__VI;
typedef union LM_LANEENABLE__VI                regLM_LANEENABLE__VI;
typedef union LM_PCIERXMUX0__VI                regLM_PCIERXMUX0__VI;
typedef union LM_PCIERXMUX1__VI                regLM_PCIERXMUX1__VI;
typedef union LM_PCIERXMUX2__VI                regLM_PCIERXMUX2__VI;
typedef union LM_PCIERXMUX3__VI                regLM_PCIERXMUX3__VI;
typedef union LM_PCIETXMUX0__VI                regLM_PCIETXMUX0__VI;
typedef union LM_PCIETXMUX1__VI                regLM_PCIETXMUX1__VI;
typedef union LM_PCIETXMUX2__VI                regLM_PCIETXMUX2__VI;
typedef union LM_PCIETXMUX3__VI                regLM_PCIETXMUX3__VI;
typedef union LM_POWERCONTROL__VI              regLM_POWERCONTROL__VI;
typedef union LM_POWERCONTROL1__VI             regLM_POWERCONTROL1__VI;
typedef union LM_POWERCONTROL2__VI             regLM_POWERCONTROL2__VI;
typedef union LM_POWERCONTROL3__VI             regLM_POWERCONTROL3__VI;
typedef union LM_POWERCONTROL4__VI             regLM_POWERCONTROL4__VI;
typedef union LM_PRBSCONTROL__VI               regLM_PRBSCONTROL__VI;
typedef union LNCNT_QUAN_THRD__VI              regLNCNT_QUAN_THRD__VI;
typedef union LNCNT_WEIGHT__VI                 regLNCNT_WEIGHT__VI;
typedef union LNC_BW_WACC__VI                  regLNC_BW_WACC__VI;
typedef union LNC_CMN_WACC__VI                 regLNC_CMN_WACC__VI;
typedef union LNC_TOTAL_WACC__VI               regLNC_TOTAL_WACC__VI;
typedef union LOW_POWER_TILING_CONTROL__VI     regLOW_POWER_TILING_CONTROL__VI;
typedef union MAILBOX_CONTROL__VI              regMAILBOX_CONTROL__VI;
typedef union MAILBOX_INDEX__VI                regMAILBOX_INDEX__VI;
typedef union MAILBOX_INT_CNTL__VI             regMAILBOX_INT_CNTL__VI;
typedef union MAILBOX_MSGBUF_RCV_DW0__VI       regMAILBOX_MSGBUF_RCV_DW0__VI;
typedef union MAILBOX_MSGBUF_RCV_DW1__VI       regMAILBOX_MSGBUF_RCV_DW1__VI;
typedef union MAILBOX_MSGBUF_RCV_DW2__VI       regMAILBOX_MSGBUF_RCV_DW2__VI;
typedef union MAILBOX_MSGBUF_RCV_DW3__VI       regMAILBOX_MSGBUF_RCV_DW3__VI;
typedef union MAILBOX_MSGBUF_TRN_DW0__VI       regMAILBOX_MSGBUF_TRN_DW0__VI;
typedef union MAILBOX_MSGBUF_TRN_DW1__VI       regMAILBOX_MSGBUF_TRN_DW1__VI;
typedef union MAILBOX_MSGBUF_TRN_DW2__VI       regMAILBOX_MSGBUF_TRN_DW2__VI;
typedef union MAILBOX_MSGBUF_TRN_DW3__VI       regMAILBOX_MSGBUF_TRN_DW3__VI;
typedef union MCARB_DRAM_TIMING_TABLE_1__VI    regMCARB_DRAM_TIMING_TABLE_1__VI;
typedef union MCARB_DRAM_TIMING_TABLE_10__VI   regMCARB_DRAM_TIMING_TABLE_10__VI;
typedef union MCARB_DRAM_TIMING_TABLE_11__VI   regMCARB_DRAM_TIMING_TABLE_11__VI;
typedef union MCARB_DRAM_TIMING_TABLE_12__VI   regMCARB_DRAM_TIMING_TABLE_12__VI;
typedef union MCARB_DRAM_TIMING_TABLE_13__VI   regMCARB_DRAM_TIMING_TABLE_13__VI;
typedef union MCARB_DRAM_TIMING_TABLE_14__VI   regMCARB_DRAM_TIMING_TABLE_14__VI;
typedef union MCARB_DRAM_TIMING_TABLE_15__VI   regMCARB_DRAM_TIMING_TABLE_15__VI;
typedef union MCARB_DRAM_TIMING_TABLE_16__VI   regMCARB_DRAM_TIMING_TABLE_16__VI;
typedef union MCARB_DRAM_TIMING_TABLE_17__VI   regMCARB_DRAM_TIMING_TABLE_17__VI;
typedef union MCARB_DRAM_TIMING_TABLE_18__VI   regMCARB_DRAM_TIMING_TABLE_18__VI;
typedef union MCARB_DRAM_TIMING_TABLE_19__VI   regMCARB_DRAM_TIMING_TABLE_19__VI;
typedef union MCARB_DRAM_TIMING_TABLE_2__VI    regMCARB_DRAM_TIMING_TABLE_2__VI;
typedef union MCARB_DRAM_TIMING_TABLE_20__VI   regMCARB_DRAM_TIMING_TABLE_20__VI;
typedef union MCARB_DRAM_TIMING_TABLE_21__VI   regMCARB_DRAM_TIMING_TABLE_21__VI;
typedef union MCARB_DRAM_TIMING_TABLE_22__VI   regMCARB_DRAM_TIMING_TABLE_22__VI;
typedef union MCARB_DRAM_TIMING_TABLE_23__VI   regMCARB_DRAM_TIMING_TABLE_23__VI;
typedef union MCARB_DRAM_TIMING_TABLE_24__VI   regMCARB_DRAM_TIMING_TABLE_24__VI;
typedef union MCARB_DRAM_TIMING_TABLE_25__VI   regMCARB_DRAM_TIMING_TABLE_25__VI;
typedef union MCARB_DRAM_TIMING_TABLE_26__VI   regMCARB_DRAM_TIMING_TABLE_26__VI;
typedef union MCARB_DRAM_TIMING_TABLE_27__VI   regMCARB_DRAM_TIMING_TABLE_27__VI;
typedef union MCARB_DRAM_TIMING_TABLE_28__VI   regMCARB_DRAM_TIMING_TABLE_28__VI;
typedef union MCARB_DRAM_TIMING_TABLE_29__VI   regMCARB_DRAM_TIMING_TABLE_29__VI;
typedef union MCARB_DRAM_TIMING_TABLE_3__VI    regMCARB_DRAM_TIMING_TABLE_3__VI;
typedef union MCARB_DRAM_TIMING_TABLE_30__VI   regMCARB_DRAM_TIMING_TABLE_30__VI;
typedef union MCARB_DRAM_TIMING_TABLE_31__VI   regMCARB_DRAM_TIMING_TABLE_31__VI;
typedef union MCARB_DRAM_TIMING_TABLE_32__VI   regMCARB_DRAM_TIMING_TABLE_32__VI;
typedef union MCARB_DRAM_TIMING_TABLE_33__VI   regMCARB_DRAM_TIMING_TABLE_33__VI;
typedef union MCARB_DRAM_TIMING_TABLE_34__VI   regMCARB_DRAM_TIMING_TABLE_34__VI;
typedef union MCARB_DRAM_TIMING_TABLE_35__VI   regMCARB_DRAM_TIMING_TABLE_35__VI;
typedef union MCARB_DRAM_TIMING_TABLE_36__VI   regMCARB_DRAM_TIMING_TABLE_36__VI;
typedef union MCARB_DRAM_TIMING_TABLE_37__VI   regMCARB_DRAM_TIMING_TABLE_37__VI;
typedef union MCARB_DRAM_TIMING_TABLE_38__VI   regMCARB_DRAM_TIMING_TABLE_38__VI;
typedef union MCARB_DRAM_TIMING_TABLE_39__VI   regMCARB_DRAM_TIMING_TABLE_39__VI;
typedef union MCARB_DRAM_TIMING_TABLE_4__VI    regMCARB_DRAM_TIMING_TABLE_4__VI;
typedef union MCARB_DRAM_TIMING_TABLE_40__VI   regMCARB_DRAM_TIMING_TABLE_40__VI;
typedef union MCARB_DRAM_TIMING_TABLE_41__VI   regMCARB_DRAM_TIMING_TABLE_41__VI;
typedef union MCARB_DRAM_TIMING_TABLE_42__VI   regMCARB_DRAM_TIMING_TABLE_42__VI;
typedef union MCARB_DRAM_TIMING_TABLE_43__VI   regMCARB_DRAM_TIMING_TABLE_43__VI;
typedef union MCARB_DRAM_TIMING_TABLE_44__VI   regMCARB_DRAM_TIMING_TABLE_44__VI;
typedef union MCARB_DRAM_TIMING_TABLE_45__VI   regMCARB_DRAM_TIMING_TABLE_45__VI;
typedef union MCARB_DRAM_TIMING_TABLE_46__VI   regMCARB_DRAM_TIMING_TABLE_46__VI;
typedef union MCARB_DRAM_TIMING_TABLE_47__VI   regMCARB_DRAM_TIMING_TABLE_47__VI;
typedef union MCARB_DRAM_TIMING_TABLE_48__VI   regMCARB_DRAM_TIMING_TABLE_48__VI;
typedef union MCARB_DRAM_TIMING_TABLE_49__VI   regMCARB_DRAM_TIMING_TABLE_49__VI;
typedef union MCARB_DRAM_TIMING_TABLE_5__VI    regMCARB_DRAM_TIMING_TABLE_5__VI;
typedef union MCARB_DRAM_TIMING_TABLE_50__VI   regMCARB_DRAM_TIMING_TABLE_50__VI;
typedef union MCARB_DRAM_TIMING_TABLE_51__VI   regMCARB_DRAM_TIMING_TABLE_51__VI;
typedef union MCARB_DRAM_TIMING_TABLE_52__VI   regMCARB_DRAM_TIMING_TABLE_52__VI;
typedef union MCARB_DRAM_TIMING_TABLE_53__VI   regMCARB_DRAM_TIMING_TABLE_53__VI;
typedef union MCARB_DRAM_TIMING_TABLE_54__VI   regMCARB_DRAM_TIMING_TABLE_54__VI;
typedef union MCARB_DRAM_TIMING_TABLE_55__VI   regMCARB_DRAM_TIMING_TABLE_55__VI;
typedef union MCARB_DRAM_TIMING_TABLE_56__VI   regMCARB_DRAM_TIMING_TABLE_56__VI;
typedef union MCARB_DRAM_TIMING_TABLE_57__VI   regMCARB_DRAM_TIMING_TABLE_57__VI;
typedef union MCARB_DRAM_TIMING_TABLE_58__VI   regMCARB_DRAM_TIMING_TABLE_58__VI;
typedef union MCARB_DRAM_TIMING_TABLE_59__VI   regMCARB_DRAM_TIMING_TABLE_59__VI;
typedef union MCARB_DRAM_TIMING_TABLE_6__VI    regMCARB_DRAM_TIMING_TABLE_6__VI;
typedef union MCARB_DRAM_TIMING_TABLE_60__VI   regMCARB_DRAM_TIMING_TABLE_60__VI;
typedef union MCARB_DRAM_TIMING_TABLE_61__VI   regMCARB_DRAM_TIMING_TABLE_61__VI;
typedef union MCARB_DRAM_TIMING_TABLE_62__VI   regMCARB_DRAM_TIMING_TABLE_62__VI;
typedef union MCARB_DRAM_TIMING_TABLE_63__VI   regMCARB_DRAM_TIMING_TABLE_63__VI;
typedef union MCARB_DRAM_TIMING_TABLE_64__VI   regMCARB_DRAM_TIMING_TABLE_64__VI;
typedef union MCARB_DRAM_TIMING_TABLE_65__VI   regMCARB_DRAM_TIMING_TABLE_65__VI;
typedef union MCARB_DRAM_TIMING_TABLE_66__VI   regMCARB_DRAM_TIMING_TABLE_66__VI;
typedef union MCARB_DRAM_TIMING_TABLE_67__VI   regMCARB_DRAM_TIMING_TABLE_67__VI;
typedef union MCARB_DRAM_TIMING_TABLE_68__VI   regMCARB_DRAM_TIMING_TABLE_68__VI;
typedef union MCARB_DRAM_TIMING_TABLE_69__VI   regMCARB_DRAM_TIMING_TABLE_69__VI;
typedef union MCARB_DRAM_TIMING_TABLE_7__VI    regMCARB_DRAM_TIMING_TABLE_7__VI;
typedef union MCARB_DRAM_TIMING_TABLE_70__VI   regMCARB_DRAM_TIMING_TABLE_70__VI;
typedef union MCARB_DRAM_TIMING_TABLE_71__VI   regMCARB_DRAM_TIMING_TABLE_71__VI;
typedef union MCARB_DRAM_TIMING_TABLE_72__VI   regMCARB_DRAM_TIMING_TABLE_72__VI;
typedef union MCARB_DRAM_TIMING_TABLE_73__VI   regMCARB_DRAM_TIMING_TABLE_73__VI;
typedef union MCARB_DRAM_TIMING_TABLE_74__VI   regMCARB_DRAM_TIMING_TABLE_74__VI;
typedef union MCARB_DRAM_TIMING_TABLE_75__VI   regMCARB_DRAM_TIMING_TABLE_75__VI;
typedef union MCARB_DRAM_TIMING_TABLE_76__VI   regMCARB_DRAM_TIMING_TABLE_76__VI;
typedef union MCARB_DRAM_TIMING_TABLE_77__VI   regMCARB_DRAM_TIMING_TABLE_77__VI;
typedef union MCARB_DRAM_TIMING_TABLE_78__VI   regMCARB_DRAM_TIMING_TABLE_78__VI;
typedef union MCARB_DRAM_TIMING_TABLE_79__VI   regMCARB_DRAM_TIMING_TABLE_79__VI;
typedef union MCARB_DRAM_TIMING_TABLE_8__VI    regMCARB_DRAM_TIMING_TABLE_8__VI;
typedef union MCARB_DRAM_TIMING_TABLE_80__VI   regMCARB_DRAM_TIMING_TABLE_80__VI;
typedef union MCARB_DRAM_TIMING_TABLE_81__VI   regMCARB_DRAM_TIMING_TABLE_81__VI;
typedef union MCARB_DRAM_TIMING_TABLE_82__VI   regMCARB_DRAM_TIMING_TABLE_82__VI;
typedef union MCARB_DRAM_TIMING_TABLE_83__VI   regMCARB_DRAM_TIMING_TABLE_83__VI;
typedef union MCARB_DRAM_TIMING_TABLE_84__VI   regMCARB_DRAM_TIMING_TABLE_84__VI;
typedef union MCARB_DRAM_TIMING_TABLE_85__VI   regMCARB_DRAM_TIMING_TABLE_85__VI;
typedef union MCARB_DRAM_TIMING_TABLE_86__VI   regMCARB_DRAM_TIMING_TABLE_86__VI;
typedef union MCARB_DRAM_TIMING_TABLE_87__VI   regMCARB_DRAM_TIMING_TABLE_87__VI;
typedef union MCARB_DRAM_TIMING_TABLE_88__VI   regMCARB_DRAM_TIMING_TABLE_88__VI;
typedef union MCARB_DRAM_TIMING_TABLE_89__VI   regMCARB_DRAM_TIMING_TABLE_89__VI;
typedef union MCARB_DRAM_TIMING_TABLE_9__VI    regMCARB_DRAM_TIMING_TABLE_9__VI;
typedef union MCARB_DRAM_TIMING_TABLE_90__VI   regMCARB_DRAM_TIMING_TABLE_90__VI;
typedef union MCARB_DRAM_TIMING_TABLE_91__VI   regMCARB_DRAM_TIMING_TABLE_91__VI;
typedef union MCARB_DRAM_TIMING_TABLE_92__VI   regMCARB_DRAM_TIMING_TABLE_92__VI;
typedef union MCARB_DRAM_TIMING_TABLE_93__VI   regMCARB_DRAM_TIMING_TABLE_93__VI;
typedef union MCARB_DRAM_TIMING_TABLE_94__VI   regMCARB_DRAM_TIMING_TABLE_94__VI;
typedef union MCARB_DRAM_TIMING_TABLE_95__VI   regMCARB_DRAM_TIMING_TABLE_95__VI;
typedef union MCARB_DRAM_TIMING_TABLE_96__VI   regMCARB_DRAM_TIMING_TABLE_96__VI;
typedef union MCIF_MEM_CONTROL__VI             regMCIF_MEM_CONTROL__VI;
typedef union MCIF_VMID__VI                    regMCIF_VMID__VI;
typedef union MCIF_WB_ARBITRATION_CONTROL__VI  regMCIF_WB_ARBITRATION_CONTROL__VI;
typedef union MCIF_WB_BUFMGR_CUR_LINE_R__VI    regMCIF_WB_BUFMGR_CUR_LINE_R__VI;
typedef union MCIF_WB_BUFMGR_STATUS__VI        regMCIF_WB_BUFMGR_STATUS__VI;
typedef union MCIF_WB_BUFMGR_SW_CONTROL__VI    regMCIF_WB_BUFMGR_SW_CONTROL__VI;
typedef union MCIF_WB_BUFMGR_VCE_CONTROL__VI   regMCIF_WB_BUFMGR_VCE_CONTROL__VI;
typedef union MCIF_WB_BUF_1_ADDR_C__VI         regMCIF_WB_BUF_1_ADDR_C__VI;
typedef union MCIF_WB_BUF_1_ADDR_C_OFFSET__VI  regMCIF_WB_BUF_1_ADDR_C_OFFSET__VI;
typedef union MCIF_WB_BUF_1_ADDR_Y__VI         regMCIF_WB_BUF_1_ADDR_Y__VI;
typedef union MCIF_WB_BUF_1_ADDR_Y_OFFSET__VI  regMCIF_WB_BUF_1_ADDR_Y_OFFSET__VI;
typedef union MCIF_WB_BUF_1_STATUS__VI         regMCIF_WB_BUF_1_STATUS__VI;
typedef union MCIF_WB_BUF_1_STATUS2__VI        regMCIF_WB_BUF_1_STATUS2__VI;
typedef union MCIF_WB_BUF_2_ADDR_C__VI         regMCIF_WB_BUF_2_ADDR_C__VI;
typedef union MCIF_WB_BUF_2_ADDR_C_OFFSET__VI  regMCIF_WB_BUF_2_ADDR_C_OFFSET__VI;
typedef union MCIF_WB_BUF_2_ADDR_Y__VI         regMCIF_WB_BUF_2_ADDR_Y__VI;
typedef union MCIF_WB_BUF_2_ADDR_Y_OFFSET__VI  regMCIF_WB_BUF_2_ADDR_Y_OFFSET__VI;
typedef union MCIF_WB_BUF_2_STATUS__VI         regMCIF_WB_BUF_2_STATUS__VI;
typedef union MCIF_WB_BUF_2_STATUS2__VI        regMCIF_WB_BUF_2_STATUS2__VI;
typedef union MCIF_WB_BUF_3_ADDR_C__VI         regMCIF_WB_BUF_3_ADDR_C__VI;
typedef union MCIF_WB_BUF_3_ADDR_C_OFFSET__VI  regMCIF_WB_BUF_3_ADDR_C_OFFSET__VI;
typedef union MCIF_WB_BUF_3_ADDR_Y__VI         regMCIF_WB_BUF_3_ADDR_Y__VI;
typedef union MCIF_WB_BUF_3_ADDR_Y_OFFSET__VI  regMCIF_WB_BUF_3_ADDR_Y_OFFSET__VI;
typedef union MCIF_WB_BUF_3_STATUS__VI         regMCIF_WB_BUF_3_STATUS__VI;
typedef union MCIF_WB_BUF_3_STATUS2__VI        regMCIF_WB_BUF_3_STATUS2__VI;
typedef union MCIF_WB_BUF_4_ADDR_C__VI         regMCIF_WB_BUF_4_ADDR_C__VI;
typedef union MCIF_WB_BUF_4_ADDR_C_OFFSET__VI  regMCIF_WB_BUF_4_ADDR_C_OFFSET__VI;
typedef union MCIF_WB_BUF_4_ADDR_Y__VI         regMCIF_WB_BUF_4_ADDR_Y__VI;
typedef union MCIF_WB_BUF_4_ADDR_Y_OFFSET__VI  regMCIF_WB_BUF_4_ADDR_Y_OFFSET__VI;
typedef union MCIF_WB_BUF_4_STATUS__VI         regMCIF_WB_BUF_4_STATUS__VI;
typedef union MCIF_WB_BUF_4_STATUS2__VI        regMCIF_WB_BUF_4_STATUS2__VI;
typedef union MCIF_WB_BUF_PITCH__VI            regMCIF_WB_BUF_PITCH__VI;
typedef union MCIF_WB_HVVMID_CONTROL__VI       regMCIF_WB_HVVMID_CONTROL__VI;
typedef union MCIF_WB_TEST_DEBUG_DATA__VI      regMCIF_WB_TEST_DEBUG_DATA__VI;
typedef union MCIF_WB_TEST_DEBUG_INDEX__VI     regMCIF_WB_TEST_DEBUG_INDEX__VI;
typedef union MCIF_WB_URGENCY_WATERMARK__VI    regMCIF_WB_URGENCY_WATERMARK__VI;
typedef union MC_ARB_ATOMIC__VI                regMC_ARB_ATOMIC__VI;
typedef union MC_ARB_GRUB__VI                  regMC_ARB_GRUB__VI;
typedef union MC_ARB_GRUB2__VI                 regMC_ARB_GRUB2__VI;
typedef union MC_ARB_GRUB_PRIORITY1_RD__VI     regMC_ARB_GRUB_PRIORITY1_RD__VI;
typedef union MC_ARB_GRUB_PRIORITY1_WR__VI     regMC_ARB_GRUB_PRIORITY1_WR__VI;
typedef union MC_ARB_GRUB_PRIORITY2_RD__VI     regMC_ARB_GRUB_PRIORITY2_RD__VI;
typedef union MC_ARB_GRUB_PRIORITY2_WR__VI     regMC_ARB_GRUB_PRIORITY2_WR__VI;
typedef union MC_ARB_GRUB_PROMOTE__VI          regMC_ARB_GRUB_PROMOTE__VI;
typedef union MC_ARB_GRUB_REALTIME_RD__VI      regMC_ARB_GRUB_REALTIME_RD__VI;
typedef union MC_ARB_GRUB_REALTIME_WR__VI      regMC_ARB_GRUB_REALTIME_WR__VI;
typedef union MC_ARB_PERF_CID__VI              regMC_ARB_PERF_CID__VI;
typedef union MC_ARB_SNOOP__VI                 regMC_ARB_SNOOP__VI;
typedef union MC_BIST_CMD__VI                  regMC_BIST_CMD__VI;
typedef union MC_BIST_DAT__VI                  regMC_BIST_DAT__VI;
typedef union MC_CITF_CREDITS_ARB_RD2__VI      regMC_CITF_CREDITS_ARB_RD2__VI;
typedef union MC_FUS_ARB_GARLIC_CNTL__VI       regMC_FUS_ARB_GARLIC_CNTL__VI;
typedef union MC_FUS_ARB_GARLIC_ISOC_PRI__VI   regMC_FUS_ARB_GARLIC_ISOC_PRI__VI;
typedef union MC_FUS_ARB_GARLIC_WR_PRI__VI     regMC_FUS_ARB_GARLIC_WR_PRI__VI;
typedef union MC_FUS_ARB_GARLIC_WR_PRI2__VI    regMC_FUS_ARB_GARLIC_WR_PRI2__VI;
typedef union MC_FUS_DRAM0_BANK_ADDR_MAPPING__VI regMC_FUS_DRAM0_BANK_ADDR_MAPPING__VI;
typedef union MC_FUS_DRAM0_CS0_BASE__VI        regMC_FUS_DRAM0_CS0_BASE__VI;
typedef union MC_FUS_DRAM0_CS1_BASE__VI        regMC_FUS_DRAM0_CS1_BASE__VI;
typedef union MC_FUS_DRAM0_CS2_BASE__VI        regMC_FUS_DRAM0_CS2_BASE__VI;
typedef union MC_FUS_DRAM0_CS3_BASE__VI        regMC_FUS_DRAM0_CS3_BASE__VI;
typedef union MC_FUS_DRAM0_CTL_BASE__VI        regMC_FUS_DRAM0_CTL_BASE__VI;
typedef union MC_FUS_DRAM0_CTL_LIMIT__VI       regMC_FUS_DRAM0_CTL_LIMIT__VI;
typedef union MC_FUS_DRAM1_BANK_ADDR_MAPPING__VI regMC_FUS_DRAM1_BANK_ADDR_MAPPING__VI;
typedef union MC_FUS_DRAM1_CS0_BASE__VI        regMC_FUS_DRAM1_CS0_BASE__VI;
typedef union MC_FUS_DRAM1_CS1_BASE__VI        regMC_FUS_DRAM1_CS1_BASE__VI;
typedef union MC_FUS_DRAM1_CS2_BASE__VI        regMC_FUS_DRAM1_CS2_BASE__VI;
typedef union MC_FUS_DRAM1_CS3_BASE__VI        regMC_FUS_DRAM1_CS3_BASE__VI;
typedef union MC_FUS_DRAM1_CTL_BASE__VI        regMC_FUS_DRAM1_CTL_BASE__VI;
typedef union MC_FUS_DRAM1_CTL_LIMIT__VI       regMC_FUS_DRAM1_CTL_LIMIT__VI;
typedef union MC_FUS_DRAM_APER_BASE__VI        regMC_FUS_DRAM_APER_BASE__VI;
typedef union MC_FUS_DRAM_APER_DEF__VI         regMC_FUS_DRAM_APER_DEF__VI;
typedef union MC_FUS_DRAM_APER_TOP__VI         regMC_FUS_DRAM_APER_TOP__VI;
typedef union MC_FUS_DRAM_CTL_HIGH_01__VI      regMC_FUS_DRAM_CTL_HIGH_01__VI;
typedef union MC_FUS_DRAM_CTL_HIGH_23__VI      regMC_FUS_DRAM_CTL_HIGH_23__VI;
typedef union MC_FUS_DRAM_MODE__VI             regMC_FUS_DRAM_MODE__VI;
typedef union MC_GRUB_FEATURES__VI             regMC_GRUB_FEATURES__VI;
typedef union MC_GRUB_PERFCOUNTER0_CFG__VI     regMC_GRUB_PERFCOUNTER0_CFG__VI;
typedef union MC_GRUB_PERFCOUNTER1_CFG__VI     regMC_GRUB_PERFCOUNTER1_CFG__VI;
typedef union MC_GRUB_PERFCOUNTER_HI__VI       regMC_GRUB_PERFCOUNTER_HI__VI;
typedef union MC_GRUB_PERFCOUNTER_LO__VI       regMC_GRUB_PERFCOUNTER_LO__VI;
typedef union MC_GRUB_PERFCOUNTER_RSLT_CNTL__VI regMC_GRUB_PERFCOUNTER_RSLT_CNTL__VI;
typedef union MC_GRUB_POST_PROBE_DELAY__VI     regMC_GRUB_POST_PROBE_DELAY__VI;
typedef union MC_GRUB_PROBE_CREDITS__VI        regMC_GRUB_PROBE_CREDITS__VI;
typedef union MC_GRUB_PROBE_MAP__VI            regMC_GRUB_PROBE_MAP__VI;
typedef union MC_GRUB_TCB_DATA_HI__VI          regMC_GRUB_TCB_DATA_HI__VI;
typedef union MC_GRUB_TCB_DATA_LO__VI          regMC_GRUB_TCB_DATA_LO__VI;
typedef union MC_GRUB_TCB_INDEX__VI            regMC_GRUB_TCB_INDEX__VI;
typedef union MC_GRUB_TX_CREDITS__VI           regMC_GRUB_TX_CREDITS__VI;
typedef union MC_HUB_MISC_ATOMIC_IDLE_STATUS__VI regMC_HUB_MISC_ATOMIC_IDLE_STATUS__VI;
typedef union MC_HUB_RDREQ_BYPASS_GBL0__VI     regMC_HUB_RDREQ_BYPASS_GBL0__VI;
typedef union MC_HUB_RDREQ_ISP_CCPU__VI        regMC_HUB_RDREQ_ISP_CCPU__VI;
typedef union MC_HUB_RDREQ_ISP_MPM__VI         regMC_HUB_RDREQ_ISP_MPM__VI;
typedef union MC_HUB_RDREQ_ISP_SPM__VI         regMC_HUB_RDREQ_ISP_SPM__VI;
typedef union MC_HUB_RDREQ_MCDS__VI            regMC_HUB_RDREQ_MCDS__VI;
typedef union MC_HUB_RDREQ_MCDT__VI            regMC_HUB_RDREQ_MCDT__VI;
typedef union MC_HUB_RDREQ_MCDU__VI            regMC_HUB_RDREQ_MCDU__VI;
typedef union MC_HUB_RDREQ_MCDV__VI            regMC_HUB_RDREQ_MCDV__VI;
typedef union MC_HUB_RDREQ_SAMMSP__VI          regMC_HUB_RDREQ_SAMMSP__VI;
typedef union MC_HUB_RDREQ_TLS__VI             regMC_HUB_RDREQ_TLS__VI;
typedef union MC_HUB_RDREQ_VCE0__VI            regMC_HUB_RDREQ_VCE0__VI;
typedef union MC_HUB_RDREQ_VCE1__VI            regMC_HUB_RDREQ_VCE1__VI;
typedef union MC_HUB_RDREQ_VCEU0__VI           regMC_HUB_RDREQ_VCEU0__VI;
typedef union MC_HUB_RDREQ_VCEU1__VI           regMC_HUB_RDREQ_VCEU1__VI;
typedef union MC_HUB_RDREQ_VP8__VI             regMC_HUB_RDREQ_VP8__VI;
typedef union MC_HUB_RDREQ_VP8U__VI            regMC_HUB_RDREQ_VP8U__VI;
typedef union MC_HUB_WDP_BP2__VI               regMC_HUB_WDP_BP2__VI;
typedef union MC_HUB_WDP_BYPASS_GBL0__VI       regMC_HUB_WDP_BYPASS_GBL0__VI;
typedef union MC_HUB_WDP_BYPASS_GBL1__VI       regMC_HUB_WDP_BYPASS_GBL1__VI;
typedef union MC_HUB_WDP_CREDITS2__VI          regMC_HUB_WDP_CREDITS2__VI;
typedef union MC_HUB_WDP_CREDITS3__VI          regMC_HUB_WDP_CREDITS3__VI;
typedef union MC_HUB_WDP_CREDITS_MCDS__VI      regMC_HUB_WDP_CREDITS_MCDS__VI;
typedef union MC_HUB_WDP_CREDITS_MCDT__VI      regMC_HUB_WDP_CREDITS_MCDT__VI;
typedef union MC_HUB_WDP_CREDITS_MCDU__VI      regMC_HUB_WDP_CREDITS_MCDU__VI;
typedef union MC_HUB_WDP_CREDITS_MCDV__VI      regMC_HUB_WDP_CREDITS_MCDV__VI;
typedef union MC_HUB_WDP_CREDITS_MCDW__VI      regMC_HUB_WDP_CREDITS_MCDW__VI;
typedef union MC_HUB_WDP_CREDITS_MCDX__VI      regMC_HUB_WDP_CREDITS_MCDX__VI;
typedef union MC_HUB_WDP_CREDITS_MCDY__VI      regMC_HUB_WDP_CREDITS_MCDY__VI;
typedef union MC_HUB_WDP_CREDITS_MCDZ__VI      regMC_HUB_WDP_CREDITS_MCDZ__VI;
typedef union MC_HUB_WDP_ISP_CCPU__VI          regMC_HUB_WDP_ISP_CCPU__VI;
typedef union MC_HUB_WDP_ISP_MPM__VI           regMC_HUB_WDP_ISP_MPM__VI;
typedef union MC_HUB_WDP_ISP_MPS__VI           regMC_HUB_WDP_ISP_MPS__VI;
typedef union MC_HUB_WDP_ISP_SPM__VI           regMC_HUB_WDP_ISP_SPM__VI;
typedef union MC_HUB_WDP_MCDS__VI              regMC_HUB_WDP_MCDS__VI;
typedef union MC_HUB_WDP_MCDT__VI              regMC_HUB_WDP_MCDT__VI;
typedef union MC_HUB_WDP_MCDU__VI              regMC_HUB_WDP_MCDU__VI;
typedef union MC_HUB_WDP_MCDV__VI              regMC_HUB_WDP_MCDV__VI;
typedef union MC_HUB_WDP_SAMMSP__VI            regMC_HUB_WDP_SAMMSP__VI;
typedef union MC_HUB_WDP_VCE0__VI              regMC_HUB_WDP_VCE0__VI;
typedef union MC_HUB_WDP_VCE1__VI              regMC_HUB_WDP_VCE1__VI;
typedef union MC_HUB_WDP_VCEU0__VI             regMC_HUB_WDP_VCEU0__VI;
typedef union MC_HUB_WDP_VCEU1__VI             regMC_HUB_WDP_VCEU1__VI;
typedef union MC_HUB_WDP_VIN0__VI              regMC_HUB_WDP_VIN0__VI;
typedef union MC_HUB_WDP_VP8__VI               regMC_HUB_WDP_VP8__VI;
typedef union MC_HUB_WDP_VP8U__VI              regMC_HUB_WDP_VP8U__VI;
typedef union MC_HUB_WRRET_MCDS__VI            regMC_HUB_WRRET_MCDS__VI;
typedef union MC_HUB_WRRET_MCDT__VI            regMC_HUB_WRRET_MCDT__VI;
typedef union MC_HUB_WRRET_MCDU__VI            regMC_HUB_WRRET_MCDU__VI;
typedef union MC_HUB_WRRET_MCDV__VI            regMC_HUB_WRRET_MCDV__VI;
typedef union MC_RPB_TCI_CNTL__VI              regMC_RPB_TCI_CNTL__VI;
typedef union MC_RPB_TCI_CNTL2__VI             regMC_RPB_TCI_CNTL2__VI;
typedef union MC_SEQ_IO_RESERVE__VI            regMC_SEQ_IO_RESERVE__VI;
typedef union MC_SHARED_ACTIVE_FCN_ID__VI      regMC_SHARED_ACTIVE_FCN_ID__VI;
typedef union MC_SHARED_CHREMAP2__VI           regMC_SHARED_CHREMAP2__VI;
typedef union MC_SHARED_VF_ENABLE__VI          regMC_SHARED_VF_ENABLE__VI;
typedef union MC_SHARED_VIRT_RESET_REQ__VI     regMC_SHARED_VIRT_RESET_REQ__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF0__VI     regMC_VM_FB_SIZE_OFFSET_VF0__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF1__VI     regMC_VM_FB_SIZE_OFFSET_VF1__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF10__VI    regMC_VM_FB_SIZE_OFFSET_VF10__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF11__VI    regMC_VM_FB_SIZE_OFFSET_VF11__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF12__VI    regMC_VM_FB_SIZE_OFFSET_VF12__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF13__VI    regMC_VM_FB_SIZE_OFFSET_VF13__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF14__VI    regMC_VM_FB_SIZE_OFFSET_VF14__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF15__VI    regMC_VM_FB_SIZE_OFFSET_VF15__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF2__VI     regMC_VM_FB_SIZE_OFFSET_VF2__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF3__VI     regMC_VM_FB_SIZE_OFFSET_VF3__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF4__VI     regMC_VM_FB_SIZE_OFFSET_VF4__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF5__VI     regMC_VM_FB_SIZE_OFFSET_VF5__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF6__VI     regMC_VM_FB_SIZE_OFFSET_VF6__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF7__VI     regMC_VM_FB_SIZE_OFFSET_VF7__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF8__VI     regMC_VM_FB_SIZE_OFFSET_VF8__VI;
typedef union MC_VM_FB_SIZE_OFFSET_VF9__VI     regMC_VM_FB_SIZE_OFFSET_VF9__VI;
typedef union MC_VM_MARC_BASE_HI_0__VI         regMC_VM_MARC_BASE_HI_0__VI;
typedef union MC_VM_MARC_BASE_HI_1__VI         regMC_VM_MARC_BASE_HI_1__VI;
typedef union MC_VM_MARC_BASE_HI_2__VI         regMC_VM_MARC_BASE_HI_2__VI;
typedef union MC_VM_MARC_BASE_HI_3__VI         regMC_VM_MARC_BASE_HI_3__VI;
typedef union MC_VM_MARC_BASE_LO_0__VI         regMC_VM_MARC_BASE_LO_0__VI;
typedef union MC_VM_MARC_BASE_LO_1__VI         regMC_VM_MARC_BASE_LO_1__VI;
typedef union MC_VM_MARC_BASE_LO_2__VI         regMC_VM_MARC_BASE_LO_2__VI;
typedef union MC_VM_MARC_BASE_LO_3__VI         regMC_VM_MARC_BASE_LO_3__VI;
typedef union MC_VM_MARC_CNTL__VI              regMC_VM_MARC_CNTL__VI;
typedef union MC_VM_MARC_LEN_HI_0__VI          regMC_VM_MARC_LEN_HI_0__VI;
typedef union MC_VM_MARC_LEN_HI_1__VI          regMC_VM_MARC_LEN_HI_1__VI;
typedef union MC_VM_MARC_LEN_HI_2__VI          regMC_VM_MARC_LEN_HI_2__VI;
typedef union MC_VM_MARC_LEN_HI_3__VI          regMC_VM_MARC_LEN_HI_3__VI;
typedef union MC_VM_MARC_LEN_LO_0__VI          regMC_VM_MARC_LEN_LO_0__VI;
typedef union MC_VM_MARC_LEN_LO_1__VI          regMC_VM_MARC_LEN_LO_1__VI;
typedef union MC_VM_MARC_LEN_LO_2__VI          regMC_VM_MARC_LEN_LO_2__VI;
typedef union MC_VM_MARC_LEN_LO_3__VI          regMC_VM_MARC_LEN_LO_3__VI;
typedef union MC_VM_MARC_RELOC_HI_0__VI        regMC_VM_MARC_RELOC_HI_0__VI;
typedef union MC_VM_MARC_RELOC_HI_1__VI        regMC_VM_MARC_RELOC_HI_1__VI;
typedef union MC_VM_MARC_RELOC_HI_2__VI        regMC_VM_MARC_RELOC_HI_2__VI;
typedef union MC_VM_MARC_RELOC_HI_3__VI        regMC_VM_MARC_RELOC_HI_3__VI;
typedef union MC_VM_MARC_RELOC_LO_0__VI        regMC_VM_MARC_RELOC_LO_0__VI;
typedef union MC_VM_MARC_RELOC_LO_1__VI        regMC_VM_MARC_RELOC_LO_1__VI;
typedef union MC_VM_MARC_RELOC_LO_2__VI        regMC_VM_MARC_RELOC_LO_2__VI;
typedef union MC_VM_MARC_RELOC_LO_3__VI        regMC_VM_MARC_RELOC_LO_3__VI;
typedef union MC_VM_MB_L1_TLB1_DEBUG__VI       regMC_VM_MB_L1_TLB1_DEBUG__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL0__VI       regMC_VM_MB_L1_TLS0_CNTL0__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL1__VI       regMC_VM_MB_L1_TLS0_CNTL1__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL2__VI       regMC_VM_MB_L1_TLS0_CNTL2__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL3__VI       regMC_VM_MB_L1_TLS0_CNTL3__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL4__VI       regMC_VM_MB_L1_TLS0_CNTL4__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL5__VI       regMC_VM_MB_L1_TLS0_CNTL5__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL6__VI       regMC_VM_MB_L1_TLS0_CNTL6__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL7__VI       regMC_VM_MB_L1_TLS0_CNTL7__VI;
typedef union MC_VM_MB_L1_TLS0_CNTL8__VI       regMC_VM_MB_L1_TLS0_CNTL8__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR0__VI   regMC_VM_MB_L1_TLS0_END_ADDR0__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR1__VI   regMC_VM_MB_L1_TLS0_END_ADDR1__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR2__VI   regMC_VM_MB_L1_TLS0_END_ADDR2__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR3__VI   regMC_VM_MB_L1_TLS0_END_ADDR3__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR4__VI   regMC_VM_MB_L1_TLS0_END_ADDR4__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR5__VI   regMC_VM_MB_L1_TLS0_END_ADDR5__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR6__VI   regMC_VM_MB_L1_TLS0_END_ADDR6__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR7__VI   regMC_VM_MB_L1_TLS0_END_ADDR7__VI;
typedef union MC_VM_MB_L1_TLS0_END_ADDR8__VI   regMC_VM_MB_L1_TLS0_END_ADDR8__VI;
typedef union MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__VI regMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__VI;
typedef union MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VI regMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR0__VI regMC_VM_MB_L1_TLS0_START_ADDR0__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR1__VI regMC_VM_MB_L1_TLS0_START_ADDR1__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR2__VI regMC_VM_MB_L1_TLS0_START_ADDR2__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR3__VI regMC_VM_MB_L1_TLS0_START_ADDR3__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR4__VI regMC_VM_MB_L1_TLS0_START_ADDR4__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR5__VI regMC_VM_MB_L1_TLS0_START_ADDR5__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR6__VI regMC_VM_MB_L1_TLS0_START_ADDR6__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR7__VI regMC_VM_MB_L1_TLS0_START_ADDR7__VI;
typedef union MC_VM_MB_L1_TLS0_START_ADDR8__VI regMC_VM_MB_L1_TLS0_START_ADDR8__VI;
typedef union MC_VM_NB_LOWER_TOP_OF_DRAM2__VI  regMC_VM_NB_LOWER_TOP_OF_DRAM2__VI;
typedef union MC_VM_NB_MMIOBASE__VI            regMC_VM_NB_MMIOBASE__VI;
typedef union MC_VM_NB_MMIOLIMIT__VI           regMC_VM_NB_MMIOLIMIT__VI;
typedef union MC_VM_NB_PCI_ARB__VI             regMC_VM_NB_PCI_ARB__VI;
typedef union MC_VM_NB_PCI_CTRL__VI            regMC_VM_NB_PCI_CTRL__VI;
typedef union MC_VM_NB_TOP_OF_DRAM3__VI        regMC_VM_NB_TOP_OF_DRAM3__VI;
typedef union MC_VM_NB_TOP_OF_DRAM_SLOT1__VI   regMC_VM_NB_TOP_OF_DRAM_SLOT1__VI;
typedef union MC_VM_NB_UPPER_TOP_OF_DRAM2__VI  regMC_VM_NB_UPPER_TOP_OF_DRAM2__VI;
typedef union MC_XBAR_FIFO_MON_CNTL0__VI       regMC_XBAR_FIFO_MON_CNTL0__VI;
typedef union MC_XBAR_FIFO_MON_CNTL1__VI       regMC_XBAR_FIFO_MON_CNTL1__VI;
typedef union MC_XBAR_FIFO_MON_CNTL2__VI       regMC_XBAR_FIFO_MON_CNTL2__VI;
typedef union MC_XBAR_FIFO_MON_MAX_THSH__VI    regMC_XBAR_FIFO_MON_MAX_THSH__VI;
typedef union MC_XBAR_FIFO_MON_RSLT0__VI       regMC_XBAR_FIFO_MON_RSLT0__VI;
typedef union MC_XBAR_FIFO_MON_RSLT1__VI       regMC_XBAR_FIFO_MON_RSLT1__VI;
typedef union MC_XBAR_FIFO_MON_RSLT2__VI       regMC_XBAR_FIFO_MON_RSLT2__VI;
typedef union MC_XBAR_FIFO_MON_RSLT3__VI       regMC_XBAR_FIFO_MON_RSLT3__VI;
typedef union MILLISECOND_TIME_BASE_DIV__VI    regMILLISECOND_TIME_BASE_DIV__VI;
typedef union MP_FPS_CNT__VI                   regMP_FPS_CNT__VI;
typedef union MSI_MASK__VI                     regMSI_MASK__VI;
typedef union MSI_MASK_64__VI                  regMSI_MASK_64__VI;
typedef union MSI_PENDING__VI                  regMSI_PENDING__VI;
typedef union MSI_PENDING_64__VI               regMSI_PENDING_64__VI;
typedef union MVP_DEBUG__VI                    regMVP_DEBUG__VI;
typedef union OUTPUT_CSC_C11_C12__VI           regOUTPUT_CSC_C11_C12__VI;
typedef union OUTPUT_CSC_C11_C12_A__VI         regOUTPUT_CSC_C11_C12_A__VI;
typedef union OUTPUT_CSC_C11_C12_B__VI         regOUTPUT_CSC_C11_C12_B__VI;
typedef union OUTPUT_CSC_C13_C14__VI           regOUTPUT_CSC_C13_C14__VI;
typedef union OUTPUT_CSC_C13_C14_A__VI         regOUTPUT_CSC_C13_C14_A__VI;
typedef union OUTPUT_CSC_C13_C14_B__VI         regOUTPUT_CSC_C13_C14_B__VI;
typedef union OUTPUT_CSC_C21_C22__VI           regOUTPUT_CSC_C21_C22__VI;
typedef union OUTPUT_CSC_C21_C22_A__VI         regOUTPUT_CSC_C21_C22_A__VI;
typedef union OUTPUT_CSC_C21_C22_B__VI         regOUTPUT_CSC_C21_C22_B__VI;
typedef union OUTPUT_CSC_C23_C24__VI           regOUTPUT_CSC_C23_C24__VI;
typedef union OUTPUT_CSC_C23_C24_A__VI         regOUTPUT_CSC_C23_C24_A__VI;
typedef union OUTPUT_CSC_C23_C24_B__VI         regOUTPUT_CSC_C23_C24_B__VI;
typedef union OUTPUT_CSC_C31_C32__VI           regOUTPUT_CSC_C31_C32__VI;
typedef union OUTPUT_CSC_C31_C32_A__VI         regOUTPUT_CSC_C31_C32_A__VI;
typedef union OUTPUT_CSC_C31_C32_B__VI         regOUTPUT_CSC_C31_C32_B__VI;
typedef union OUTPUT_CSC_C33_C34__VI           regOUTPUT_CSC_C33_C34__VI;
typedef union OUTPUT_CSC_C33_C34_A__VI         regOUTPUT_CSC_C33_C34_A__VI;
typedef union OUTPUT_CSC_C33_C34_B__VI         regOUTPUT_CSC_C33_C34_B__VI;
typedef union OUTPUT_CSC_CONTROL__VI           regOUTPUT_CSC_CONTROL__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__VI regOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__VI regOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__VI regOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__VI regOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__VI regOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_FORMAT__VI regOUTPUT_STREAM_DESCRIPTOR_FORMAT__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__VI regOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__VI regOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__VI;
typedef union OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__VI regOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__VI;
typedef union OUTPUT_STREAM_PAYLOAD_CAPABILITY__VI regOUTPUT_STREAM_PAYLOAD_CAPABILITY__VI;
typedef union OUT_CLAMP_CONTROL_B_CB__VI       regOUT_CLAMP_CONTROL_B_CB__VI;
typedef union OUT_CLAMP_CONTROL_G_Y__VI        regOUT_CLAMP_CONTROL_G_Y__VI;
typedef union OUT_CLAMP_CONTROL_R_CR__VI       regOUT_CLAMP_CONTROL_R_CR__VI;
typedef union OUT_ROUND_CONTROL__VI            regOUT_ROUND_CONTROL__VI;
typedef union OVL_SECONDARY_SURFACE_ADDRESS__VI regOVL_SECONDARY_SURFACE_ADDRESS__VI;
typedef union OVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI regOVL_SECONDARY_SURFACE_ADDRESS_HIGH__VI;
typedef union OVL_STEREOSYNC_FLIP__VI          regOVL_STEREOSYNC_FLIP__VI;
typedef union PB0_PIF_BIF_CMD_STATUS__VI       regPB0_PIF_BIF_CMD_STATUS__VI;
typedef union PB0_PIF_CMD_BUS_CTRL__VI         regPB0_PIF_CMD_BUS_CTRL__VI;
typedef union PB0_PIF_CMD_BUS_GLB_OVRD__VI     regPB0_PIF_CMD_BUS_GLB_OVRD__VI;
typedef union PB0_PIF_CTRL__VI                 regPB0_PIF_CTRL__VI;
typedef union PB0_PIF_GLB_OVRD__VI             regPB0_PIF_GLB_OVRD__VI;
typedef union PB0_PIF_GLB_OVRD2__VI            regPB0_PIF_GLB_OVRD2__VI;
typedef union PB0_PIF_LANE0_OVRD__VI           regPB0_PIF_LANE0_OVRD__VI;
typedef union PB0_PIF_LANE0_OVRD2__VI          regPB0_PIF_LANE0_OVRD2__VI;
typedef union PB0_PIF_LANE1_OVRD__VI           regPB0_PIF_LANE1_OVRD__VI;
typedef union PB0_PIF_LANE1_OVRD2__VI          regPB0_PIF_LANE1_OVRD2__VI;
typedef union PB0_PIF_LANE2_OVRD__VI           regPB0_PIF_LANE2_OVRD__VI;
typedef union PB0_PIF_LANE2_OVRD2__VI          regPB0_PIF_LANE2_OVRD2__VI;
typedef union PB0_PIF_LANE3_OVRD__VI           regPB0_PIF_LANE3_OVRD__VI;
typedef union PB0_PIF_LANE3_OVRD2__VI          regPB0_PIF_LANE3_OVRD2__VI;
typedef union PB0_PIF_LANE4_OVRD__VI           regPB0_PIF_LANE4_OVRD__VI;
typedef union PB0_PIF_LANE4_OVRD2__VI          regPB0_PIF_LANE4_OVRD2__VI;
typedef union PB0_PIF_LANE5_OVRD__VI           regPB0_PIF_LANE5_OVRD__VI;
typedef union PB0_PIF_LANE5_OVRD2__VI          regPB0_PIF_LANE5_OVRD2__VI;
typedef union PB0_PIF_LANE6_OVRD__VI           regPB0_PIF_LANE6_OVRD__VI;
typedef union PB0_PIF_LANE6_OVRD2__VI          regPB0_PIF_LANE6_OVRD2__VI;
typedef union PB0_PIF_LANE7_OVRD__VI           regPB0_PIF_LANE7_OVRD__VI;
typedef union PB0_PIF_LANE7_OVRD2__VI          regPB0_PIF_LANE7_OVRD2__VI;
typedef union PB0_PIF_RX_CTRL__VI              regPB0_PIF_RX_CTRL__VI;
typedef union PB0_PIF_RX_CTRL2__VI             regPB0_PIF_RX_CTRL2__VI;
typedef union PB0_PIF_STRAP_0__VI              regPB0_PIF_STRAP_0__VI;
typedef union PB0_PIF_TX_CTRL__VI              regPB0_PIF_TX_CTRL__VI;
typedef union PB0_PIF_TX_CTRL2__VI             regPB0_PIF_TX_CTRL2__VI;
typedef union PB0_STRAP_GLB_REG1__VI           regPB0_STRAP_GLB_REG1__VI;
typedef union PB0_STRAP_GLB_REG2__VI           regPB0_STRAP_GLB_REG2__VI;
typedef union PB1_PIF_BIF_CMD_STATUS__VI       regPB1_PIF_BIF_CMD_STATUS__VI;
typedef union PB1_PIF_CMD_BUS_CTRL__VI         regPB1_PIF_CMD_BUS_CTRL__VI;
typedef union PB1_PIF_CMD_BUS_GLB_OVRD__VI     regPB1_PIF_CMD_BUS_GLB_OVRD__VI;
typedef union PB1_PIF_CTRL__VI                 regPB1_PIF_CTRL__VI;
typedef union PB1_PIF_GLB_OVRD__VI             regPB1_PIF_GLB_OVRD__VI;
typedef union PB1_PIF_GLB_OVRD2__VI            regPB1_PIF_GLB_OVRD2__VI;
typedef union PB1_PIF_LANE0_OVRD__VI           regPB1_PIF_LANE0_OVRD__VI;
typedef union PB1_PIF_LANE0_OVRD2__VI          regPB1_PIF_LANE0_OVRD2__VI;
typedef union PB1_PIF_LANE1_OVRD__VI           regPB1_PIF_LANE1_OVRD__VI;
typedef union PB1_PIF_LANE1_OVRD2__VI          regPB1_PIF_LANE1_OVRD2__VI;
typedef union PB1_PIF_LANE2_OVRD__VI           regPB1_PIF_LANE2_OVRD__VI;
typedef union PB1_PIF_LANE2_OVRD2__VI          regPB1_PIF_LANE2_OVRD2__VI;
typedef union PB1_PIF_LANE3_OVRD__VI           regPB1_PIF_LANE3_OVRD__VI;
typedef union PB1_PIF_LANE3_OVRD2__VI          regPB1_PIF_LANE3_OVRD2__VI;
typedef union PB1_PIF_LANE4_OVRD__VI           regPB1_PIF_LANE4_OVRD__VI;
typedef union PB1_PIF_LANE4_OVRD2__VI          regPB1_PIF_LANE4_OVRD2__VI;
typedef union PB1_PIF_LANE5_OVRD__VI           regPB1_PIF_LANE5_OVRD__VI;
typedef union PB1_PIF_LANE5_OVRD2__VI          regPB1_PIF_LANE5_OVRD2__VI;
typedef union PB1_PIF_LANE6_OVRD__VI           regPB1_PIF_LANE6_OVRD__VI;
typedef union PB1_PIF_LANE6_OVRD2__VI          regPB1_PIF_LANE6_OVRD2__VI;
typedef union PB1_PIF_LANE7_OVRD__VI           regPB1_PIF_LANE7_OVRD__VI;
typedef union PB1_PIF_LANE7_OVRD2__VI          regPB1_PIF_LANE7_OVRD2__VI;
typedef union PB1_PIF_RX_CTRL__VI              regPB1_PIF_RX_CTRL__VI;
typedef union PB1_PIF_RX_CTRL2__VI             regPB1_PIF_RX_CTRL2__VI;
typedef union PB1_PIF_STRAP_0__VI              regPB1_PIF_STRAP_0__VI;
typedef union PB1_PIF_TX_CTRL__VI              regPB1_PIF_TX_CTRL__VI;
typedef union PB1_PIF_TX_CTRL2__VI             regPB1_PIF_TX_CTRL2__VI;
typedef union PB1_STRAP_GLB_REG1__VI           regPB1_STRAP_GLB_REG1__VI;
typedef union PB1_STRAP_GLB_REG2__VI           regPB1_STRAP_GLB_REG2__VI;
typedef union PCIEP_ERROR_INJECT_PHYSICAL__VI  regPCIEP_ERROR_INJECT_PHYSICAL__VI;
typedef union PCIEP_ERROR_INJECT_TRANSACTION__VI regPCIEP_ERROR_INJECT_TRANSACTION__VI;
typedef union PCIEP_SRIOV_PRIV_CTRL__VI        regPCIEP_SRIOV_PRIV_CTRL__VI;
typedef union PCIE_ARI_CAP__VI                 regPCIE_ARI_CAP__VI;
typedef union PCIE_ARI_CNTL__VI                regPCIE_ARI_CNTL__VI;
typedef union PCIE_ARI_ENH_CAP_LIST__VI        regPCIE_ARI_ENH_CAP_LIST__VI;
typedef union PCIE_EFUSE__VI                   regPCIE_EFUSE__VI;
typedef union PCIE_EFUSE2__VI                  regPCIE_EFUSE2__VI;
typedef union PCIE_EFUSE3__VI                  regPCIE_EFUSE3__VI;
typedef union PCIE_EFUSE4__VI                  regPCIE_EFUSE4__VI;
typedef union PCIE_EFUSE5__VI                  regPCIE_EFUSE5__VI;
typedef union PCIE_EFUSE6__VI                  regPCIE_EFUSE6__VI;
typedef union PCIE_EFUSE7__VI                  regPCIE_EFUSE7__VI;
typedef union PCIE_HOLD_TRAINING_A__VI         regPCIE_HOLD_TRAINING_A__VI;
typedef union PCIE_LC_BEST_EQ_SETTINGS__VI     regPCIE_LC_BEST_EQ_SETTINGS__VI;
typedef union PCIE_LC_CNTL6__VI                regPCIE_LC_CNTL6__VI;
typedef union PCIE_LC_FORCE_EQ_REQ_COEFF__VI   regPCIE_LC_FORCE_EQ_REQ_COEFF__VI;
typedef union PCIE_LTR_CAP__VI                 regPCIE_LTR_CAP__VI;
typedef union PCIE_LTR_ENH_CAP_LIST__VI        regPCIE_LTR_ENH_CAP_LIST__VI;
typedef union PCIE_MC_ADDR0__VI                regPCIE_MC_ADDR0__VI;
typedef union PCIE_MC_ADDR1__VI                regPCIE_MC_ADDR1__VI;
typedef union PCIE_MC_BLOCK_ALL0__VI           regPCIE_MC_BLOCK_ALL0__VI;
typedef union PCIE_MC_BLOCK_ALL1__VI           regPCIE_MC_BLOCK_ALL1__VI;
typedef union PCIE_MC_BLOCK_UNTRANSLATED_0__VI regPCIE_MC_BLOCK_UNTRANSLATED_0__VI;
typedef union PCIE_MC_BLOCK_UNTRANSLATED_1__VI regPCIE_MC_BLOCK_UNTRANSLATED_1__VI;
typedef union PCIE_MC_CAP__VI                  regPCIE_MC_CAP__VI;
typedef union PCIE_MC_CNTL__VI                 regPCIE_MC_CNTL__VI;
typedef union PCIE_MC_ENH_CAP_LIST__VI         regPCIE_MC_ENH_CAP_LIST__VI;
typedef union PCIE_MC_RCV0__VI                 regPCIE_MC_RCV0__VI;
typedef union PCIE_MC_RCV1__VI                 regPCIE_MC_RCV1__VI;
typedef union PCIE_OBFF_CNTL__VI               regPCIE_OBFF_CNTL__VI;
typedef union PCIE_RXDET_OVERRIDE__VI          regPCIE_RXDET_OVERRIDE__VI;
typedef union PCIE_SRIOV_CAP__VI               regPCIE_SRIOV_CAP__VI;
typedef union PCIE_SRIOV_CONTROL__VI           regPCIE_SRIOV_CONTROL__VI;
typedef union PCIE_SRIOV_ENH_CAP_LIST__VI      regPCIE_SRIOV_ENH_CAP_LIST__VI;
typedef union PCIE_SRIOV_FIRST_VF_OFFSET__VI   regPCIE_SRIOV_FIRST_VF_OFFSET__VI;
typedef union PCIE_SRIOV_FUNC_DEP_LINK__VI     regPCIE_SRIOV_FUNC_DEP_LINK__VI;
typedef union PCIE_SRIOV_INITIAL_VFS__VI       regPCIE_SRIOV_INITIAL_VFS__VI;
typedef union PCIE_SRIOV_NUM_VFS__VI           regPCIE_SRIOV_NUM_VFS__VI;
typedef union PCIE_SRIOV_STATUS__VI            regPCIE_SRIOV_STATUS__VI;
typedef union PCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI regPCIE_SRIOV_SUPPORTED_PAGE_SIZE__VI;
typedef union PCIE_SRIOV_SYSTEM_PAGE_SIZE__VI  regPCIE_SRIOV_SYSTEM_PAGE_SIZE__VI;
typedef union PCIE_SRIOV_TOTAL_VFS__VI         regPCIE_SRIOV_TOTAL_VFS__VI;
typedef union PCIE_SRIOV_VF_BASE_ADDR_0__VI    regPCIE_SRIOV_VF_BASE_ADDR_0__VI;
typedef union PCIE_SRIOV_VF_BASE_ADDR_1__VI    regPCIE_SRIOV_VF_BASE_ADDR_1__VI;
typedef union PCIE_SRIOV_VF_BASE_ADDR_2__VI    regPCIE_SRIOV_VF_BASE_ADDR_2__VI;
typedef union PCIE_SRIOV_VF_BASE_ADDR_3__VI    regPCIE_SRIOV_VF_BASE_ADDR_3__VI;
typedef union PCIE_SRIOV_VF_BASE_ADDR_4__VI    regPCIE_SRIOV_VF_BASE_ADDR_4__VI;
typedef union PCIE_SRIOV_VF_BASE_ADDR_5__VI    regPCIE_SRIOV_VF_BASE_ADDR_5__VI;
typedef union PCIE_SRIOV_VF_DEVICE_ID__VI      regPCIE_SRIOV_VF_DEVICE_ID__VI;
typedef union PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI regPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__VI;
typedef union PCIE_SRIOV_VF_STRIDE__VI         regPCIE_SRIOV_VF_STRIDE__VI;
typedef union PCIE_TPH_REQR_CAP__VI            regPCIE_TPH_REQR_CAP__VI;
typedef union PCIE_TPH_REQR_CNTL__VI           regPCIE_TPH_REQR_CNTL__VI;
typedef union PCIE_TPH_REQR_ENH_CAP_LIST__VI   regPCIE_TPH_REQR_ENH_CAP_LIST__VI;
typedef union PCIE_TX_LTR_CNTL__VI             regPCIE_TX_LTR_CNTL__VI;
typedef union PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI regPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__VI;
typedef union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI regPCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VI;
typedef union PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI regPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__VI;
typedef union PCIE_WRAP_DTM_MISC__VI           regPCIE_WRAP_DTM_MISC__VI;
typedef union PCIE_WRAP_MISC__VI               regPCIE_WRAP_MISC__VI;
typedef union PCIE_WRAP_PIF_MISC__VI           regPCIE_WRAP_PIF_MISC__VI;
typedef union PCIE_WRAP_REG_TARG_MISC__VI      regPCIE_WRAP_REG_TARG_MISC__VI;
typedef union PCIE_WRAP_SCRATCH1__VI           regPCIE_WRAP_SCRATCH1__VI;
typedef union PCIE_WRAP_SCRATCH2__VI           regPCIE_WRAP_SCRATCH2__VI;
typedef union PCIE_WRAP_TURNAROUND_DAISYCHAIN__VI regPCIE_WRAP_TURNAROUND_DAISYCHAIN__VI;
typedef union PERFCOUNTER_CNTL__VI             regPERFCOUNTER_CNTL__VI;
typedef union PERFCOUNTER_STATE__VI            regPERFCOUNTER_STATE__VI;
typedef union PERFMON_CNTL__VI                 regPERFMON_CNTL__VI;
typedef union PERFMON_CNTL2__VI                regPERFMON_CNTL2__VI;
typedef union PERFMON_CVALUE_INT_MISC__VI      regPERFMON_CVALUE_INT_MISC__VI;
typedef union PERFMON_CVALUE_LOW__VI           regPERFMON_CVALUE_LOW__VI;
typedef union PERFMON_HI__VI                   regPERFMON_HI__VI;
typedef union PERFMON_LOW__VI                  regPERFMON_LOW__VI;
typedef union PERFMON_TEST_DEBUG_DATA__VI      regPERFMON_TEST_DEBUG_DATA__VI;
typedef union PERFMON_TEST_DEBUG_INDEX__VI     regPERFMON_TEST_DEBUG_INDEX__VI;
typedef union PIPE0_DMIF_BUFFER_CONTROL__VI    regPIPE0_DMIF_BUFFER_CONTROL__VI;
typedef union PIPE0_MAX_REQUESTS__VI           regPIPE0_MAX_REQUESTS__VI;
typedef union PIPE0_PG_CONFIG__VI              regPIPE0_PG_CONFIG__VI;
typedef union PIPE0_PG_ENABLE__VI              regPIPE0_PG_ENABLE__VI;
typedef union PIPE0_PG_STATUS__VI              regPIPE0_PG_STATUS__VI;
typedef union PIPE1_DMIF_BUFFER_CONTROL__VI    regPIPE1_DMIF_BUFFER_CONTROL__VI;
typedef union PIPE1_MAX_REQUESTS__VI           regPIPE1_MAX_REQUESTS__VI;
typedef union PIPE1_PG_CONFIG__VI              regPIPE1_PG_CONFIG__VI;
typedef union PIPE1_PG_ENABLE__VI              regPIPE1_PG_ENABLE__VI;
typedef union PIPE1_PG_STATUS__VI              regPIPE1_PG_STATUS__VI;
typedef union PIPE2_DMIF_BUFFER_CONTROL__VI    regPIPE2_DMIF_BUFFER_CONTROL__VI;
typedef union PIPE2_MAX_REQUESTS__VI           regPIPE2_MAX_REQUESTS__VI;
typedef union PIPE2_PG_CONFIG__VI              regPIPE2_PG_CONFIG__VI;
typedef union PIPE2_PG_ENABLE__VI              regPIPE2_PG_ENABLE__VI;
typedef union PIPE2_PG_STATUS__VI              regPIPE2_PG_STATUS__VI;
typedef union PIPE3_DMIF_BUFFER_CONTROL__VI    regPIPE3_DMIF_BUFFER_CONTROL__VI;
typedef union PIPE3_MAX_REQUESTS__VI           regPIPE3_MAX_REQUESTS__VI;
typedef union PIPE3_PG_CONFIG__VI              regPIPE3_PG_CONFIG__VI;
typedef union PIPE3_PG_ENABLE__VI              regPIPE3_PG_ENABLE__VI;
typedef union PIPE3_PG_STATUS__VI              regPIPE3_PG_STATUS__VI;
typedef union PIPE4_DMIF_BUFFER_CONTROL__VI    regPIPE4_DMIF_BUFFER_CONTROL__VI;
typedef union PIPE4_MAX_REQUESTS__VI           regPIPE4_MAX_REQUESTS__VI;
typedef union PIPE4_PG_CONFIG__VI              regPIPE4_PG_CONFIG__VI;
typedef union PIPE4_PG_ENABLE__VI              regPIPE4_PG_ENABLE__VI;
typedef union PIPE4_PG_STATUS__VI              regPIPE4_PG_STATUS__VI;
typedef union PIPE5_DMIF_BUFFER_CONTROL__VI    regPIPE5_DMIF_BUFFER_CONTROL__VI;
typedef union PIPE5_MAX_REQUESTS__VI           regPIPE5_MAX_REQUESTS__VI;
typedef union PIPE5_PG_CONFIG__VI              regPIPE5_PG_CONFIG__VI;
typedef union PIPE5_PG_ENABLE__VI              regPIPE5_PG_ENABLE__VI;
typedef union PIPE5_PG_STATUS__VI              regPIPE5_PG_STATUS__VI;
typedef union PIPE6_ARBITRATION_CONTROL3__VI   regPIPE6_ARBITRATION_CONTROL3__VI;
typedef union PIPE6_MAX_REQUESTS__VI           regPIPE6_MAX_REQUESTS__VI;
typedef union PIPE7_ARBITRATION_CONTROL3__VI   regPIPE7_ARBITRATION_CONTROL3__VI;
typedef union PIPE7_MAX_REQUESTS__VI           regPIPE7_MAX_REQUESTS__VI;
typedef union PIXCLK0_RESYNC_CNTL__VI          regPIXCLK0_RESYNC_CNTL__VI;
typedef union PLL_ANALOG__VI                   regPLL_ANALOG__VI;
typedef union PLL_ANALOG_CNTL__VI              regPLL_ANALOG_CNTL__VI;
typedef union PLL_CNTL__VI                     regPLL_CNTL__VI;
typedef union PLL_DEBUG_CNTL__VI               regPLL_DEBUG_CNTL__VI;
typedef union PLL_DS_CNTL__VI                  regPLL_DS_CNTL__VI;
typedef union PLL_FB_DIV__VI                   regPLL_FB_DIV__VI;
typedef union PLL_IDCLK_CNTL__VI               regPLL_IDCLK_CNTL__VI;
typedef union PLL_MACRO_CNTL_RESERVED0__VI     regPLL_MACRO_CNTL_RESERVED0__VI;
typedef union PLL_MACRO_CNTL_RESERVED1__VI     regPLL_MACRO_CNTL_RESERVED1__VI;
typedef union PLL_MACRO_CNTL_RESERVED10__VI    regPLL_MACRO_CNTL_RESERVED10__VI;
typedef union PLL_MACRO_CNTL_RESERVED11__VI    regPLL_MACRO_CNTL_RESERVED11__VI;
typedef union PLL_MACRO_CNTL_RESERVED12__VI    regPLL_MACRO_CNTL_RESERVED12__VI;
typedef union PLL_MACRO_CNTL_RESERVED13__VI    regPLL_MACRO_CNTL_RESERVED13__VI;
typedef union PLL_MACRO_CNTL_RESERVED14__VI    regPLL_MACRO_CNTL_RESERVED14__VI;
typedef union PLL_MACRO_CNTL_RESERVED15__VI    regPLL_MACRO_CNTL_RESERVED15__VI;
typedef union PLL_MACRO_CNTL_RESERVED16__VI    regPLL_MACRO_CNTL_RESERVED16__VI;
typedef union PLL_MACRO_CNTL_RESERVED17__VI    regPLL_MACRO_CNTL_RESERVED17__VI;
typedef union PLL_MACRO_CNTL_RESERVED18__VI    regPLL_MACRO_CNTL_RESERVED18__VI;
typedef union PLL_MACRO_CNTL_RESERVED19__VI    regPLL_MACRO_CNTL_RESERVED19__VI;
typedef union PLL_MACRO_CNTL_RESERVED2__VI     regPLL_MACRO_CNTL_RESERVED2__VI;
typedef union PLL_MACRO_CNTL_RESERVED20__VI    regPLL_MACRO_CNTL_RESERVED20__VI;
typedef union PLL_MACRO_CNTL_RESERVED21__VI    regPLL_MACRO_CNTL_RESERVED21__VI;
typedef union PLL_MACRO_CNTL_RESERVED22__VI    regPLL_MACRO_CNTL_RESERVED22__VI;
typedef union PLL_MACRO_CNTL_RESERVED23__VI    regPLL_MACRO_CNTL_RESERVED23__VI;
typedef union PLL_MACRO_CNTL_RESERVED24__VI    regPLL_MACRO_CNTL_RESERVED24__VI;
typedef union PLL_MACRO_CNTL_RESERVED25__VI    regPLL_MACRO_CNTL_RESERVED25__VI;
typedef union PLL_MACRO_CNTL_RESERVED26__VI    regPLL_MACRO_CNTL_RESERVED26__VI;
typedef union PLL_MACRO_CNTL_RESERVED27__VI    regPLL_MACRO_CNTL_RESERVED27__VI;
typedef union PLL_MACRO_CNTL_RESERVED28__VI    regPLL_MACRO_CNTL_RESERVED28__VI;
typedef union PLL_MACRO_CNTL_RESERVED29__VI    regPLL_MACRO_CNTL_RESERVED29__VI;
typedef union PLL_MACRO_CNTL_RESERVED3__VI     regPLL_MACRO_CNTL_RESERVED3__VI;
typedef union PLL_MACRO_CNTL_RESERVED30__VI    regPLL_MACRO_CNTL_RESERVED30__VI;
typedef union PLL_MACRO_CNTL_RESERVED31__VI    regPLL_MACRO_CNTL_RESERVED31__VI;
typedef union PLL_MACRO_CNTL_RESERVED32__VI    regPLL_MACRO_CNTL_RESERVED32__VI;
typedef union PLL_MACRO_CNTL_RESERVED33__VI    regPLL_MACRO_CNTL_RESERVED33__VI;
typedef union PLL_MACRO_CNTL_RESERVED34__VI    regPLL_MACRO_CNTL_RESERVED34__VI;
typedef union PLL_MACRO_CNTL_RESERVED35__VI    regPLL_MACRO_CNTL_RESERVED35__VI;
typedef union PLL_MACRO_CNTL_RESERVED36__VI    regPLL_MACRO_CNTL_RESERVED36__VI;
typedef union PLL_MACRO_CNTL_RESERVED37__VI    regPLL_MACRO_CNTL_RESERVED37__VI;
typedef union PLL_MACRO_CNTL_RESERVED38__VI    regPLL_MACRO_CNTL_RESERVED38__VI;
typedef union PLL_MACRO_CNTL_RESERVED39__VI    regPLL_MACRO_CNTL_RESERVED39__VI;
typedef union PLL_MACRO_CNTL_RESERVED4__VI     regPLL_MACRO_CNTL_RESERVED4__VI;
typedef union PLL_MACRO_CNTL_RESERVED40__VI    regPLL_MACRO_CNTL_RESERVED40__VI;
typedef union PLL_MACRO_CNTL_RESERVED41__VI    regPLL_MACRO_CNTL_RESERVED41__VI;
typedef union PLL_MACRO_CNTL_RESERVED5__VI     regPLL_MACRO_CNTL_RESERVED5__VI;
typedef union PLL_MACRO_CNTL_RESERVED6__VI     regPLL_MACRO_CNTL_RESERVED6__VI;
typedef union PLL_MACRO_CNTL_RESERVED7__VI     regPLL_MACRO_CNTL_RESERVED7__VI;
typedef union PLL_MACRO_CNTL_RESERVED8__VI     regPLL_MACRO_CNTL_RESERVED8__VI;
typedef union PLL_MACRO_CNTL_RESERVED9__VI     regPLL_MACRO_CNTL_RESERVED9__VI;
typedef union PLL_POST_DIV__VI                 regPLL_POST_DIV__VI;
typedef union PLL_REF_DIV__VI                  regPLL_REF_DIV__VI;
typedef union PLL_SS_AMOUNT_DSFRAC__VI         regPLL_SS_AMOUNT_DSFRAC__VI;
typedef union PLL_SS_CNTL__VI                  regPLL_SS_CNTL__VI;
typedef union PLL_UNLOCK_DETECT_CNTL__VI       regPLL_UNLOCK_DETECT_CNTL__VI;
typedef union PLL_UPDATE_CNTL__VI              regPLL_UPDATE_CNTL__VI;
typedef union PLL_UPDATE_LOCK__VI              regPLL_UPDATE_LOCK__VI;
typedef union PLL_VREG_CNTL__VI                regPLL_VREG_CNTL__VI;
typedef union PLL_XOR_LOCK__VI                 regPLL_XOR_LOCK__VI;
typedef union PM_FUSES_1__VI                   regPM_FUSES_1__VI;
typedef union PM_FUSES_10__VI                  regPM_FUSES_10__VI;
typedef union PM_FUSES_11__VI                  regPM_FUSES_11__VI;
typedef union PM_FUSES_12__VI                  regPM_FUSES_12__VI;
typedef union PM_FUSES_13__VI                  regPM_FUSES_13__VI;
typedef union PM_FUSES_14__VI                  regPM_FUSES_14__VI;
typedef union PM_FUSES_15__VI                  regPM_FUSES_15__VI;
typedef union PM_FUSES_2__VI                   regPM_FUSES_2__VI;
typedef union PM_FUSES_3__VI                   regPM_FUSES_3__VI;
typedef union PM_FUSES_4__VI                   regPM_FUSES_4__VI;
typedef union PM_FUSES_5__VI                   regPM_FUSES_5__VI;
typedef union PM_FUSES_6__VI                   regPM_FUSES_6__VI;
typedef union PM_FUSES_7__VI                   regPM_FUSES_7__VI;
typedef union PM_FUSES_8__VI                   regPM_FUSES_8__VI;
typedef union PM_FUSES_9__VI                   regPM_FUSES_9__VI;
typedef union PPLL_DEBUG_MUX_CNTL__VI          regPPLL_DEBUG_MUX_CNTL__VI;
typedef union PPLL_DIV_UPDATE_DEBUG__VI        regPPLL_DIV_UPDATE_DEBUG__VI;
typedef union PPLL_SPARE0__VI                  regPPLL_SPARE0__VI;
typedef union PPLL_SPARE1__VI                  regPPLL_SPARE1__VI;
typedef union PPLL_STATUS_DEBUG__VI            regPPLL_STATUS_DEBUG__VI;
typedef union PRESCALE_CONTROL__VI             regPRESCALE_CONTROL__VI;
typedef union PRESCALE_GRPH_CONTROL__VI        regPRESCALE_GRPH_CONTROL__VI;
typedef union PRESCALE_OVL_CONTROL__VI         regPRESCALE_OVL_CONTROL__VI;
typedef union PRESCALE_VALUES_B__VI            regPRESCALE_VALUES_B__VI;
typedef union PRESCALE_VALUES_G__VI            regPRESCALE_VALUES_G__VI;
typedef union PRESCALE_VALUES_GRPH_B__VI       regPRESCALE_VALUES_GRPH_B__VI;
typedef union PRESCALE_VALUES_GRPH_G__VI       regPRESCALE_VALUES_GRPH_G__VI;
typedef union PRESCALE_VALUES_GRPH_R__VI       regPRESCALE_VALUES_GRPH_R__VI;
typedef union PRESCALE_VALUES_OVL_CB__VI       regPRESCALE_VALUES_OVL_CB__VI;
typedef union PRESCALE_VALUES_OVL_CR__VI       regPRESCALE_VALUES_OVL_CR__VI;
typedef union PRESCALE_VALUES_OVL_Y__VI        regPRESCALE_VALUES_OVL_Y__VI;
typedef union PRESCALE_VALUES_R__VI            regPRESCALE_VALUES_R__VI;
typedef union PWR_AVFS0_CNTL_STATUS__VI        regPWR_AVFS0_CNTL_STATUS__VI;
typedef union PWR_AVFS10_CNTL_STATUS__VI       regPWR_AVFS10_CNTL_STATUS__VI;
typedef union PWR_AVFS11_CNTL_STATUS__VI       regPWR_AVFS11_CNTL_STATUS__VI;
typedef union PWR_AVFS12_CNTL_STATUS__VI       regPWR_AVFS12_CNTL_STATUS__VI;
typedef union PWR_AVFS13_CNTL_STATUS__VI       regPWR_AVFS13_CNTL_STATUS__VI;
typedef union PWR_AVFS14_CNTL_STATUS__VI       regPWR_AVFS14_CNTL_STATUS__VI;
typedef union PWR_AVFS15_CNTL_STATUS__VI       regPWR_AVFS15_CNTL_STATUS__VI;
typedef union PWR_AVFS16_CNTL_STATUS__VI       regPWR_AVFS16_CNTL_STATUS__VI;
typedef union PWR_AVFS17_CNTL_STATUS__VI       regPWR_AVFS17_CNTL_STATUS__VI;
typedef union PWR_AVFS18_CNTL_STATUS__VI       regPWR_AVFS18_CNTL_STATUS__VI;
typedef union PWR_AVFS19_CNTL_STATUS__VI       regPWR_AVFS19_CNTL_STATUS__VI;
typedef union PWR_AVFS1_CNTL_STATUS__VI        regPWR_AVFS1_CNTL_STATUS__VI;
typedef union PWR_AVFS20_CNTL_STATUS__VI       regPWR_AVFS20_CNTL_STATUS__VI;
typedef union PWR_AVFS21_CNTL_STATUS__VI       regPWR_AVFS21_CNTL_STATUS__VI;
typedef union PWR_AVFS22_CNTL_STATUS__VI       regPWR_AVFS22_CNTL_STATUS__VI;
typedef union PWR_AVFS23_CNTL_STATUS__VI       regPWR_AVFS23_CNTL_STATUS__VI;
typedef union PWR_AVFS24_CNTL_STATUS__VI       regPWR_AVFS24_CNTL_STATUS__VI;
typedef union PWR_AVFS25_CNTL_STATUS__VI       regPWR_AVFS25_CNTL_STATUS__VI;
typedef union PWR_AVFS26_CNTL_STATUS__VI       regPWR_AVFS26_CNTL_STATUS__VI;
typedef union PWR_AVFS27_CNTL_STATUS__VI       regPWR_AVFS27_CNTL_STATUS__VI;
typedef union PWR_AVFS2_CNTL_STATUS__VI        regPWR_AVFS2_CNTL_STATUS__VI;
typedef union PWR_AVFS3_CNTL_STATUS__VI        regPWR_AVFS3_CNTL_STATUS__VI;
typedef union PWR_AVFS4_CNTL_STATUS__VI        regPWR_AVFS4_CNTL_STATUS__VI;
typedef union PWR_AVFS5_CNTL_STATUS__VI        regPWR_AVFS5_CNTL_STATUS__VI;
typedef union PWR_AVFS6_CNTL_STATUS__VI        regPWR_AVFS6_CNTL_STATUS__VI;
typedef union PWR_AVFS7_CNTL_STATUS__VI        regPWR_AVFS7_CNTL_STATUS__VI;
typedef union PWR_AVFS8_CNTL_STATUS__VI        regPWR_AVFS8_CNTL_STATUS__VI;
typedef union PWR_AVFS9_CNTL_STATUS__VI        regPWR_AVFS9_CNTL_STATUS__VI;
typedef union PWR_AVFS_CNTL__VI                regPWR_AVFS_CNTL__VI;
typedef union PWR_AVFS_SEL__VI                 regPWR_AVFS_SEL__VI;
typedef union PWR_CKS_CNTL__VI                 regPWR_CKS_CNTL__VI;
typedef union PWR_CKS_ENABLE__VI               regPWR_CKS_ENABLE__VI;
typedef union PWR_DISP_TIMER2_CONTROL__VI      regPWR_DISP_TIMER2_CONTROL__VI;
typedef union PWR_DISP_TIMER2_DEBUG__VI        regPWR_DISP_TIMER2_DEBUG__VI;
typedef union PWR_DISP_TIMER_CONTROL__VI       regPWR_DISP_TIMER_CONTROL__VI;
typedef union PWR_DISP_TIMER_CONTROL2__VI      regPWR_DISP_TIMER_CONTROL2__VI;
typedef union PWR_DISP_TIMER_DEBUG__VI         regPWR_DISP_TIMER_DEBUG__VI;
typedef union PWR_PCC_CONTROL__VI              regPWR_PCC_CONTROL__VI;
typedef union PWR_PCC_GPIO_SELECT__VI          regPWR_PCC_GPIO_SELECT__VI;
typedef union RAS_TA_SIGNATURE1__VI            regRAS_TA_SIGNATURE1__VI;
typedef union RBBMIF_STATUS__VI                regRBBMIF_STATUS__VI;
typedef union RBBMIF_STATUS_FLAG__VI           regRBBMIF_STATUS_FLAG__VI;
typedef union RBBMIF_TIMEOUT__VI               regRBBMIF_TIMEOUT__VI;
typedef union RBBMIF_TIMEOUT_DIS__VI           regRBBMIF_TIMEOUT_DIS__VI;
typedef union RCU_VIRT_RESET_REQ__VI           regRCU_VIRT_RESET_REQ__VI;
typedef union REFCLK_CGTT_BLK_CTRL_REG__VI     regREFCLK_CGTT_BLK_CTRL_REG__VI;
typedef union REFCLK_CNTL__VI                  regREFCLK_CNTL__VI;
typedef union REGAMMA_CNTLA_END_CNTL1__VI      regREGAMMA_CNTLA_END_CNTL1__VI;
typedef union REGAMMA_CNTLA_END_CNTL2__VI      regREGAMMA_CNTLA_END_CNTL2__VI;
typedef union REGAMMA_CNTLA_REGION_0_1__VI     regREGAMMA_CNTLA_REGION_0_1__VI;
typedef union REGAMMA_CNTLA_REGION_10_11__VI   regREGAMMA_CNTLA_REGION_10_11__VI;
typedef union REGAMMA_CNTLA_REGION_12_13__VI   regREGAMMA_CNTLA_REGION_12_13__VI;
typedef union REGAMMA_CNTLA_REGION_14_15__VI   regREGAMMA_CNTLA_REGION_14_15__VI;
typedef union REGAMMA_CNTLA_REGION_2_3__VI     regREGAMMA_CNTLA_REGION_2_3__VI;
typedef union REGAMMA_CNTLA_REGION_4_5__VI     regREGAMMA_CNTLA_REGION_4_5__VI;
typedef union REGAMMA_CNTLA_REGION_6_7__VI     regREGAMMA_CNTLA_REGION_6_7__VI;
typedef union REGAMMA_CNTLA_REGION_8_9__VI     regREGAMMA_CNTLA_REGION_8_9__VI;
typedef union REGAMMA_CNTLA_SLOPE_CNTL__VI     regREGAMMA_CNTLA_SLOPE_CNTL__VI;
typedef union REGAMMA_CNTLA_START_CNTL__VI     regREGAMMA_CNTLA_START_CNTL__VI;
typedef union REGAMMA_CNTLB_END_CNTL1__VI      regREGAMMA_CNTLB_END_CNTL1__VI;
typedef union REGAMMA_CNTLB_END_CNTL2__VI      regREGAMMA_CNTLB_END_CNTL2__VI;
typedef union REGAMMA_CNTLB_REGION_0_1__VI     regREGAMMA_CNTLB_REGION_0_1__VI;
typedef union REGAMMA_CNTLB_REGION_10_11__VI   regREGAMMA_CNTLB_REGION_10_11__VI;
typedef union REGAMMA_CNTLB_REGION_12_13__VI   regREGAMMA_CNTLB_REGION_12_13__VI;
typedef union REGAMMA_CNTLB_REGION_14_15__VI   regREGAMMA_CNTLB_REGION_14_15__VI;
typedef union REGAMMA_CNTLB_REGION_2_3__VI     regREGAMMA_CNTLB_REGION_2_3__VI;
typedef union REGAMMA_CNTLB_REGION_4_5__VI     regREGAMMA_CNTLB_REGION_4_5__VI;
typedef union REGAMMA_CNTLB_REGION_6_7__VI     regREGAMMA_CNTLB_REGION_6_7__VI;
typedef union REGAMMA_CNTLB_REGION_8_9__VI     regREGAMMA_CNTLB_REGION_8_9__VI;
typedef union REGAMMA_CNTLB_SLOPE_CNTL__VI     regREGAMMA_CNTLB_SLOPE_CNTL__VI;
typedef union REGAMMA_CNTLB_START_CNTL__VI     regREGAMMA_CNTLB_START_CNTL__VI;
typedef union REGAMMA_CONTROL__VI              regREGAMMA_CONTROL__VI;
typedef union REGAMMA_LUT_DATA__VI             regREGAMMA_LUT_DATA__VI;
typedef union REGAMMA_LUT_INDEX__VI            regREGAMMA_LUT_INDEX__VI;
typedef union REGAMMA_LUT_WRITE_EN_MASK__VI    regREGAMMA_LUT_WRITE_EN_MASK__VI;
typedef union REG_ADAPT_pciecore0_CONTROL__VI  regREG_ADAPT_pciecore0_CONTROL__VI;
typedef union REG_ADAPT_pif0_CONTROL__VI       regREG_ADAPT_pif0_CONTROL__VI;
typedef union REG_ADAPT_pwregr_CONTROL__VI     regREG_ADAPT_pwregr_CONTROL__VI;
typedef union REG_ADAPT_pwregt_CONTROL__VI     regREG_ADAPT_pwregt_CONTROL__VI;
typedef union REMAP_HDP_MEM_FLUSH_CNTL__VI     regREMAP_HDP_MEM_FLUSH_CNTL__VI;
typedef union REMAP_HDP_REG_FLUSH_CNTL__VI     regREMAP_HDP_REG_FLUSH_CNTL__VI;
typedef union RLC_CP_RESPONSE0__VI             regRLC_CP_RESPONSE0__VI;
typedef union RLC_CP_RESPONSE1__VI             regRLC_CP_RESPONSE1__VI;
typedef union RLC_CP_RESPONSE2__VI             regRLC_CP_RESPONSE2__VI;
typedef union RLC_CP_RESPONSE3__VI             regRLC_CP_RESPONSE3__VI;
typedef union RLC_CP_SCHEDULERS__VI            regRLC_CP_SCHEDULERS__VI;
typedef union RLC_CSIB_ADDR_HI__VI             regRLC_CSIB_ADDR_HI__VI;
typedef union RLC_CSIB_ADDR_LO__VI             regRLC_CSIB_ADDR_LO__VI;
typedef union RLC_CSIB_LENGTH__VI              regRLC_CSIB_LENGTH__VI;
typedef union RLC_GPM_INT_DISABLE_TH0__VI      regRLC_GPM_INT_DISABLE_TH0__VI;
typedef union RLC_GPM_INT_DISABLE_TH1__VI      regRLC_GPM_INT_DISABLE_TH1__VI;
typedef union RLC_GPM_INT_FORCE_TH0__VI        regRLC_GPM_INT_FORCE_TH0__VI;
typedef union RLC_GPM_INT_FORCE_TH1__VI        regRLC_GPM_INT_FORCE_TH1__VI;
typedef union RLC_GPM_THREAD_RESET__VI         regRLC_GPM_THREAD_RESET__VI;
typedef union RLC_GPM_VMID_THREAD2__VI         regRLC_GPM_VMID_THREAD2__VI;
typedef union RLC_GPU_IOV_ACTIVE_FCN_ID__VI    regRLC_GPU_IOV_ACTIVE_FCN_ID__VI;
typedef union RLC_GPU_IOV_CFG_REG1__VI         regRLC_GPU_IOV_CFG_REG1__VI;
typedef union RLC_GPU_IOV_CFG_REG10__VI        regRLC_GPU_IOV_CFG_REG10__VI;
typedef union RLC_GPU_IOV_CFG_REG11__VI        regRLC_GPU_IOV_CFG_REG11__VI;
typedef union RLC_GPU_IOV_CFG_REG12__VI        regRLC_GPU_IOV_CFG_REG12__VI;
typedef union RLC_GPU_IOV_CFG_REG13__VI        regRLC_GPU_IOV_CFG_REG13__VI;
typedef union RLC_GPU_IOV_CFG_REG14__VI        regRLC_GPU_IOV_CFG_REG14__VI;
typedef union RLC_GPU_IOV_CFG_REG15__VI        regRLC_GPU_IOV_CFG_REG15__VI;
typedef union RLC_GPU_IOV_CFG_REG2__VI         regRLC_GPU_IOV_CFG_REG2__VI;
typedef union RLC_GPU_IOV_CFG_REG6__VI         regRLC_GPU_IOV_CFG_REG6__VI;
typedef union RLC_GPU_IOV_CFG_REG8__VI         regRLC_GPU_IOV_CFG_REG8__VI;
typedef union RLC_GPU_IOV_CFG_REG9__VI         regRLC_GPU_IOV_CFG_REG9__VI;
typedef union RLC_GPU_IOV_F32_CNTL__VI         regRLC_GPU_IOV_F32_CNTL__VI;
typedef union RLC_GPU_IOV_F32_RESET__VI        regRLC_GPU_IOV_F32_RESET__VI;
typedef union RLC_GPU_IOV_INT_DISABLE__VI      regRLC_GPU_IOV_INT_DISABLE__VI;
typedef union RLC_GPU_IOV_INT_FORCE__VI        regRLC_GPU_IOV_INT_FORCE__VI;
typedef union RLC_GPU_IOV_RLC_RESPONSE__VI     regRLC_GPU_IOV_RLC_RESPONSE__VI;
typedef union RLC_GPU_IOV_SCH_0__VI            regRLC_GPU_IOV_SCH_0__VI;
typedef union RLC_GPU_IOV_SCH_1__VI            regRLC_GPU_IOV_SCH_1__VI;
typedef union RLC_GPU_IOV_SCH_2__VI            regRLC_GPU_IOV_SCH_2__VI;
typedef union RLC_GPU_IOV_SCH_3__VI            regRLC_GPU_IOV_SCH_3__VI;
typedef union RLC_GPU_IOV_SCH_INT__VI          regRLC_GPU_IOV_SCH_INT__VI;
typedef union RLC_GPU_IOV_SCRATCH_ADDR__VI     regRLC_GPU_IOV_SCRATCH_ADDR__VI;
typedef union RLC_GPU_IOV_SCRATCH_DATA__VI     regRLC_GPU_IOV_SCRATCH_DATA__VI;
typedef union RLC_GPU_IOV_SDMA0_BUSY_STATUS__VI regRLC_GPU_IOV_SDMA0_BUSY_STATUS__VI;
typedef union RLC_GPU_IOV_SDMA0_STATUS__VI     regRLC_GPU_IOV_SDMA0_STATUS__VI;
typedef union RLC_GPU_IOV_SDMA1_BUSY_STATUS__VI regRLC_GPU_IOV_SDMA1_BUSY_STATUS__VI;
typedef union RLC_GPU_IOV_SDMA1_STATUS__VI     regRLC_GPU_IOV_SDMA1_STATUS__VI;
typedef union RLC_GPU_IOV_SMU_RESPONSE__VI     regRLC_GPU_IOV_SMU_RESPONSE__VI;
typedef union RLC_GPU_IOV_UCODE_ADDR__VI       regRLC_GPU_IOV_UCODE_ADDR__VI;
typedef union RLC_GPU_IOV_UCODE_DATA__VI       regRLC_GPU_IOV_UCODE_DATA__VI;
typedef union RLC_GPU_IOV_VF_ENABLE__VI        regRLC_GPU_IOV_VF_ENABLE__VI;
typedef union RLC_GPU_IOV_VIRT_RESET_REQ__VI   regRLC_GPU_IOV_VIRT_RESET_REQ__VI;
typedef union RLC_HYP_GPM_UCODE_ADDR__VI       regRLC_HYP_GPM_UCODE_ADDR__VI;
typedef union RLC_HYP_GPM_UCODE_DATA__VI       regRLC_HYP_GPM_UCODE_DATA__VI;
typedef union RLC_MGCG_CTRL__VI                regRLC_MGCG_CTRL__VI;
typedef union RLC_PERFMON_CLK_CNTL__VI         regRLC_PERFMON_CLK_CNTL__VI;
typedef union RLC_PG_DELAY_3__VI               regRLC_PG_DELAY_3__VI;
typedef union RLC_RLCV_COMMAND__VI             regRLC_RLCV_COMMAND__VI;
typedef union RLC_RLCV_SAFE_MODE__VI           regRLC_RLCV_SAFE_MODE__VI;
typedef union RLC_ROM_CNTL__VI                 regRLC_ROM_CNTL__VI;
typedef union RLC_SMU_COMMAND__VI              regRLC_SMU_COMMAND__VI;
typedef union RLC_SMU_MESSAGE__VI              regRLC_SMU_MESSAGE__VI;
typedef union RLC_SMU_SAFE_MODE__VI            regRLC_SMU_SAFE_MODE__VI;
typedef union RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__VI regRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__VI;
typedef union RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__VI regRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__VI;
typedef union RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__VI regRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__VI;
typedef union RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__VI regRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__VI;
typedef union RLC_SRM_ARAM_ADDR__VI            regRLC_SRM_ARAM_ADDR__VI;
typedef union RLC_SRM_ARAM_DATA__VI            regRLC_SRM_ARAM_DATA__VI;
typedef union RLC_SRM_CNTL__VI                 regRLC_SRM_CNTL__VI;
typedef union RLC_SRM_DEBUG__VI                regRLC_SRM_DEBUG__VI;
typedef union RLC_SRM_DEBUG_SELECT__VI         regRLC_SRM_DEBUG_SELECT__VI;
typedef union RLC_SRM_DRAM_ADDR__VI            regRLC_SRM_DRAM_ADDR__VI;
typedef union RLC_SRM_DRAM_DATA__VI            regRLC_SRM_DRAM_DATA__VI;
typedef union RLC_SRM_GPM_ABORT__VI            regRLC_SRM_GPM_ABORT__VI;
typedef union RLC_SRM_GPM_COMMAND__VI          regRLC_SRM_GPM_COMMAND__VI;
typedef union RLC_SRM_GPM_COMMAND_STATUS__VI   regRLC_SRM_GPM_COMMAND_STATUS__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_0__VI    regRLC_SRM_INDEX_CNTL_ADDR_0__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_1__VI    regRLC_SRM_INDEX_CNTL_ADDR_1__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_2__VI    regRLC_SRM_INDEX_CNTL_ADDR_2__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_3__VI    regRLC_SRM_INDEX_CNTL_ADDR_3__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_4__VI    regRLC_SRM_INDEX_CNTL_ADDR_4__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_5__VI    regRLC_SRM_INDEX_CNTL_ADDR_5__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_6__VI    regRLC_SRM_INDEX_CNTL_ADDR_6__VI;
typedef union RLC_SRM_INDEX_CNTL_ADDR_7__VI    regRLC_SRM_INDEX_CNTL_ADDR_7__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_0__VI    regRLC_SRM_INDEX_CNTL_DATA_0__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_1__VI    regRLC_SRM_INDEX_CNTL_DATA_1__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_2__VI    regRLC_SRM_INDEX_CNTL_DATA_2__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_3__VI    regRLC_SRM_INDEX_CNTL_DATA_3__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_4__VI    regRLC_SRM_INDEX_CNTL_DATA_4__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_5__VI    regRLC_SRM_INDEX_CNTL_DATA_5__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_6__VI    regRLC_SRM_INDEX_CNTL_DATA_6__VI;
typedef union RLC_SRM_INDEX_CNTL_DATA_7__VI    regRLC_SRM_INDEX_CNTL_DATA_7__VI;
typedef union RLC_SRM_RLCV_COMMAND__VI         regRLC_SRM_RLCV_COMMAND__VI;
typedef union RLC_SRM_RLCV_COMMAND_STATUS__VI  regRLC_SRM_RLCV_COMMAND_STATUS__VI;
typedef union RLC_SRM_STAT__VI                 regRLC_SRM_STAT__VI;
typedef union SAM_IH_EXT_ERR_INTR__VI          regSAM_IH_EXT_ERR_INTR__VI;
typedef union SAM_IH_EXT_ERR_INTR_STATUS__VI   regSAM_IH_EXT_ERR_INTR_STATUS__VI;
typedef union SCLV_ALU_CONTROL__VI             regSCLV_ALU_CONTROL__VI;
typedef union SCLV_AUTOMATIC_MODE_CONTROL__VI  regSCLV_AUTOMATIC_MODE_CONTROL__VI;
typedef union SCLV_COEF_RAM_SELECT__VI         regSCLV_COEF_RAM_SELECT__VI;
typedef union SCLV_COEF_RAM_TAP_DATA__VI       regSCLV_COEF_RAM_TAP_DATA__VI;
typedef union SCLV_CONTROL__VI                 regSCLV_CONTROL__VI;
typedef union SCLV_DEBUG__VI                   regSCLV_DEBUG__VI;
typedef union SCLV_DEBUG2__VI                  regSCLV_DEBUG2__VI;
typedef union SCLV_EXT_OVERSCAN_LEFT_RIGHT__VI regSCLV_EXT_OVERSCAN_LEFT_RIGHT__VI;
typedef union SCLV_EXT_OVERSCAN_TOP_BOTTOM__VI regSCLV_EXT_OVERSCAN_TOP_BOTTOM__VI;
typedef union SCLV_HORZ_FILTER_CONTROL__VI     regSCLV_HORZ_FILTER_CONTROL__VI;
typedef union SCLV_HORZ_FILTER_INIT__VI        regSCLV_HORZ_FILTER_INIT__VI;
typedef union SCLV_HORZ_FILTER_INIT_C__VI      regSCLV_HORZ_FILTER_INIT_C__VI;
typedef union SCLV_HORZ_FILTER_SCALE_RATIO__VI regSCLV_HORZ_FILTER_SCALE_RATIO__VI;
typedef union SCLV_HORZ_FILTER_SCALE_RATIO_C__VI regSCLV_HORZ_FILTER_SCALE_RATIO_C__VI;
typedef union SCLV_MANUAL_REPLICATE_CONTROL__VI regSCLV_MANUAL_REPLICATE_CONTROL__VI;
typedef union SCLV_MODE__VI                    regSCLV_MODE__VI;
typedef union SCLV_MODE_CHANGE_DET1__VI        regSCLV_MODE_CHANGE_DET1__VI;
typedef union SCLV_MODE_CHANGE_DET2__VI        regSCLV_MODE_CHANGE_DET2__VI;
typedef union SCLV_MODE_CHANGE_DET3__VI        regSCLV_MODE_CHANGE_DET3__VI;
typedef union SCLV_MODE_CHANGE_MASK__VI        regSCLV_MODE_CHANGE_MASK__VI;
typedef union SCLV_ROUND_OFFSET__VI            regSCLV_ROUND_OFFSET__VI;
typedef union SCLV_TAP_CONTROL__VI             regSCLV_TAP_CONTROL__VI;
typedef union SCLV_TEST_DEBUG_DATA__VI         regSCLV_TEST_DEBUG_DATA__VI;
typedef union SCLV_TEST_DEBUG_INDEX__VI        regSCLV_TEST_DEBUG_INDEX__VI;
typedef union SCLV_UPDATE__VI                  regSCLV_UPDATE__VI;
typedef union SCLV_VERT_FILTER_CONTROL__VI     regSCLV_VERT_FILTER_CONTROL__VI;
typedef union SCLV_VERT_FILTER_INIT__VI        regSCLV_VERT_FILTER_INIT__VI;
typedef union SCLV_VERT_FILTER_INIT_BOT__VI    regSCLV_VERT_FILTER_INIT_BOT__VI;
typedef union SCLV_VERT_FILTER_INIT_BOT_C__VI  regSCLV_VERT_FILTER_INIT_BOT_C__VI;
typedef union SCLV_VERT_FILTER_INIT_C__VI      regSCLV_VERT_FILTER_INIT_C__VI;
typedef union SCLV_VERT_FILTER_SCALE_RATIO__VI regSCLV_VERT_FILTER_SCALE_RATIO__VI;
typedef union SCLV_VERT_FILTER_SCALE_RATIO_C__VI regSCLV_VERT_FILTER_SCALE_RATIO_C__VI;
typedef union SCLV_VIEWPORT_SIZE__VI           regSCLV_VIEWPORT_SIZE__VI;
typedef union SCLV_VIEWPORT_SIZE_C__VI         regSCLV_VIEWPORT_SIZE_C__VI;
typedef union SCLV_VIEWPORT_START__VI          regSCLV_VIEWPORT_START__VI;
typedef union SCLV_VIEWPORT_START_C__VI        regSCLV_VIEWPORT_START_C__VI;
typedef union SCLV_VIEWPORT_START_SECONDARY__VI regSCLV_VIEWPORT_START_SECONDARY__VI;
typedef union SCLV_VIEWPORT_START_SECONDARY_C__VI regSCLV_VIEWPORT_START_SECONDARY_C__VI;
typedef union SCL_DEBUG2__VI                   regSCL_DEBUG2__VI;
typedef union SCL_HORZ_FILTER_INIT__VI         regSCL_HORZ_FILTER_INIT__VI;
typedef union SCL_MODE__VI                     regSCL_MODE__VI;
typedef union SCL_ROUND_OFFSET__VI             regSCL_ROUND_OFFSET__VI;
typedef union SDMA0_ACTIVE_FCN_ID__VI          regSDMA0_ACTIVE_FCN_ID__VI;
typedef union SDMA0_ATOMIC_CNTL__VI            regSDMA0_ATOMIC_CNTL__VI;
typedef union SDMA0_ATOMIC_PREOP_HI__VI        regSDMA0_ATOMIC_PREOP_HI__VI;
typedef union SDMA0_ATOMIC_PREOP_LO__VI        regSDMA0_ATOMIC_PREOP_LO__VI;
typedef union SDMA0_BA_THRESHOLD__VI           regSDMA0_BA_THRESHOLD__VI;
typedef union SDMA0_CONTEXT_REG_TYPE0__VI      regSDMA0_CONTEXT_REG_TYPE0__VI;
typedef union SDMA0_CONTEXT_REG_TYPE1__VI      regSDMA0_CONTEXT_REG_TYPE1__VI;
typedef union SDMA0_CONTEXT_REG_TYPE2__VI      regSDMA0_CONTEXT_REG_TYPE2__VI;
typedef union SDMA0_EDC_CONFIG__VI             regSDMA0_EDC_CONFIG__VI;
typedef union SDMA0_GFX_CSA_ADDR_HI__VI        regSDMA0_GFX_CSA_ADDR_HI__VI;
typedef union SDMA0_GFX_CSA_ADDR_LO__VI        regSDMA0_GFX_CSA_ADDR_LO__VI;
typedef union SDMA0_GFX_DOORBELL__VI           regSDMA0_GFX_DOORBELL__VI;
typedef union SDMA0_GFX_DOORBELL_LOG__VI       regSDMA0_GFX_DOORBELL_LOG__VI;
typedef union SDMA0_GFX_DUMMY_REG__VI          regSDMA0_GFX_DUMMY_REG__VI;
typedef union SDMA0_GFX_IB_SUB_REMAIN__VI      regSDMA0_GFX_IB_SUB_REMAIN__VI;
typedef union SDMA0_GFX_MIDCMD_CNTL__VI        regSDMA0_GFX_MIDCMD_CNTL__VI;
typedef union SDMA0_GFX_MIDCMD_DATA0__VI       regSDMA0_GFX_MIDCMD_DATA0__VI;
typedef union SDMA0_GFX_MIDCMD_DATA1__VI       regSDMA0_GFX_MIDCMD_DATA1__VI;
typedef union SDMA0_GFX_MIDCMD_DATA2__VI       regSDMA0_GFX_MIDCMD_DATA2__VI;
typedef union SDMA0_GFX_MIDCMD_DATA3__VI       regSDMA0_GFX_MIDCMD_DATA3__VI;
typedef union SDMA0_GFX_MIDCMD_DATA4__VI       regSDMA0_GFX_MIDCMD_DATA4__VI;
typedef union SDMA0_GFX_MIDCMD_DATA5__VI       regSDMA0_GFX_MIDCMD_DATA5__VI;
typedef union SDMA0_GFX_PREEMPT__VI            regSDMA0_GFX_PREEMPT__VI;
typedef union SDMA0_GFX_WATERMARK__VI          regSDMA0_GFX_WATERMARK__VI;
typedef union SDMA0_ID__VI                     regSDMA0_ID__VI;
typedef union SDMA0_PERF_REG_TYPE0__VI         regSDMA0_PERF_REG_TYPE0__VI;
typedef union SDMA0_POWER_CNTL_IDLE__VI        regSDMA0_POWER_CNTL_IDLE__VI;
typedef union SDMA0_PUB_REG_TYPE0__VI          regSDMA0_PUB_REG_TYPE0__VI;
typedef union SDMA0_PUB_REG_TYPE1__VI          regSDMA0_PUB_REG_TYPE1__VI;
typedef union SDMA0_RD_BURST_CNTL__VI          regSDMA0_RD_BURST_CNTL__VI;
typedef union SDMA0_RLC0_CSA_ADDR_HI__VI       regSDMA0_RLC0_CSA_ADDR_HI__VI;
typedef union SDMA0_RLC0_CSA_ADDR_LO__VI       regSDMA0_RLC0_CSA_ADDR_LO__VI;
typedef union SDMA0_RLC0_DUMMY_REG__VI         regSDMA0_RLC0_DUMMY_REG__VI;
typedef union SDMA0_RLC0_IB_SUB_REMAIN__VI     regSDMA0_RLC0_IB_SUB_REMAIN__VI;
typedef union SDMA0_RLC0_MIDCMD_CNTL__VI       regSDMA0_RLC0_MIDCMD_CNTL__VI;
typedef union SDMA0_RLC0_MIDCMD_DATA0__VI      regSDMA0_RLC0_MIDCMD_DATA0__VI;
typedef union SDMA0_RLC0_MIDCMD_DATA1__VI      regSDMA0_RLC0_MIDCMD_DATA1__VI;
typedef union SDMA0_RLC0_MIDCMD_DATA2__VI      regSDMA0_RLC0_MIDCMD_DATA2__VI;
typedef union SDMA0_RLC0_MIDCMD_DATA3__VI      regSDMA0_RLC0_MIDCMD_DATA3__VI;
typedef union SDMA0_RLC0_MIDCMD_DATA4__VI      regSDMA0_RLC0_MIDCMD_DATA4__VI;
typedef union SDMA0_RLC0_MIDCMD_DATA5__VI      regSDMA0_RLC0_MIDCMD_DATA5__VI;
typedef union SDMA0_RLC0_PREEMPT__VI           regSDMA0_RLC0_PREEMPT__VI;
typedef union SDMA0_RLC0_WATERMARK__VI         regSDMA0_RLC0_WATERMARK__VI;
typedef union SDMA0_RLC1_CSA_ADDR_HI__VI       regSDMA0_RLC1_CSA_ADDR_HI__VI;
typedef union SDMA0_RLC1_CSA_ADDR_LO__VI       regSDMA0_RLC1_CSA_ADDR_LO__VI;
typedef union SDMA0_RLC1_DUMMY_REG__VI         regSDMA0_RLC1_DUMMY_REG__VI;
typedef union SDMA0_RLC1_IB_SUB_REMAIN__VI     regSDMA0_RLC1_IB_SUB_REMAIN__VI;
typedef union SDMA0_RLC1_MIDCMD_CNTL__VI       regSDMA0_RLC1_MIDCMD_CNTL__VI;
typedef union SDMA0_RLC1_MIDCMD_DATA0__VI      regSDMA0_RLC1_MIDCMD_DATA0__VI;
typedef union SDMA0_RLC1_MIDCMD_DATA1__VI      regSDMA0_RLC1_MIDCMD_DATA1__VI;
typedef union SDMA0_RLC1_MIDCMD_DATA2__VI      regSDMA0_RLC1_MIDCMD_DATA2__VI;
typedef union SDMA0_RLC1_MIDCMD_DATA3__VI      regSDMA0_RLC1_MIDCMD_DATA3__VI;
typedef union SDMA0_RLC1_MIDCMD_DATA4__VI      regSDMA0_RLC1_MIDCMD_DATA4__VI;
typedef union SDMA0_RLC1_MIDCMD_DATA5__VI      regSDMA0_RLC1_MIDCMD_DATA5__VI;
typedef union SDMA0_RLC1_PREEMPT__VI           regSDMA0_RLC1_PREEMPT__VI;
typedef union SDMA0_RLC1_WATERMARK__VI         regSDMA0_RLC1_WATERMARK__VI;
typedef union SDMA0_STATUS2_REG__VI            regSDMA0_STATUS2_REG__VI;
typedef union SDMA0_VERSION__VI                regSDMA0_VERSION__VI;
typedef union SDMA0_VF_ENABLE__VI              regSDMA0_VF_ENABLE__VI;
typedef union SDMA0_VIRT_RESET_REQ__VI         regSDMA0_VIRT_RESET_REQ__VI;
typedef union SDMA0_VM_CNTL__VI                regSDMA0_VM_CNTL__VI;
typedef union SDMA0_VM_CTX_CNTL__VI            regSDMA0_VM_CTX_CNTL__VI;
typedef union SDMA0_VM_CTX_HI__VI              regSDMA0_VM_CTX_HI__VI;
typedef union SDMA0_VM_CTX_LO__VI              regSDMA0_VM_CTX_LO__VI;
typedef union SDMA1_ACTIVE_FCN_ID__VI          regSDMA1_ACTIVE_FCN_ID__VI;
typedef union SDMA1_ATOMIC_CNTL__VI            regSDMA1_ATOMIC_CNTL__VI;
typedef union SDMA1_ATOMIC_PREOP_HI__VI        regSDMA1_ATOMIC_PREOP_HI__VI;
typedef union SDMA1_ATOMIC_PREOP_LO__VI        regSDMA1_ATOMIC_PREOP_LO__VI;
typedef union SDMA1_BA_THRESHOLD__VI           regSDMA1_BA_THRESHOLD__VI;
typedef union SDMA1_CONTEXT_REG_TYPE0__VI      regSDMA1_CONTEXT_REG_TYPE0__VI;
typedef union SDMA1_CONTEXT_REG_TYPE1__VI      regSDMA1_CONTEXT_REG_TYPE1__VI;
typedef union SDMA1_CONTEXT_REG_TYPE2__VI      regSDMA1_CONTEXT_REG_TYPE2__VI;
typedef union SDMA1_EDC_CONFIG__VI             regSDMA1_EDC_CONFIG__VI;
typedef union SDMA1_GFX_CSA_ADDR_HI__VI        regSDMA1_GFX_CSA_ADDR_HI__VI;
typedef union SDMA1_GFX_CSA_ADDR_LO__VI        regSDMA1_GFX_CSA_ADDR_LO__VI;
typedef union SDMA1_GFX_DOORBELL__VI           regSDMA1_GFX_DOORBELL__VI;
typedef union SDMA1_GFX_DOORBELL_LOG__VI       regSDMA1_GFX_DOORBELL_LOG__VI;
typedef union SDMA1_GFX_DUMMY_REG__VI          regSDMA1_GFX_DUMMY_REG__VI;
typedef union SDMA1_GFX_IB_SUB_REMAIN__VI      regSDMA1_GFX_IB_SUB_REMAIN__VI;
typedef union SDMA1_GFX_MIDCMD_CNTL__VI        regSDMA1_GFX_MIDCMD_CNTL__VI;
typedef union SDMA1_GFX_MIDCMD_DATA0__VI       regSDMA1_GFX_MIDCMD_DATA0__VI;
typedef union SDMA1_GFX_MIDCMD_DATA1__VI       regSDMA1_GFX_MIDCMD_DATA1__VI;
typedef union SDMA1_GFX_MIDCMD_DATA2__VI       regSDMA1_GFX_MIDCMD_DATA2__VI;
typedef union SDMA1_GFX_MIDCMD_DATA3__VI       regSDMA1_GFX_MIDCMD_DATA3__VI;
typedef union SDMA1_GFX_MIDCMD_DATA4__VI       regSDMA1_GFX_MIDCMD_DATA4__VI;
typedef union SDMA1_GFX_MIDCMD_DATA5__VI       regSDMA1_GFX_MIDCMD_DATA5__VI;
typedef union SDMA1_GFX_PREEMPT__VI            regSDMA1_GFX_PREEMPT__VI;
typedef union SDMA1_GFX_WATERMARK__VI          regSDMA1_GFX_WATERMARK__VI;
typedef union SDMA1_ID__VI                     regSDMA1_ID__VI;
typedef union SDMA1_PERF_REG_TYPE0__VI         regSDMA1_PERF_REG_TYPE0__VI;
typedef union SDMA1_POWER_CNTL_IDLE__VI        regSDMA1_POWER_CNTL_IDLE__VI;
typedef union SDMA1_PUB_REG_TYPE0__VI          regSDMA1_PUB_REG_TYPE0__VI;
typedef union SDMA1_PUB_REG_TYPE1__VI          regSDMA1_PUB_REG_TYPE1__VI;
typedef union SDMA1_RD_BURST_CNTL__VI          regSDMA1_RD_BURST_CNTL__VI;
typedef union SDMA1_RLC0_CSA_ADDR_HI__VI       regSDMA1_RLC0_CSA_ADDR_HI__VI;
typedef union SDMA1_RLC0_CSA_ADDR_LO__VI       regSDMA1_RLC0_CSA_ADDR_LO__VI;
typedef union SDMA1_RLC0_DUMMY_REG__VI         regSDMA1_RLC0_DUMMY_REG__VI;
typedef union SDMA1_RLC0_IB_SUB_REMAIN__VI     regSDMA1_RLC0_IB_SUB_REMAIN__VI;
typedef union SDMA1_RLC0_MIDCMD_CNTL__VI       regSDMA1_RLC0_MIDCMD_CNTL__VI;
typedef union SDMA1_RLC0_MIDCMD_DATA0__VI      regSDMA1_RLC0_MIDCMD_DATA0__VI;
typedef union SDMA1_RLC0_MIDCMD_DATA1__VI      regSDMA1_RLC0_MIDCMD_DATA1__VI;
typedef union SDMA1_RLC0_MIDCMD_DATA2__VI      regSDMA1_RLC0_MIDCMD_DATA2__VI;
typedef union SDMA1_RLC0_MIDCMD_DATA3__VI      regSDMA1_RLC0_MIDCMD_DATA3__VI;
typedef union SDMA1_RLC0_MIDCMD_DATA4__VI      regSDMA1_RLC0_MIDCMD_DATA4__VI;
typedef union SDMA1_RLC0_MIDCMD_DATA5__VI      regSDMA1_RLC0_MIDCMD_DATA5__VI;
typedef union SDMA1_RLC0_PREEMPT__VI           regSDMA1_RLC0_PREEMPT__VI;
typedef union SDMA1_RLC0_WATERMARK__VI         regSDMA1_RLC0_WATERMARK__VI;
typedef union SDMA1_RLC1_CSA_ADDR_HI__VI       regSDMA1_RLC1_CSA_ADDR_HI__VI;
typedef union SDMA1_RLC1_CSA_ADDR_LO__VI       regSDMA1_RLC1_CSA_ADDR_LO__VI;
typedef union SDMA1_RLC1_DUMMY_REG__VI         regSDMA1_RLC1_DUMMY_REG__VI;
typedef union SDMA1_RLC1_IB_SUB_REMAIN__VI     regSDMA1_RLC1_IB_SUB_REMAIN__VI;
typedef union SDMA1_RLC1_MIDCMD_CNTL__VI       regSDMA1_RLC1_MIDCMD_CNTL__VI;
typedef union SDMA1_RLC1_MIDCMD_DATA0__VI      regSDMA1_RLC1_MIDCMD_DATA0__VI;
typedef union SDMA1_RLC1_MIDCMD_DATA1__VI      regSDMA1_RLC1_MIDCMD_DATA1__VI;
typedef union SDMA1_RLC1_MIDCMD_DATA2__VI      regSDMA1_RLC1_MIDCMD_DATA2__VI;
typedef union SDMA1_RLC1_MIDCMD_DATA3__VI      regSDMA1_RLC1_MIDCMD_DATA3__VI;
typedef union SDMA1_RLC1_MIDCMD_DATA4__VI      regSDMA1_RLC1_MIDCMD_DATA4__VI;
typedef union SDMA1_RLC1_MIDCMD_DATA5__VI      regSDMA1_RLC1_MIDCMD_DATA5__VI;
typedef union SDMA1_RLC1_PREEMPT__VI           regSDMA1_RLC1_PREEMPT__VI;
typedef union SDMA1_RLC1_WATERMARK__VI         regSDMA1_RLC1_WATERMARK__VI;
typedef union SDMA1_STATUS2_REG__VI            regSDMA1_STATUS2_REG__VI;
typedef union SDMA1_VERSION__VI                regSDMA1_VERSION__VI;
typedef union SDMA1_VF_ENABLE__VI              regSDMA1_VF_ENABLE__VI;
typedef union SDMA1_VIRT_RESET_REQ__VI         regSDMA1_VIRT_RESET_REQ__VI;
typedef union SDMA1_VM_CNTL__VI                regSDMA1_VM_CNTL__VI;
typedef union SDMA1_VM_CTX_CNTL__VI            regSDMA1_VM_CTX_CNTL__VI;
typedef union SDMA1_VM_CTX_HI__VI              regSDMA1_VM_CTX_HI__VI;
typedef union SDMA1_VM_CTX_LO__VI              regSDMA1_VM_CTX_LO__VI;
typedef union SEM_ACTIVE_FCN_ID__VI            regSEM_ACTIVE_FCN_ID__VI;
typedef union SEM_MAILBOX_CLIENTCONFIG_EXTRA__VI regSEM_MAILBOX_CLIENTCONFIG_EXTRA__VI;
typedef union SEM_PERFCOUNTER0_RESULT__VI      regSEM_PERFCOUNTER0_RESULT__VI;
typedef union SEM_PERFCOUNTER1_RESULT__VI      regSEM_PERFCOUNTER1_RESULT__VI;
typedef union SEM_PERFMON_CNTL__VI             regSEM_PERFMON_CNTL__VI;
typedef union SEM_VF_ENABLE__VI                regSEM_VF_ENABLE__VI;
typedef union SEM_VIRT_RESET_REQ__VI           regSEM_VIRT_RESET_REQ__VI;
typedef union SE_CAC_CGTT_CLK_CTRL__VI         regSE_CAC_CGTT_CLK_CTRL__VI;
typedef union SINK_DESCRIPTION0__VI            regSINK_DESCRIPTION0__VI;
typedef union SINK_DESCRIPTION1__VI            regSINK_DESCRIPTION1__VI;
typedef union SINK_DESCRIPTION10__VI           regSINK_DESCRIPTION10__VI;
typedef union SINK_DESCRIPTION11__VI           regSINK_DESCRIPTION11__VI;
typedef union SINK_DESCRIPTION12__VI           regSINK_DESCRIPTION12__VI;
typedef union SINK_DESCRIPTION13__VI           regSINK_DESCRIPTION13__VI;
typedef union SINK_DESCRIPTION14__VI           regSINK_DESCRIPTION14__VI;
typedef union SINK_DESCRIPTION15__VI           regSINK_DESCRIPTION15__VI;
typedef union SINK_DESCRIPTION16__VI           regSINK_DESCRIPTION16__VI;
typedef union SINK_DESCRIPTION17__VI           regSINK_DESCRIPTION17__VI;
typedef union SINK_DESCRIPTION2__VI            regSINK_DESCRIPTION2__VI;
typedef union SINK_DESCRIPTION3__VI            regSINK_DESCRIPTION3__VI;
typedef union SINK_DESCRIPTION4__VI            regSINK_DESCRIPTION4__VI;
typedef union SINK_DESCRIPTION5__VI            regSINK_DESCRIPTION5__VI;
typedef union SINK_DESCRIPTION6__VI            regSINK_DESCRIPTION6__VI;
typedef union SINK_DESCRIPTION7__VI            regSINK_DESCRIPTION7__VI;
typedef union SINK_DESCRIPTION8__VI            regSINK_DESCRIPTION8__VI;
typedef union SINK_DESCRIPTION9__VI            regSINK_DESCRIPTION9__VI;
typedef union SMBUS_BACO_DUMMY__VI             regSMBUS_BACO_DUMMY__VI;
typedef union SMU_BIF_VDDGFX_PWR_STATUS__VI    regSMU_BIF_VDDGFX_PWR_STATUS__VI;
typedef union SMU_CONTROL__VI                  regSMU_CONTROL__VI;
typedef union SMU_IND_DATA_0__VI               regSMU_IND_DATA_0__VI;
typedef union SMU_IND_DATA_1__VI               regSMU_IND_DATA_1__VI;
typedef union SMU_IND_DATA_2__VI               regSMU_IND_DATA_2__VI;
typedef union SMU_IND_DATA_3__VI               regSMU_IND_DATA_3__VI;
typedef union SMU_IND_DATA_4__VI               regSMU_IND_DATA_4__VI;
typedef union SMU_IND_DATA_5__VI               regSMU_IND_DATA_5__VI;
typedef union SMU_IND_DATA_6__VI               regSMU_IND_DATA_6__VI;
typedef union SMU_IND_DATA_7__VI               regSMU_IND_DATA_7__VI;
typedef union SMU_IND_INDEX_0__VI              regSMU_IND_INDEX_0__VI;
typedef union SMU_IND_INDEX_1__VI              regSMU_IND_INDEX_1__VI;
typedef union SMU_IND_INDEX_2__VI              regSMU_IND_INDEX_2__VI;
typedef union SMU_IND_INDEX_3__VI              regSMU_IND_INDEX_3__VI;
typedef union SMU_IND_INDEX_4__VI              regSMU_IND_INDEX_4__VI;
typedef union SMU_IND_INDEX_5__VI              regSMU_IND_INDEX_5__VI;
typedef union SMU_IND_INDEX_6__VI              regSMU_IND_INDEX_6__VI;
typedef union SMU_IND_INDEX_7__VI              regSMU_IND_INDEX_7__VI;
typedef union SMU_INTERRUPT_CONTROL__VI        regSMU_INTERRUPT_CONTROL__VI;
typedef union SMU_MP1_RLC2MP_RESP__VI          regSMU_MP1_RLC2MP_RESP__VI;
typedef union SMU_MP1_SRBM2P_MSG_5__VI         regSMU_MP1_SRBM2P_MSG_5__VI;
typedef union SMU_PM_STATUS_0__VI              regSMU_PM_STATUS_0__VI;
typedef union SMU_PM_STATUS_1__VI              regSMU_PM_STATUS_1__VI;
typedef union SMU_PM_STATUS_10__VI             regSMU_PM_STATUS_10__VI;
typedef union SMU_PM_STATUS_100__VI            regSMU_PM_STATUS_100__VI;
typedef union SMU_PM_STATUS_101__VI            regSMU_PM_STATUS_101__VI;
typedef union SMU_PM_STATUS_102__VI            regSMU_PM_STATUS_102__VI;
typedef union SMU_PM_STATUS_103__VI            regSMU_PM_STATUS_103__VI;
typedef union SMU_PM_STATUS_104__VI            regSMU_PM_STATUS_104__VI;
typedef union SMU_PM_STATUS_105__VI            regSMU_PM_STATUS_105__VI;
typedef union SMU_PM_STATUS_106__VI            regSMU_PM_STATUS_106__VI;
typedef union SMU_PM_STATUS_107__VI            regSMU_PM_STATUS_107__VI;
typedef union SMU_PM_STATUS_108__VI            regSMU_PM_STATUS_108__VI;
typedef union SMU_PM_STATUS_109__VI            regSMU_PM_STATUS_109__VI;
typedef union SMU_PM_STATUS_11__VI             regSMU_PM_STATUS_11__VI;
typedef union SMU_PM_STATUS_110__VI            regSMU_PM_STATUS_110__VI;
typedef union SMU_PM_STATUS_111__VI            regSMU_PM_STATUS_111__VI;
typedef union SMU_PM_STATUS_112__VI            regSMU_PM_STATUS_112__VI;
typedef union SMU_PM_STATUS_113__VI            regSMU_PM_STATUS_113__VI;
typedef union SMU_PM_STATUS_114__VI            regSMU_PM_STATUS_114__VI;
typedef union SMU_PM_STATUS_115__VI            regSMU_PM_STATUS_115__VI;
typedef union SMU_PM_STATUS_116__VI            regSMU_PM_STATUS_116__VI;
typedef union SMU_PM_STATUS_117__VI            regSMU_PM_STATUS_117__VI;
typedef union SMU_PM_STATUS_118__VI            regSMU_PM_STATUS_118__VI;
typedef union SMU_PM_STATUS_119__VI            regSMU_PM_STATUS_119__VI;
typedef union SMU_PM_STATUS_12__VI             regSMU_PM_STATUS_12__VI;
typedef union SMU_PM_STATUS_120__VI            regSMU_PM_STATUS_120__VI;
typedef union SMU_PM_STATUS_121__VI            regSMU_PM_STATUS_121__VI;
typedef union SMU_PM_STATUS_122__VI            regSMU_PM_STATUS_122__VI;
typedef union SMU_PM_STATUS_123__VI            regSMU_PM_STATUS_123__VI;
typedef union SMU_PM_STATUS_124__VI            regSMU_PM_STATUS_124__VI;
typedef union SMU_PM_STATUS_125__VI            regSMU_PM_STATUS_125__VI;
typedef union SMU_PM_STATUS_126__VI            regSMU_PM_STATUS_126__VI;
typedef union SMU_PM_STATUS_127__VI            regSMU_PM_STATUS_127__VI;
typedef union SMU_PM_STATUS_13__VI             regSMU_PM_STATUS_13__VI;
typedef union SMU_PM_STATUS_14__VI             regSMU_PM_STATUS_14__VI;
typedef union SMU_PM_STATUS_15__VI             regSMU_PM_STATUS_15__VI;
typedef union SMU_PM_STATUS_16__VI             regSMU_PM_STATUS_16__VI;
typedef union SMU_PM_STATUS_17__VI             regSMU_PM_STATUS_17__VI;
typedef union SMU_PM_STATUS_18__VI             regSMU_PM_STATUS_18__VI;
typedef union SMU_PM_STATUS_19__VI             regSMU_PM_STATUS_19__VI;
typedef union SMU_PM_STATUS_2__VI              regSMU_PM_STATUS_2__VI;
typedef union SMU_PM_STATUS_20__VI             regSMU_PM_STATUS_20__VI;
typedef union SMU_PM_STATUS_21__VI             regSMU_PM_STATUS_21__VI;
typedef union SMU_PM_STATUS_22__VI             regSMU_PM_STATUS_22__VI;
typedef union SMU_PM_STATUS_23__VI             regSMU_PM_STATUS_23__VI;
typedef union SMU_PM_STATUS_24__VI             regSMU_PM_STATUS_24__VI;
typedef union SMU_PM_STATUS_25__VI             regSMU_PM_STATUS_25__VI;
typedef union SMU_PM_STATUS_26__VI             regSMU_PM_STATUS_26__VI;
typedef union SMU_PM_STATUS_27__VI             regSMU_PM_STATUS_27__VI;
typedef union SMU_PM_STATUS_28__VI             regSMU_PM_STATUS_28__VI;
typedef union SMU_PM_STATUS_29__VI             regSMU_PM_STATUS_29__VI;
typedef union SMU_PM_STATUS_3__VI              regSMU_PM_STATUS_3__VI;
typedef union SMU_PM_STATUS_30__VI             regSMU_PM_STATUS_30__VI;
typedef union SMU_PM_STATUS_31__VI             regSMU_PM_STATUS_31__VI;
typedef union SMU_PM_STATUS_32__VI             regSMU_PM_STATUS_32__VI;
typedef union SMU_PM_STATUS_33__VI             regSMU_PM_STATUS_33__VI;
typedef union SMU_PM_STATUS_34__VI             regSMU_PM_STATUS_34__VI;
typedef union SMU_PM_STATUS_35__VI             regSMU_PM_STATUS_35__VI;
typedef union SMU_PM_STATUS_36__VI             regSMU_PM_STATUS_36__VI;
typedef union SMU_PM_STATUS_37__VI             regSMU_PM_STATUS_37__VI;
typedef union SMU_PM_STATUS_38__VI             regSMU_PM_STATUS_38__VI;
typedef union SMU_PM_STATUS_39__VI             regSMU_PM_STATUS_39__VI;
typedef union SMU_PM_STATUS_4__VI              regSMU_PM_STATUS_4__VI;
typedef union SMU_PM_STATUS_40__VI             regSMU_PM_STATUS_40__VI;
typedef union SMU_PM_STATUS_41__VI             regSMU_PM_STATUS_41__VI;
typedef union SMU_PM_STATUS_42__VI             regSMU_PM_STATUS_42__VI;
typedef union SMU_PM_STATUS_43__VI             regSMU_PM_STATUS_43__VI;
typedef union SMU_PM_STATUS_44__VI             regSMU_PM_STATUS_44__VI;
typedef union SMU_PM_STATUS_45__VI             regSMU_PM_STATUS_45__VI;
typedef union SMU_PM_STATUS_46__VI             regSMU_PM_STATUS_46__VI;
typedef union SMU_PM_STATUS_47__VI             regSMU_PM_STATUS_47__VI;
typedef union SMU_PM_STATUS_48__VI             regSMU_PM_STATUS_48__VI;
typedef union SMU_PM_STATUS_49__VI             regSMU_PM_STATUS_49__VI;
typedef union SMU_PM_STATUS_5__VI              regSMU_PM_STATUS_5__VI;
typedef union SMU_PM_STATUS_50__VI             regSMU_PM_STATUS_50__VI;
typedef union SMU_PM_STATUS_51__VI             regSMU_PM_STATUS_51__VI;
typedef union SMU_PM_STATUS_52__VI             regSMU_PM_STATUS_52__VI;
typedef union SMU_PM_STATUS_53__VI             regSMU_PM_STATUS_53__VI;
typedef union SMU_PM_STATUS_54__VI             regSMU_PM_STATUS_54__VI;
typedef union SMU_PM_STATUS_55__VI             regSMU_PM_STATUS_55__VI;
typedef union SMU_PM_STATUS_56__VI             regSMU_PM_STATUS_56__VI;
typedef union SMU_PM_STATUS_57__VI             regSMU_PM_STATUS_57__VI;
typedef union SMU_PM_STATUS_58__VI             regSMU_PM_STATUS_58__VI;
typedef union SMU_PM_STATUS_59__VI             regSMU_PM_STATUS_59__VI;
typedef union SMU_PM_STATUS_6__VI              regSMU_PM_STATUS_6__VI;
typedef union SMU_PM_STATUS_60__VI             regSMU_PM_STATUS_60__VI;
typedef union SMU_PM_STATUS_61__VI             regSMU_PM_STATUS_61__VI;
typedef union SMU_PM_STATUS_62__VI             regSMU_PM_STATUS_62__VI;
typedef union SMU_PM_STATUS_63__VI             regSMU_PM_STATUS_63__VI;
typedef union SMU_PM_STATUS_64__VI             regSMU_PM_STATUS_64__VI;
typedef union SMU_PM_STATUS_65__VI             regSMU_PM_STATUS_65__VI;
typedef union SMU_PM_STATUS_66__VI             regSMU_PM_STATUS_66__VI;
typedef union SMU_PM_STATUS_67__VI             regSMU_PM_STATUS_67__VI;
typedef union SMU_PM_STATUS_68__VI             regSMU_PM_STATUS_68__VI;
typedef union SMU_PM_STATUS_69__VI             regSMU_PM_STATUS_69__VI;
typedef union SMU_PM_STATUS_7__VI              regSMU_PM_STATUS_7__VI;
typedef union SMU_PM_STATUS_70__VI             regSMU_PM_STATUS_70__VI;
typedef union SMU_PM_STATUS_71__VI             regSMU_PM_STATUS_71__VI;
typedef union SMU_PM_STATUS_72__VI             regSMU_PM_STATUS_72__VI;
typedef union SMU_PM_STATUS_73__VI             regSMU_PM_STATUS_73__VI;
typedef union SMU_PM_STATUS_74__VI             regSMU_PM_STATUS_74__VI;
typedef union SMU_PM_STATUS_75__VI             regSMU_PM_STATUS_75__VI;
typedef union SMU_PM_STATUS_76__VI             regSMU_PM_STATUS_76__VI;
typedef union SMU_PM_STATUS_77__VI             regSMU_PM_STATUS_77__VI;
typedef union SMU_PM_STATUS_78__VI             regSMU_PM_STATUS_78__VI;
typedef union SMU_PM_STATUS_79__VI             regSMU_PM_STATUS_79__VI;
typedef union SMU_PM_STATUS_8__VI              regSMU_PM_STATUS_8__VI;
typedef union SMU_PM_STATUS_80__VI             regSMU_PM_STATUS_80__VI;
typedef union SMU_PM_STATUS_81__VI             regSMU_PM_STATUS_81__VI;
typedef union SMU_PM_STATUS_82__VI             regSMU_PM_STATUS_82__VI;
typedef union SMU_PM_STATUS_83__VI             regSMU_PM_STATUS_83__VI;
typedef union SMU_PM_STATUS_84__VI             regSMU_PM_STATUS_84__VI;
typedef union SMU_PM_STATUS_85__VI             regSMU_PM_STATUS_85__VI;
typedef union SMU_PM_STATUS_86__VI             regSMU_PM_STATUS_86__VI;
typedef union SMU_PM_STATUS_87__VI             regSMU_PM_STATUS_87__VI;
typedef union SMU_PM_STATUS_88__VI             regSMU_PM_STATUS_88__VI;
typedef union SMU_PM_STATUS_89__VI             regSMU_PM_STATUS_89__VI;
typedef union SMU_PM_STATUS_9__VI              regSMU_PM_STATUS_9__VI;
typedef union SMU_PM_STATUS_90__VI             regSMU_PM_STATUS_90__VI;
typedef union SMU_PM_STATUS_91__VI             regSMU_PM_STATUS_91__VI;
typedef union SMU_PM_STATUS_92__VI             regSMU_PM_STATUS_92__VI;
typedef union SMU_PM_STATUS_93__VI             regSMU_PM_STATUS_93__VI;
typedef union SMU_PM_STATUS_94__VI             regSMU_PM_STATUS_94__VI;
typedef union SMU_PM_STATUS_95__VI             regSMU_PM_STATUS_95__VI;
typedef union SMU_PM_STATUS_96__VI             regSMU_PM_STATUS_96__VI;
typedef union SMU_PM_STATUS_97__VI             regSMU_PM_STATUS_97__VI;
typedef union SMU_PM_STATUS_98__VI             regSMU_PM_STATUS_98__VI;
typedef union SMU_PM_STATUS_99__VI             regSMU_PM_STATUS_99__VI;
typedef union SMU_RLC_RESPONSE__VI             regSMU_RLC_RESPONSE__VI;
typedef union SM_CONTROL2__VI                  regSM_CONTROL2__VI;
typedef union SOFT_REGISTERS_TABLE_1__VI       regSOFT_REGISTERS_TABLE_1__VI;
typedef union SOFT_REGISTERS_TABLE_10__VI      regSOFT_REGISTERS_TABLE_10__VI;
typedef union SOFT_REGISTERS_TABLE_11__VI      regSOFT_REGISTERS_TABLE_11__VI;
typedef union SOFT_REGISTERS_TABLE_12__VI      regSOFT_REGISTERS_TABLE_12__VI;
typedef union SOFT_REGISTERS_TABLE_13__VI      regSOFT_REGISTERS_TABLE_13__VI;
typedef union SOFT_REGISTERS_TABLE_14__VI      regSOFT_REGISTERS_TABLE_14__VI;
typedef union SOFT_REGISTERS_TABLE_15__VI      regSOFT_REGISTERS_TABLE_15__VI;
typedef union SOFT_REGISTERS_TABLE_16__VI      regSOFT_REGISTERS_TABLE_16__VI;
typedef union SOFT_REGISTERS_TABLE_17__VI      regSOFT_REGISTERS_TABLE_17__VI;
typedef union SOFT_REGISTERS_TABLE_18__VI      regSOFT_REGISTERS_TABLE_18__VI;
typedef union SOFT_REGISTERS_TABLE_19__VI      regSOFT_REGISTERS_TABLE_19__VI;
typedef union SOFT_REGISTERS_TABLE_2__VI       regSOFT_REGISTERS_TABLE_2__VI;
typedef union SOFT_REGISTERS_TABLE_20__VI      regSOFT_REGISTERS_TABLE_20__VI;
typedef union SOFT_REGISTERS_TABLE_21__VI      regSOFT_REGISTERS_TABLE_21__VI;
typedef union SOFT_REGISTERS_TABLE_22__VI      regSOFT_REGISTERS_TABLE_22__VI;
typedef union SOFT_REGISTERS_TABLE_23__VI      regSOFT_REGISTERS_TABLE_23__VI;
typedef union SOFT_REGISTERS_TABLE_24__VI      regSOFT_REGISTERS_TABLE_24__VI;
typedef union SOFT_REGISTERS_TABLE_25__VI      regSOFT_REGISTERS_TABLE_25__VI;
typedef union SOFT_REGISTERS_TABLE_26__VI      regSOFT_REGISTERS_TABLE_26__VI;
typedef union SOFT_REGISTERS_TABLE_27__VI      regSOFT_REGISTERS_TABLE_27__VI;
typedef union SOFT_REGISTERS_TABLE_28__VI      regSOFT_REGISTERS_TABLE_28__VI;
typedef union SOFT_REGISTERS_TABLE_29__VI      regSOFT_REGISTERS_TABLE_29__VI;
typedef union SOFT_REGISTERS_TABLE_3__VI       regSOFT_REGISTERS_TABLE_3__VI;
typedef union SOFT_REGISTERS_TABLE_30__VI      regSOFT_REGISTERS_TABLE_30__VI;
typedef union SOFT_REGISTERS_TABLE_4__VI       regSOFT_REGISTERS_TABLE_4__VI;
typedef union SOFT_REGISTERS_TABLE_5__VI       regSOFT_REGISTERS_TABLE_5__VI;
typedef union SOFT_REGISTERS_TABLE_6__VI       regSOFT_REGISTERS_TABLE_6__VI;
typedef union SOFT_REGISTERS_TABLE_7__VI       regSOFT_REGISTERS_TABLE_7__VI;
typedef union SOFT_REGISTERS_TABLE_8__VI       regSOFT_REGISTERS_TABLE_8__VI;
typedef union SOFT_REGISTERS_TABLE_9__VI       regSOFT_REGISTERS_TABLE_9__VI;
typedef union SPI_COMPUTE_WF_CTX_SAVE__VI      regSPI_COMPUTE_WF_CTX_SAVE__VI;
typedef union SPI_CONFIG_CNTL_2__VI            regSPI_CONFIG_CNTL_2__VI;
typedef union SPI_DSM_CNTL__VI                 regSPI_DSM_CNTL__VI;
typedef union SPI_EDC_CNT__VI                  regSPI_EDC_CNT__VI;
typedef union SPI_GFX_CNTL__VI                 regSPI_GFX_CNTL__VI;
typedef union SPI_RESOURCE_RESERVE_CU_12__VI   regSPI_RESOURCE_RESERVE_CU_12__VI;
typedef union SPI_RESOURCE_RESERVE_CU_13__VI   regSPI_RESOURCE_RESERVE_CU_13__VI;
typedef union SPI_RESOURCE_RESERVE_CU_14__VI   regSPI_RESOURCE_RESERVE_CU_14__VI;
typedef union SPI_RESOURCE_RESERVE_CU_15__VI   regSPI_RESOURCE_RESERVE_CU_15__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_12__VI regSPI_RESOURCE_RESERVE_EN_CU_12__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_13__VI regSPI_RESOURCE_RESERVE_EN_CU_13__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_14__VI regSPI_RESOURCE_RESERVE_EN_CU_14__VI;
typedef union SPI_RESOURCE_RESERVE_EN_CU_15__VI regSPI_RESOURCE_RESERVE_EN_CU_15__VI;
typedef union SPI_START_PHASE__VI              regSPI_START_PHASE__VI;
typedef union SPMI_CONFIG0_0__VI               regSPMI_CONFIG0_0__VI;
typedef union SPMI_CONFIG1_0__VI               regSPMI_CONFIG1_0__VI;
typedef union SPMI_FORCE_CLOCK_GATERS__VI      regSPMI_FORCE_CLOCK_GATERS__VI;
typedef union SPMI_SPARE__VI                   regSPMI_SPARE__VI;
typedef union SPMI_SPARE_EX__VI                regSPMI_SPARE_EX__VI;
typedef union SPMI_SRAM_CLK_GATER__VI          regSPMI_SRAM_CLK_GATER__VI;
typedef union SPU_PORT_STATUS__VI              regSPU_PORT_STATUS__VI;
typedef union SQC_ATC_EDC_GATCL1_CNT__VI       regSQC_ATC_EDC_GATCL1_CNT__VI;
typedef union SQC_DSM_CNTL__VI                 regSQC_DSM_CNTL__VI;
typedef union SQC_EDC_CNT__VI                  regSQC_EDC_CNT__VI;
typedef union SQC_GATCL1_CNTL__VI              regSQC_GATCL1_CNTL__VI;
typedef union SQC_WRITEBACK__VI                regSQC_WRITEBACK__VI;
typedef union SQ_DSM_CNTL__VI                  regSQ_DSM_CNTL__VI;
typedef union SQ_EDC_DED_CNT__VI               regSQ_EDC_DED_CNT__VI;
typedef union SQ_EDC_INFO__VI                  regSQ_EDC_INFO__VI;
typedef union SQ_EDC_SEC_CNT__VI               regSQ_EDC_SEC_CNT__VI;
typedef union SQ_M0_GPR_IDX_WORD__VI           regSQ_M0_GPR_IDX_WORD__VI;
typedef union SQ_SMEM_0__VI                    regSQ_SMEM_0__VI;
typedef union SQ_SMEM_1__VI                    regSQ_SMEM_1__VI;
typedef union SQ_VOP_DPP__VI                   regSQ_VOP_DPP__VI;
typedef union SQ_VOP_SDWA__VI                  regSQ_VOP_SDWA__VI;
typedef union SQ_WAVE_IB_DBG1__VI              regSQ_WAVE_IB_DBG1__VI;
typedef union SQ_WREXEC_EXEC_HI__VI            regSQ_WREXEC_EXEC_HI__VI;
typedef union SQ_WREXEC_EXEC_LO__VI            regSQ_WREXEC_EXEC_LO__VI;
typedef union SRBM_CREDIT_RECOVER__VI          regSRBM_CREDIT_RECOVER__VI;
typedef union SRBM_CREDIT_RECOVER_CNTL__VI     regSRBM_CREDIT_RECOVER_CNTL__VI;
typedef union SRBM_CREDIT_RESET__VI            regSRBM_CREDIT_RESET__VI;
typedef union SRBM_DEBUG_SNAPSHOT2__VI         regSRBM_DEBUG_SNAPSHOT2__VI;
typedef union SRBM_DSM_TRIG_CNTL0__VI          regSRBM_DSM_TRIG_CNTL0__VI;
typedef union SRBM_DSM_TRIG_CNTL1__VI          regSRBM_DSM_TRIG_CNTL1__VI;
typedef union SRBM_DSM_TRIG_MASK0__VI          regSRBM_DSM_TRIG_MASK0__VI;
typedef union SRBM_DSM_TRIG_MASK1__VI          regSRBM_DSM_TRIG_MASK1__VI;
typedef union SRBM_FIREWALL_ERROR_ADDR__VI     regSRBM_FIREWALL_ERROR_ADDR__VI;
typedef union SRBM_FIREWALL_ERROR_SRC__VI      regSRBM_FIREWALL_ERROR_SRC__VI;
typedef union SRBM_GFX_CNTL_DATA__VI           regSRBM_GFX_CNTL_DATA__VI;
typedef union SRBM_GFX_CNTL_SELECT__VI         regSRBM_GFX_CNTL_SELECT__VI;
typedef union SRBM_ISP_CLKEN_CNTL__VI          regSRBM_ISP_CLKEN_CNTL__VI;
typedef union SRBM_ISP_DOMAIN_ADDR0__VI        regSRBM_ISP_DOMAIN_ADDR0__VI;
typedef union SRBM_ISP_DOMAIN_ADDR1__VI        regSRBM_ISP_DOMAIN_ADDR1__VI;
typedef union SRBM_ISP_DOMAIN_ADDR2__VI        regSRBM_ISP_DOMAIN_ADDR2__VI;
typedef union SRBM_MC_DOMAIN_ADDR0__VI         regSRBM_MC_DOMAIN_ADDR0__VI;
typedef union SRBM_MC_DOMAIN_ADDR1__VI         regSRBM_MC_DOMAIN_ADDR1__VI;
typedef union SRBM_MC_DOMAIN_ADDR2__VI         regSRBM_MC_DOMAIN_ADDR2__VI;
typedef union SRBM_MC_DOMAIN_ADDR3__VI         regSRBM_MC_DOMAIN_ADDR3__VI;
typedef union SRBM_MC_DOMAIN_ADDR4__VI         regSRBM_MC_DOMAIN_ADDR4__VI;
typedef union SRBM_MC_DOMAIN_ADDR5__VI         regSRBM_MC_DOMAIN_ADDR5__VI;
typedef union SRBM_MC_DOMAIN_ADDR6__VI         regSRBM_MC_DOMAIN_ADDR6__VI;
typedef union SRBM_READ_CNTL__VI               regSRBM_READ_CNTL__VI;
typedef union SRBM_READ_ERROR2__VI             regSRBM_READ_ERROR2__VI;
typedef union SRBM_SAM_DOMAIN_ADDR0__VI        regSRBM_SAM_DOMAIN_ADDR0__VI;
typedef union SRBM_SAM_DOMAIN_ADDR1__VI        regSRBM_SAM_DOMAIN_ADDR1__VI;
typedef union SRBM_SAM_DOMAIN_ADDR2__VI        regSRBM_SAM_DOMAIN_ADDR2__VI;
typedef union SRBM_SDMA_DOMAIN_ADDR0__VI       regSRBM_SDMA_DOMAIN_ADDR0__VI;
typedef union SRBM_SDMA_DOMAIN_ADDR1__VI       regSRBM_SDMA_DOMAIN_ADDR1__VI;
typedef union SRBM_SDMA_DOMAIN_ADDR2__VI       regSRBM_SDMA_DOMAIN_ADDR2__VI;
typedef union SRBM_SDMA_DOMAIN_ADDR3__VI       regSRBM_SDMA_DOMAIN_ADDR3__VI;
typedef union SRBM_STATUS3__VI                 regSRBM_STATUS3__VI;
typedef union SRBM_SYS_DOMAIN_ADDR0__VI        regSRBM_SYS_DOMAIN_ADDR0__VI;
typedef union SRBM_SYS_DOMAIN_ADDR1__VI        regSRBM_SYS_DOMAIN_ADDR1__VI;
typedef union SRBM_SYS_DOMAIN_ADDR2__VI        regSRBM_SYS_DOMAIN_ADDR2__VI;
typedef union SRBM_SYS_DOMAIN_ADDR3__VI        regSRBM_SYS_DOMAIN_ADDR3__VI;
typedef union SRBM_SYS_DOMAIN_ADDR4__VI        regSRBM_SYS_DOMAIN_ADDR4__VI;
typedef union SRBM_SYS_DOMAIN_ADDR5__VI        regSRBM_SYS_DOMAIN_ADDR5__VI;
typedef union SRBM_SYS_DOMAIN_ADDR6__VI        regSRBM_SYS_DOMAIN_ADDR6__VI;
typedef union SRBM_UVD_DOMAIN_ADDR0__VI        regSRBM_UVD_DOMAIN_ADDR0__VI;
typedef union SRBM_UVD_DOMAIN_ADDR1__VI        regSRBM_UVD_DOMAIN_ADDR1__VI;
typedef union SRBM_UVD_DOMAIN_ADDR2__VI        regSRBM_UVD_DOMAIN_ADDR2__VI;
typedef union SRBM_VCE_DOMAIN_ADDR0__VI        regSRBM_VCE_DOMAIN_ADDR0__VI;
typedef union SRBM_VCE_DOMAIN_ADDR1__VI        regSRBM_VCE_DOMAIN_ADDR1__VI;
typedef union SRBM_VCE_DOMAIN_ADDR2__VI        regSRBM_VCE_DOMAIN_ADDR2__VI;
typedef union SRBM_VF_ENABLE__VI               regSRBM_VF_ENABLE__VI;
typedef union SRBM_VIRT_CNTL__VI               regSRBM_VIRT_CNTL__VI;
typedef union SRBM_VIRT_RESET_REQ__VI          regSRBM_VIRT_RESET_REQ__VI;
typedef union SRBM_VP8_CLKEN_CNTL__VI          regSRBM_VP8_CLKEN_CNTL__VI;
typedef union SRBM_VP8_DOMAIN_ADDR0__VI        regSRBM_VP8_DOMAIN_ADDR0__VI;
typedef union SWRST_COMMAND_0__VI              regSWRST_COMMAND_0__VI;
typedef union SWRST_COMMAND_1__VI              regSWRST_COMMAND_1__VI;
typedef union SWRST_COMMAND_STATUS__VI         regSWRST_COMMAND_STATUS__VI;
typedef union SWRST_CONTROL_0__VI              regSWRST_CONTROL_0__VI;
typedef union SWRST_CONTROL_1__VI              regSWRST_CONTROL_1__VI;
typedef union SWRST_CONTROL_2__VI              regSWRST_CONTROL_2__VI;
typedef union SWRST_CONTROL_3__VI              regSWRST_CONTROL_3__VI;
typedef union SWRST_CONTROL_4__VI              regSWRST_CONTROL_4__VI;
typedef union SWRST_CONTROL_5__VI              regSWRST_CONTROL_5__VI;
typedef union SWRST_CONTROL_6__VI              regSWRST_CONTROL_6__VI;
typedef union SWRST_EP_COMMAND_0__VI           regSWRST_EP_COMMAND_0__VI;
typedef union SWRST_EP_CONTROL_0__VI           regSWRST_EP_CONTROL_0__VI;
typedef union SWRST_GENERAL_CONTROL__VI        regSWRST_GENERAL_CONTROL__VI;
typedef union SX_BLEND_OPT_CONTROL__VI         regSX_BLEND_OPT_CONTROL__VI;
typedef union SX_BLEND_OPT_EPSILON__VI         regSX_BLEND_OPT_EPSILON__VI;
typedef union SX_MRT0_BLEND_OPT__VI            regSX_MRT0_BLEND_OPT__VI;
typedef union SX_MRT1_BLEND_OPT__VI            regSX_MRT1_BLEND_OPT__VI;
typedef union SX_MRT2_BLEND_OPT__VI            regSX_MRT2_BLEND_OPT__VI;
typedef union SX_MRT3_BLEND_OPT__VI            regSX_MRT3_BLEND_OPT__VI;
typedef union SX_MRT4_BLEND_OPT__VI            regSX_MRT4_BLEND_OPT__VI;
typedef union SX_MRT5_BLEND_OPT__VI            regSX_MRT5_BLEND_OPT__VI;
typedef union SX_MRT6_BLEND_OPT__VI            regSX_MRT6_BLEND_OPT__VI;
typedef union SX_MRT7_BLEND_OPT__VI            regSX_MRT7_BLEND_OPT__VI;
typedef union SX_PS_DOWNCONVERT__VI            regSX_PS_DOWNCONVERT__VI;
typedef union SYMCLKA_CLOCK_ENABLE__VI         regSYMCLKA_CLOCK_ENABLE__VI;
typedef union SYMCLKB_CLOCK_ENABLE__VI         regSYMCLKB_CLOCK_ENABLE__VI;
typedef union SYMCLKC_CLOCK_ENABLE__VI         regSYMCLKC_CLOCK_ENABLE__VI;
typedef union SYMCLKD_CLOCK_ENABLE__VI         regSYMCLKD_CLOCK_ENABLE__VI;
typedef union SYMCLKE_CLOCK_ENABLE__VI         regSYMCLKE_CLOCK_ENABLE__VI;
typedef union SYMCLKF_CLOCK_ENABLE__VI         regSYMCLKF_CLOCK_ENABLE__VI;
typedef union SYMCLKG_CLOCK_ENABLE__VI         regSYMCLKG_CLOCK_ENABLE__VI;
typedef union SYS_GRBM_GFX_INDEX_DATA__VI      regSYS_GRBM_GFX_INDEX_DATA__VI;
typedef union SYS_GRBM_GFX_INDEX_SELECT__VI    regSYS_GRBM_GFX_INDEX_SELECT__VI;
typedef union TCC_DSM_CNTL__VI                 regTCC_DSM_CNTL__VI;
typedef union TCC_EDC_CNT__VI                  regTCC_EDC_CNT__VI;
typedef union TCC_EXE_DISABLE__VI              regTCC_EXE_DISABLE__VI;
typedef union TCP_ATC_EDC_GATCL1_CNT__VI       regTCP_ATC_EDC_GATCL1_CNT__VI;
typedef union TCP_CNTL2__VI                    regTCP_CNTL2__VI;
typedef union TCP_DSM_CNTL__VI                 regTCP_DSM_CNTL__VI;
typedef union TCP_EDC_CNT__VI                  regTCP_EDC_CNT__VI;
typedef union TCP_GATCL1_CNTL__VI              regTCP_GATCL1_CNTL__VI;
typedef union TCP_GATCL1_DSM_CNTL__VI          regTCP_GATCL1_DSM_CNTL__VI;
typedef union TDC_MV_AVERAGE__VI               regTDC_MV_AVERAGE__VI;
typedef union TDC_STATUS__VI                   regTDC_STATUS__VI;
typedef union TDC_VRM_LIMIT__VI                regTDC_VRM_LIMIT__VI;
typedef union TD_DSM_CNTL__VI                  regTD_DSM_CNTL__VI;
typedef union THM_TMON0_STATUS__VI             regTHM_TMON0_STATUS__VI;
typedef union THM_TMON1_STATUS__VI             regTHM_TMON1_STATUS__VI;
typedef union THM_TMON2_CSR_RD__VI             regTHM_TMON2_CSR_RD__VI;
typedef union THM_TMON2_CSR_WR__VI             regTHM_TMON2_CSR_WR__VI;
typedef union THM_TMON2_CTRL__VI               regTHM_TMON2_CTRL__VI;
typedef union THM_TMON2_CTRL2__VI              regTHM_TMON2_CTRL2__VI;
typedef union THM_TMON2_DEBUG__VI              regTHM_TMON2_DEBUG__VI;
typedef union THM_TMON2_INT_DATA__VI           regTHM_TMON2_INT_DATA__VI;
typedef union THM_TMON2_RDIL0_DATA__VI         regTHM_TMON2_RDIL0_DATA__VI;
typedef union THM_TMON2_RDIL10_DATA__VI        regTHM_TMON2_RDIL10_DATA__VI;
typedef union THM_TMON2_RDIL11_DATA__VI        regTHM_TMON2_RDIL11_DATA__VI;
typedef union THM_TMON2_RDIL12_DATA__VI        regTHM_TMON2_RDIL12_DATA__VI;
typedef union THM_TMON2_RDIL13_DATA__VI        regTHM_TMON2_RDIL13_DATA__VI;
typedef union THM_TMON2_RDIL14_DATA__VI        regTHM_TMON2_RDIL14_DATA__VI;
typedef union THM_TMON2_RDIL15_DATA__VI        regTHM_TMON2_RDIL15_DATA__VI;
typedef union THM_TMON2_RDIL1_DATA__VI         regTHM_TMON2_RDIL1_DATA__VI;
typedef union THM_TMON2_RDIL2_DATA__VI         regTHM_TMON2_RDIL2_DATA__VI;
typedef union THM_TMON2_RDIL3_DATA__VI         regTHM_TMON2_RDIL3_DATA__VI;
typedef union THM_TMON2_RDIL4_DATA__VI         regTHM_TMON2_RDIL4_DATA__VI;
typedef union THM_TMON2_RDIL5_DATA__VI         regTHM_TMON2_RDIL5_DATA__VI;
typedef union THM_TMON2_RDIL6_DATA__VI         regTHM_TMON2_RDIL6_DATA__VI;
typedef union THM_TMON2_RDIL7_DATA__VI         regTHM_TMON2_RDIL7_DATA__VI;
typedef union THM_TMON2_RDIL8_DATA__VI         regTHM_TMON2_RDIL8_DATA__VI;
typedef union THM_TMON2_RDIL9_DATA__VI         regTHM_TMON2_RDIL9_DATA__VI;
typedef union THM_TMON2_RDIR0_DATA__VI         regTHM_TMON2_RDIR0_DATA__VI;
typedef union THM_TMON2_RDIR10_DATA__VI        regTHM_TMON2_RDIR10_DATA__VI;
typedef union THM_TMON2_RDIR11_DATA__VI        regTHM_TMON2_RDIR11_DATA__VI;
typedef union THM_TMON2_RDIR12_DATA__VI        regTHM_TMON2_RDIR12_DATA__VI;
typedef union THM_TMON2_RDIR13_DATA__VI        regTHM_TMON2_RDIR13_DATA__VI;
typedef union THM_TMON2_RDIR14_DATA__VI        regTHM_TMON2_RDIR14_DATA__VI;
typedef union THM_TMON2_RDIR15_DATA__VI        regTHM_TMON2_RDIR15_DATA__VI;
typedef union THM_TMON2_RDIR1_DATA__VI         regTHM_TMON2_RDIR1_DATA__VI;
typedef union THM_TMON2_RDIR2_DATA__VI         regTHM_TMON2_RDIR2_DATA__VI;
typedef union THM_TMON2_RDIR3_DATA__VI         regTHM_TMON2_RDIR3_DATA__VI;
typedef union THM_TMON2_RDIR4_DATA__VI         regTHM_TMON2_RDIR4_DATA__VI;
typedef union THM_TMON2_RDIR5_DATA__VI         regTHM_TMON2_RDIR5_DATA__VI;
typedef union THM_TMON2_RDIR6_DATA__VI         regTHM_TMON2_RDIR6_DATA__VI;
typedef union THM_TMON2_RDIR7_DATA__VI         regTHM_TMON2_RDIR7_DATA__VI;
typedef union THM_TMON2_RDIR8_DATA__VI         regTHM_TMON2_RDIR8_DATA__VI;
typedef union THM_TMON2_RDIR9_DATA__VI         regTHM_TMON2_RDIR9_DATA__VI;
typedef union THM_TMON2_STATUS__VI             regTHM_TMON2_STATUS__VI;
typedef union UNIPHYA_CHANNEL_XBAR_CNTL__VI    regUNIPHYA_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYA_LINK_CNTL__VI            regUNIPHYA_LINK_CNTL__VI;
typedef union UNIPHYB_CHANNEL_XBAR_CNTL__VI    regUNIPHYB_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYB_LINK_CNTL__VI            regUNIPHYB_LINK_CNTL__VI;
typedef union UNIPHYC_CHANNEL_XBAR_CNTL__VI    regUNIPHYC_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYC_LINK_CNTL__VI            regUNIPHYC_LINK_CNTL__VI;
typedef union UNIPHYD_CHANNEL_XBAR_CNTL__VI    regUNIPHYD_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYD_LINK_CNTL__VI            regUNIPHYD_LINK_CNTL__VI;
typedef union UNIPHYE_CHANNEL_XBAR_CNTL__VI    regUNIPHYE_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYE_LINK_CNTL__VI            regUNIPHYE_LINK_CNTL__VI;
typedef union UNIPHYF_CHANNEL_XBAR_CNTL__VI    regUNIPHYF_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYF_LINK_CNTL__VI            regUNIPHYF_LINK_CNTL__VI;
typedef union UNIPHYG_CHANNEL_XBAR_CNTL__VI    regUNIPHYG_CHANNEL_XBAR_CNTL__VI;
typedef union UNIPHYG_LINK_CNTL__VI            regUNIPHYG_LINK_CNTL__VI;
typedef union UNIPHY_ANG_BIST_CNTL__VI         regUNIPHY_ANG_BIST_CNTL__VI;
typedef union UNIPHY_DEBUG__VI                 regUNIPHY_DEBUG__VI;
typedef union UNIPHY_IMPCAL_PSW_AB__VI         regUNIPHY_IMPCAL_PSW_AB__VI;
typedef union UNIPHY_IMPCAL_PSW_CD__VI         regUNIPHY_IMPCAL_PSW_CD__VI;
typedef union UNIPHY_IMPCAL_PSW_EF__VI         regUNIPHY_IMPCAL_PSW_EF__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED0__VI  regUNIPHY_MACRO_CNTL_RESERVED0__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED1__VI  regUNIPHY_MACRO_CNTL_RESERVED1__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED10__VI regUNIPHY_MACRO_CNTL_RESERVED10__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED11__VI regUNIPHY_MACRO_CNTL_RESERVED11__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED12__VI regUNIPHY_MACRO_CNTL_RESERVED12__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED13__VI regUNIPHY_MACRO_CNTL_RESERVED13__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED14__VI regUNIPHY_MACRO_CNTL_RESERVED14__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED15__VI regUNIPHY_MACRO_CNTL_RESERVED15__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED16__VI regUNIPHY_MACRO_CNTL_RESERVED16__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED17__VI regUNIPHY_MACRO_CNTL_RESERVED17__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED18__VI regUNIPHY_MACRO_CNTL_RESERVED18__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED19__VI regUNIPHY_MACRO_CNTL_RESERVED19__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED2__VI  regUNIPHY_MACRO_CNTL_RESERVED2__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED20__VI regUNIPHY_MACRO_CNTL_RESERVED20__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED21__VI regUNIPHY_MACRO_CNTL_RESERVED21__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED22__VI regUNIPHY_MACRO_CNTL_RESERVED22__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED23__VI regUNIPHY_MACRO_CNTL_RESERVED23__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED24__VI regUNIPHY_MACRO_CNTL_RESERVED24__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED25__VI regUNIPHY_MACRO_CNTL_RESERVED25__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED26__VI regUNIPHY_MACRO_CNTL_RESERVED26__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED27__VI regUNIPHY_MACRO_CNTL_RESERVED27__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED28__VI regUNIPHY_MACRO_CNTL_RESERVED28__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED29__VI regUNIPHY_MACRO_CNTL_RESERVED29__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED3__VI  regUNIPHY_MACRO_CNTL_RESERVED3__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED30__VI regUNIPHY_MACRO_CNTL_RESERVED30__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED31__VI regUNIPHY_MACRO_CNTL_RESERVED31__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED4__VI  regUNIPHY_MACRO_CNTL_RESERVED4__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED5__VI  regUNIPHY_MACRO_CNTL_RESERVED5__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED6__VI  regUNIPHY_MACRO_CNTL_RESERVED6__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED7__VI  regUNIPHY_MACRO_CNTL_RESERVED7__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED8__VI  regUNIPHY_MACRO_CNTL_RESERVED8__VI;
typedef union UNIPHY_MACRO_CNTL_RESERVED9__VI  regUNIPHY_MACRO_CNTL_RESERVED9__VI;
typedef union UNIPHY_PLL_CONTROL1__VI          regUNIPHY_PLL_CONTROL1__VI;
typedef union UNIPHY_PLL_CONTROL2__VI          regUNIPHY_PLL_CONTROL2__VI;
typedef union UNIPHY_PLL_FBDIV__VI             regUNIPHY_PLL_FBDIV__VI;
typedef union UNIPHY_PLL_SS_CNTL__VI           regUNIPHY_PLL_SS_CNTL__VI;
typedef union UNIPHY_PLL_SS_STEP_SIZE__VI      regUNIPHY_PLL_SS_STEP_SIZE__VI;
typedef union UNIPHY_POWER_CONTROL__VI         regUNIPHY_POWER_CONTROL__VI;
typedef union UNIPHY_REG_TEST_OUTPUT2__VI      regUNIPHY_REG_TEST_OUTPUT2__VI;
typedef union UNIPHY_TPG_CONTROL__VI           regUNIPHY_TPG_CONTROL__VI;
typedef union UNIPHY_TPG_SEED__VI              regUNIPHY_TPG_SEED__VI;
typedef union UNIPHY_TX_CONTROL1__VI           regUNIPHY_TX_CONTROL1__VI;
typedef union UNIPHY_TX_CONTROL2__VI           regUNIPHY_TX_CONTROL2__VI;
typedef union UNIPHY_TX_CONTROL3__VI           regUNIPHY_TX_CONTROL3__VI;
typedef union UNIPHY_TX_CONTROL4__VI           regUNIPHY_TX_CONTROL4__VI;
typedef union UNP_CRC_CONTROL__VI              regUNP_CRC_CONTROL__VI;
typedef union UNP_CRC_CURRENT__VI              regUNP_CRC_CURRENT__VI;
typedef union UNP_CRC_LAST__VI                 regUNP_CRC_LAST__VI;
typedef union UNP_CRC_MASK__VI                 regUNP_CRC_MASK__VI;
typedef union UNP_DEBUG__VI                    regUNP_DEBUG__VI;
typedef union UNP_DEBUG2__VI                   regUNP_DEBUG2__VI;
typedef union UNP_GRPH_CONTROL__VI             regUNP_GRPH_CONTROL__VI;
typedef union UNP_GRPH_CONTROL_EXP__VI         regUNP_GRPH_CONTROL_EXP__VI;
typedef union UNP_GRPH_DFQ_CONTROL__VI         regUNP_GRPH_DFQ_CONTROL__VI;
typedef union UNP_GRPH_DFQ_STATUS__VI          regUNP_GRPH_DFQ_STATUS__VI;
typedef union UNP_GRPH_ENABLE__VI              regUNP_GRPH_ENABLE__VI;
typedef union UNP_GRPH_FLIP_RATE_CNTL__VI      regUNP_GRPH_FLIP_RATE_CNTL__VI;
typedef union UNP_GRPH_INTERRUPT_CONTROL__VI   regUNP_GRPH_INTERRUPT_CONTROL__VI;
typedef union UNP_GRPH_INTERRUPT_STATUS__VI    regUNP_GRPH_INTERRUPT_STATUS__VI;
typedef union UNP_GRPH_PITCH_C__VI             regUNP_GRPH_PITCH_C__VI;
typedef union UNP_GRPH_PITCH_L__VI             regUNP_GRPH_PITCH_L__VI;
typedef union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__VI regUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__VI;
typedef union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI regUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI;
typedef union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI regUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI;
typedef union UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__VI regUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__VI;
typedef union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__VI regUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__VI;
typedef union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__VI regUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__VI;
typedef union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__VI regUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__VI;
typedef union UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__VI regUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__VI;
typedef union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__VI regUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__VI;
typedef union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI regUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__VI;
typedef union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI regUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__VI;
typedef union UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__VI regUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__VI;
typedef union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__VI regUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__VI;
typedef union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__VI regUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__VI;
typedef union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__VI regUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__VI;
typedef union UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__VI regUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__VI;
typedef union UNP_GRPH_STEREOSYNC_FLIP__VI     regUNP_GRPH_STEREOSYNC_FLIP__VI;
typedef union UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__VI regUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__VI;
typedef union UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__VI regUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__VI;
typedef union UNP_GRPH_SURFACE_ADDRESS_INUSE_C__VI regUNP_GRPH_SURFACE_ADDRESS_INUSE_C__VI;
typedef union UNP_GRPH_SURFACE_ADDRESS_INUSE_L__VI regUNP_GRPH_SURFACE_ADDRESS_INUSE_L__VI;
typedef union UNP_GRPH_SURFACE_OFFSET_X_C__VI  regUNP_GRPH_SURFACE_OFFSET_X_C__VI;
typedef union UNP_GRPH_SURFACE_OFFSET_X_L__VI  regUNP_GRPH_SURFACE_OFFSET_X_L__VI;
typedef union UNP_GRPH_SURFACE_OFFSET_Y_C__VI  regUNP_GRPH_SURFACE_OFFSET_Y_C__VI;
typedef union UNP_GRPH_SURFACE_OFFSET_Y_L__VI  regUNP_GRPH_SURFACE_OFFSET_Y_L__VI;
typedef union UNP_GRPH_SWAP_CNTL__VI           regUNP_GRPH_SWAP_CNTL__VI;
typedef union UNP_GRPH_UPDATE__VI              regUNP_GRPH_UPDATE__VI;
typedef union UNP_GRPH_X_END_C__VI             regUNP_GRPH_X_END_C__VI;
typedef union UNP_GRPH_X_END_L__VI             regUNP_GRPH_X_END_L__VI;
typedef union UNP_GRPH_X_START_C__VI           regUNP_GRPH_X_START_C__VI;
typedef union UNP_GRPH_X_START_L__VI           regUNP_GRPH_X_START_L__VI;
typedef union UNP_GRPH_Y_END_C__VI             regUNP_GRPH_Y_END_C__VI;
typedef union UNP_GRPH_Y_END_L__VI             regUNP_GRPH_Y_END_L__VI;
typedef union UNP_GRPH_Y_START_C__VI           regUNP_GRPH_Y_START_C__VI;
typedef union UNP_GRPH_Y_START_L__VI           regUNP_GRPH_Y_START_L__VI;
typedef union UNP_HW_ROTATION__VI              regUNP_HW_ROTATION__VI;
typedef union UNP_LB_DATA_GAP_BETWEEN_CHUNK__VI regUNP_LB_DATA_GAP_BETWEEN_CHUNK__VI;
typedef union UNP_TEST_DEBUG_DATA__VI          regUNP_TEST_DEBUG_DATA__VI;
typedef union UNP_TEST_DEBUG_INDEX__VI         regUNP_TEST_DEBUG_INDEX__VI;
typedef union UVD_CGC_CTRL2__VI                regUVD_CGC_CTRL2__VI;
typedef union UVD_CGC_MEM_CTRL__VI             regUVD_CGC_MEM_CTRL__VI;
typedef union UVD_CGC_UDEC_STATUS__VI          regUVD_CGC_UDEC_STATUS__VI;
typedef union UVD_JPEG_ADDR_CONFIG__VI         regUVD_JPEG_ADDR_CONFIG__VI;
typedef union UVD_LMI_ADDR_EXT2__VI            regUVD_LMI_ADDR_EXT2__VI;
typedef union UVD_LMI_RBC_IB_64BIT_BAR_HIGH__VI regUVD_LMI_RBC_IB_64BIT_BAR_HIGH__VI;
typedef union UVD_LMI_RBC_IB_64BIT_BAR_LOW__VI regUVD_LMI_RBC_IB_64BIT_BAR_LOW__VI;
typedef union UVD_LMI_RBC_IB_VMID__VI          regUVD_LMI_RBC_IB_VMID__VI;
typedef union UVD_LMI_RBC_RB_64BIT_BAR_HIGH__VI regUVD_LMI_RBC_RB_64BIT_BAR_HIGH__VI;
typedef union UVD_LMI_RBC_RB_64BIT_BAR_LOW__VI regUVD_LMI_RBC_RB_64BIT_BAR_LOW__VI;
typedef union UVD_LMI_RBC_RB_VMID__VI          regUVD_LMI_RBC_RB_VMID__VI;
typedef union UVD_LMI_SWAP_CNTL2__VI           regUVD_LMI_SWAP_CNTL2__VI;
typedef union UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__VI regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__VI;
typedef union UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__VI regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__VI;
typedef union UVD_LMI_VMID_INTERNAL__VI        regUVD_LMI_VMID_INTERNAL__VI;
typedef union UVD_LMI_VMID_INTERNAL2__VI       regUVD_LMI_VMID_INTERNAL2__VI;
typedef union UVD_LMI_VMID_INTERNAL3__VI       regUVD_LMI_VMID_INTERNAL3__VI;
typedef union UVD_MIF_CURR_ADDR_CONFIG__VI     regUVD_MIF_CURR_ADDR_CONFIG__VI;
typedef union UVD_MIF_RECON1_ADDR_CONFIG__VI   regUVD_MIF_RECON1_ADDR_CONFIG__VI;
typedef union UVD_MIF_REF_ADDR_CONFIG__VI      regUVD_MIF_REF_ADDR_CONFIG__VI;
typedef union UVD_MIF_SCLR_ADDR_CONFIG__VI     regUVD_MIF_SCLR_ADDR_CONFIG__VI;
typedef union UVD_PGFSM_CONFIG__VI             regUVD_PGFSM_CONFIG__VI;
typedef union UVD_PGFSM_READ_TILE1__VI         regUVD_PGFSM_READ_TILE1__VI;
typedef union UVD_PGFSM_READ_TILE2__VI         regUVD_PGFSM_READ_TILE2__VI;
typedef union UVD_PGFSM_READ_TILE3__VI         regUVD_PGFSM_READ_TILE3__VI;
typedef union UVD_PGFSM_READ_TILE4__VI         regUVD_PGFSM_READ_TILE4__VI;
typedef union UVD_PGFSM_READ_TILE5__VI         regUVD_PGFSM_READ_TILE5__VI;
typedef union UVD_PGFSM_READ_TILE6__VI         regUVD_PGFSM_READ_TILE6__VI;
typedef union UVD_PGFSM_READ_TILE7__VI         regUVD_PGFSM_READ_TILE7__VI;
typedef union UVD_POWER_STATUS__VI             regUVD_POWER_STATUS__VI;
typedef union UVD_SUVD_CGC_CTRL__VI            regUVD_SUVD_CGC_CTRL__VI;
typedef union UVD_SUVD_CGC_GATE__VI            regUVD_SUVD_CGC_GATE__VI;
typedef union UVD_SUVD_CGC_STATUS__VI          regUVD_SUVD_CGC_STATUS__VI;
typedef union UVD_UDEC_ADDR_CONFIG__VI         regUVD_UDEC_ADDR_CONFIG__VI;
typedef union UVD_UDEC_DBW_ADDR_CONFIG__VI     regUVD_UDEC_DBW_ADDR_CONFIG__VI;
typedef union UVD_UDEC_DB_ADDR_CONFIG__VI      regUVD_UDEC_DB_ADDR_CONFIG__VI;
typedef union VCE_LMI_CACHE_CTRL__VI           regVCE_LMI_CACHE_CTRL__VI;
typedef union VCE_LMI_CTRL__VI                 regVCE_LMI_CTRL__VI;
typedef union VCE_LMI_CTRL2__VI                regVCE_LMI_CTRL2__VI;
typedef union VCE_LMI_SWAP_CNTL__VI            regVCE_LMI_SWAP_CNTL__VI;
typedef union VCE_LMI_SWAP_CNTL1__VI           regVCE_LMI_SWAP_CNTL1__VI;
typedef union VCE_LMI_SWAP_CNTL2__VI           regVCE_LMI_SWAP_CNTL2__VI;
typedef union VCE_LMI_SWAP_CNTL3__VI           regVCE_LMI_SWAP_CNTL3__VI;
typedef union VCE_LMI_VCPU_CACHE_40BIT_BAR__VI regVCE_LMI_VCPU_CACHE_40BIT_BAR__VI;
typedef union VCE_RB_ARB_CTRL__VI              regVCE_RB_ARB_CTRL__VI;
typedef union VCE_RB_BASE_HI__VI               regVCE_RB_BASE_HI__VI;
typedef union VCE_RB_BASE_HI2__VI              regVCE_RB_BASE_HI2__VI;
typedef union VCE_RB_BASE_HI3__VI              regVCE_RB_BASE_HI3__VI;
typedef union VCE_RB_BASE_LO__VI               regVCE_RB_BASE_LO__VI;
typedef union VCE_RB_BASE_LO2__VI              regVCE_RB_BASE_LO2__VI;
typedef union VCE_RB_BASE_LO3__VI              regVCE_RB_BASE_LO3__VI;
typedef union VCE_RB_RPTR__VI                  regVCE_RB_RPTR__VI;
typedef union VCE_RB_RPTR2__VI                 regVCE_RB_RPTR2__VI;
typedef union VCE_RB_RPTR3__VI                 regVCE_RB_RPTR3__VI;
typedef union VCE_RB_SIZE__VI                  regVCE_RB_SIZE__VI;
typedef union VCE_RB_SIZE2__VI                 regVCE_RB_SIZE2__VI;
typedef union VCE_RB_SIZE3__VI                 regVCE_RB_SIZE3__VI;
typedef union VCE_RB_WPTR__VI                  regVCE_RB_WPTR__VI;
typedef union VCE_RB_WPTR2__VI                 regVCE_RB_WPTR2__VI;
typedef union VCE_RB_WPTR3__VI                 regVCE_RB_WPTR3__VI;
typedef union VCE_SOFT_RESET__VI               regVCE_SOFT_RESET__VI;
typedef union VCE_STATUS__VI                   regVCE_STATUS__VI;
typedef union VCE_SYS_INT_ACK__VI              regVCE_SYS_INT_ACK__VI;
typedef union VCE_SYS_INT_EN__VI               regVCE_SYS_INT_EN__VI;
typedef union VCE_SYS_INT_STATUS__VI           regVCE_SYS_INT_STATUS__VI;
typedef union VCE_UENC_DMA_DCLK_CTRL__VI       regVCE_UENC_DMA_DCLK_CTRL__VI;
typedef union VCE_VCPU_CACHE_OFFSET0__VI       regVCE_VCPU_CACHE_OFFSET0__VI;
typedef union VCE_VCPU_CACHE_OFFSET1__VI       regVCE_VCPU_CACHE_OFFSET1__VI;
typedef union VCE_VCPU_CACHE_OFFSET2__VI       regVCE_VCPU_CACHE_OFFSET2__VI;
typedef union VCE_VCPU_CACHE_SIZE0__VI         regVCE_VCPU_CACHE_SIZE0__VI;
typedef union VCE_VCPU_CACHE_SIZE1__VI         regVCE_VCPU_CACHE_SIZE1__VI;
typedef union VCE_VCPU_CACHE_SIZE2__VI         regVCE_VCPU_CACHE_SIZE2__VI;
typedef union VCE_VCPU_CNTL__VI                regVCE_VCPU_CNTL__VI;
typedef union VDDGFX_IDLE_CONTROL__VI          regVDDGFX_IDLE_CONTROL__VI;
typedef union VDDGFX_IDLE_EXIT__VI             regVDDGFX_IDLE_EXIT__VI;
typedef union VDDGFX_IDLE_PARAMETER__VI        regVDDGFX_IDLE_PARAMETER__VI;
typedef union VGA25_PPLL_ANALOG__VI            regVGA25_PPLL_ANALOG__VI;
typedef union VGA28_PPLL_ANALOG__VI            regVGA28_PPLL_ANALOG__VI;
typedef union VGA41_PPLL_ANALOG__VI            regVGA41_PPLL_ANALOG__VI;
typedef union VGT_DISPATCH_DRAW_INDEX__VI      regVGT_DISPATCH_DRAW_INDEX__VI;
typedef union VGT_TESS_DISTRIBUTION__VI        regVGT_TESS_DISTRIBUTION__VI;
typedef union VIEWPORT_START_SECONDARY__VI     regVIEWPORT_START_SECONDARY__VI;
typedef union VM_INIT_STATUS__VI               regVM_INIT_STATUS__VI;
typedef union VM_L2_BANK_SELECT_RESERVED_CID__VI regVM_L2_BANK_SELECT_RESERVED_CID__VI;
typedef union VM_L2_BANK_SELECT_RESERVED_CID2__VI regVM_L2_BANK_SELECT_RESERVED_CID2__VI;
typedef union VM_L2_CNTL4__VI                  regVM_L2_CNTL4__VI;
typedef union WB_DBG_MODE__VI                  regWB_DBG_MODE__VI;
typedef union WB_DEBUG_CTRL__VI                regWB_DEBUG_CTRL__VI;
typedef union WB_EC_CONFIG__VI                 regWB_EC_CONFIG__VI;
typedef union WB_ENABLE__VI                    regWB_ENABLE__VI;
typedef union WB_HW_DEBUG__VI                  regWB_HW_DEBUG__VI;
typedef union WB_SOFT_RESET__VI                regWB_SOFT_RESET__VI;
typedef union WD_DEBUG_REG10__VI               regWD_DEBUG_REG10__VI;
typedef union WD_DEBUG_REG6__VI                regWD_DEBUG_REG6__VI;
typedef union WD_DEBUG_REG7__VI                regWD_DEBUG_REG7__VI;
typedef union WD_DEBUG_REG8__VI                regWD_DEBUG_REG8__VI;
typedef union WD_DEBUG_REG9__VI                regWD_DEBUG_REG9__VI;
typedef union WD_QOS__VI                       regWD_QOS__VI;
typedef union XDMA_AON_TEST_DEBUG_DATA__VI     regXDMA_AON_TEST_DEBUG_DATA__VI;
typedef union XDMA_AON_TEST_DEBUG_INDEX__VI    regXDMA_AON_TEST_DEBUG_INDEX__VI;
typedef union XDMA_CLOCK_GATING_CNTL__VI       regXDMA_CLOCK_GATING_CNTL__VI;
typedef union XDMA_IF_BIF_STATUS__VI           regXDMA_IF_BIF_STATUS__VI;
typedef union XDMA_IF_STATUS__VI               regXDMA_IF_STATUS__VI;
typedef union XDMA_INTERRUPT__VI               regXDMA_INTERRUPT__VI;
typedef union XDMA_LOCAL_SURFACE_TILING1__VI   regXDMA_LOCAL_SURFACE_TILING1__VI;
typedef union XDMA_LOCAL_SURFACE_TILING2__VI   regXDMA_LOCAL_SURFACE_TILING2__VI;
typedef union XDMA_MC_PCIE_CLIENT_CONFIG__VI   regXDMA_MC_PCIE_CLIENT_CONFIG__VI;
typedef union XDMA_MEM_POWER_CNTL__VI          regXDMA_MEM_POWER_CNTL__VI;
typedef union XDMA_MSTR_CACHE__VI              regXDMA_MSTR_CACHE__VI;
typedef union XDMA_MSTR_CACHE_BASE_ADDR__VI    regXDMA_MSTR_CACHE_BASE_ADDR__VI;
typedef union XDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI regXDMA_MSTR_CACHE_BASE_ADDR_HIGH__VI;
typedef union XDMA_MSTR_CHANNEL_DIM__VI        regXDMA_MSTR_CHANNEL_DIM__VI;
typedef union XDMA_MSTR_CHANNEL_START__VI      regXDMA_MSTR_CHANNEL_START__VI;
typedef union XDMA_MSTR_CMD_URGENT_CNTL__VI    regXDMA_MSTR_CMD_URGENT_CNTL__VI;
typedef union XDMA_MSTR_CNTL__VI               regXDMA_MSTR_CNTL__VI;
typedef union XDMA_MSTR_HEIGHT__VI             regXDMA_MSTR_HEIGHT__VI;
typedef union XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__VI regXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__VI;
typedef union XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__VI regXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__VI;
typedef union XDMA_MSTR_LOCAL_SURFACE_PITCH__VI regXDMA_MSTR_LOCAL_SURFACE_PITCH__VI;
typedef union XDMA_MSTR_MEM_CLIENT_CONFIG__VI  regXDMA_MSTR_MEM_CLIENT_CONFIG__VI;
typedef union XDMA_MSTR_MEM_NACK_STATUS__VI    regXDMA_MSTR_MEM_NACK_STATUS__VI;
typedef union XDMA_MSTR_MEM_URGENT_CNTL__VI    regXDMA_MSTR_MEM_URGENT_CNTL__VI;
typedef union XDMA_MSTR_PCIE_NACK_STATUS__VI   regXDMA_MSTR_PCIE_NACK_STATUS__VI;
typedef union XDMA_MSTR_PERFMEAS_CNTL__VI      regXDMA_MSTR_PERFMEAS_CNTL__VI;
typedef union XDMA_MSTR_PERFMEAS_STATUS__VI    regXDMA_MSTR_PERFMEAS_STATUS__VI;
typedef union XDMA_MSTR_PIPE_CNTL__VI          regXDMA_MSTR_PIPE_CNTL__VI;
typedef union XDMA_MSTR_READ_COMMAND__VI       regXDMA_MSTR_READ_COMMAND__VI;
typedef union XDMA_MSTR_REMOTE_GPU_ADDRESS__VI regXDMA_MSTR_REMOTE_GPU_ADDRESS__VI;
typedef union XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI regXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__VI;
typedef union XDMA_MSTR_REMOTE_SURFACE_BASE__VI regXDMA_MSTR_REMOTE_SURFACE_BASE__VI;
typedef union XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI regXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__VI;
typedef union XDMA_MSTR_STATUS__VI             regXDMA_MSTR_STATUS__VI;
typedef union XDMA_MSTR_VSYNC_GSL_CHECK__VI    regXDMA_MSTR_VSYNC_GSL_CHECK__VI;
typedef union XDMA_PERF_MEAS_STATUS__VI        regXDMA_PERF_MEAS_STATUS__VI;
typedef union XDMA_PG_CONTROL__VI              regXDMA_PG_CONTROL__VI;
typedef union XDMA_PG_STATUS__VI               regXDMA_PG_STATUS__VI;
typedef union XDMA_PG_WDATA__VI                regXDMA_PG_WDATA__VI;
typedef union XDMA_RBBMIF_RDWR_CNTL__VI        regXDMA_RBBMIF_RDWR_CNTL__VI;
typedef union XDMA_SLV_CHANNEL_CNTL__VI        regXDMA_SLV_CHANNEL_CNTL__VI;
typedef union XDMA_SLV_CNTL__VI                regXDMA_SLV_CNTL__VI;
typedef union XDMA_SLV_FLIP_PENDING__VI        regXDMA_SLV_FLIP_PENDING__VI;
typedef union XDMA_SLV_MEM_CLIENT_CONFIG__VI   regXDMA_SLV_MEM_CLIENT_CONFIG__VI;
typedef union XDMA_SLV_MEM_NACK_STATUS__VI     regXDMA_SLV_MEM_NACK_STATUS__VI;
typedef union XDMA_SLV_PCIE_NACK_STATUS__VI    regXDMA_SLV_PCIE_NACK_STATUS__VI;
typedef union XDMA_SLV_RDRET_BUF_STATUS__VI    regXDMA_SLV_RDRET_BUF_STATUS__VI;
typedef union XDMA_SLV_READ_LATENCY_AVE__VI    regXDMA_SLV_READ_LATENCY_AVE__VI;
typedef union XDMA_SLV_READ_LATENCY_MINMAX__VI regXDMA_SLV_READ_LATENCY_MINMAX__VI;
typedef union XDMA_SLV_READ_LATENCY_TIMER__VI  regXDMA_SLV_READ_LATENCY_TIMER__VI;
typedef union XDMA_SLV_READ_URGENT_CNTL__VI    regXDMA_SLV_READ_URGENT_CNTL__VI;
typedef union XDMA_SLV_REMOTE_GPU_ADDRESS__VI  regXDMA_SLV_REMOTE_GPU_ADDRESS__VI;
typedef union XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI regXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__VI;
typedef union XDMA_SLV_SLS_PITCH__VI           regXDMA_SLV_SLS_PITCH__VI;
typedef union XDMA_SLV_WB_RATE_CNTL__VI        regXDMA_SLV_WB_RATE_CNTL__VI;
typedef union XDMA_SLV_WRITE_URGENT_CNTL__VI   regXDMA_SLV_WRITE_URGENT_CNTL__VI;
typedef union XDMA_TEST_DEBUG_DATA__VI         regXDMA_TEST_DEBUG_DATA__VI;
typedef union XDMA_TEST_DEBUG_INDEX__VI        regXDMA_TEST_DEBUG_INDEX__VI;

} // inline namespace Chip
} // namespace Gfx6
} // namespace Pal

#endif
